JP5017179B2 - Digital output circuit with failure detection function - Google Patents

Digital output circuit with failure detection function Download PDF

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JP5017179B2
JP5017179B2 JP2008139117A JP2008139117A JP5017179B2 JP 5017179 B2 JP5017179 B2 JP 5017179B2 JP 2008139117 A JP2008139117 A JP 2008139117A JP 2008139117 A JP2008139117 A JP 2008139117A JP 5017179 B2 JP5017179 B2 JP 5017179B2
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switch element
digital output
circuit
output circuit
failure
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JP2009290415A (en
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守 稲田
前田  徹
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Hitachi Ltd
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Description

本発明はフェールセーフ性が要求される高安全なシステムを構成するデジタル出力回路に関し、特に簡易な構成で、負荷に対して誤出力することなく故障検知が可能なデジタル出力回路に関するものである。   The present invention relates to a digital output circuit that constitutes a highly safe system that requires fail-safety, and more particularly to a digital output circuit that can detect a failure with a simple configuration without erroneous output to a load.

高い安全性が要求される鉄道信号制御システムでは、システムを構成する部品の故障といった不測の事態が生じても、システム全体を安全側の状態に遷移させるフェールセーフな構成の実現が必要不可欠である。鉄道信号制御システムに用いられ、信号機や転轍機といった現場機器を実際に制御する役割を担うデジタル出力回路においても、部品の故障で危険側動作することは許容されない。デジタル出力回路において、このフェールセーフ性を実現するためには、オン側出力が危険側動作、オフ側出力が安全側動作となるようにシステム全体を構築し、デジタル出力回路を構成する部品が故障した場合は出力がオフとなるよう回路を構成する必要がある。   In railway signal control systems that require high safety, it is indispensable to realize a fail-safe configuration that transitions the entire system to a safer state even if an unexpected situation such as a failure of the components that make up the system occurs. . Even in a digital output circuit that is used in a railway signal control system and plays a role of actually controlling field devices such as traffic lights and switches, it is not allowed to operate on the dangerous side due to a component failure. In order to achieve this fail-safety in the digital output circuit, the entire system is constructed so that the on-side output is on the dangerous side and the off-side output is on the safe side, and the components that make up the digital output circuit fail. In this case, it is necessary to configure the circuit so that the output is turned off.

このようなデジタル出力回路を実現する手段として2個のスイッチ素子を直列に接続する構成が一般に用いられる。2個のスイッチ素子を直列に接続した構成のデジタル出力回路では、スイッチ素子1個が短絡故障したとしても、他のスイッチ素子が正常である限り、誤ったオン出力といった危険側動作を引き起こさない。ただし、このスイッチ素子の短絡故障が検出できず故障を潜在化させてしまった場合、もう一方の正常であった側のスイッチ素子が短絡故障した際に誤出力してしまう。このため、このようなデジタル出力回路では各スイッチ素子に故障検知回路を設け、常時故障検知を行なうことによって故障の潜在化を防ぐことが一般に行なわれる。   As means for realizing such a digital output circuit, a configuration in which two switch elements are connected in series is generally used. In a digital output circuit having a configuration in which two switch elements are connected in series, even if one switch element is short-circuited, a dangerous operation such as an erroneous ON output is not caused as long as the other switch elements are normal. However, if this short circuit failure of the switch element cannot be detected and the failure is made latent, an error is output when the other normal switch element has a short circuit failure. For this reason, in such a digital output circuit, a failure detection circuit is generally provided in each switch element, and failure detection is generally prevented by performing failure detection at all times.

この故障検知方式の一例を図3に示す。図3のデジタル出力回路では2個のスイッチ素子の出力側に各々電圧検知回路を接続している。本回路構成においてスイッチ素子2の故障検出を行なう場合、スイッチ素子3をオフしたままスイッチ素子2をオン、オフさせる。スイッチ素子2をオンした状態で電圧検出回路4が電圧を検出、かつスイッチ素子2をオフした状態で電圧検出回路4が電圧を検出しなければスイッチ素子2は正常と判断し、これ以外の状態を異常と判断する。スイッチ素子3の故障検知はデジタル出力回路をオンに制御するタイミングで行なう。デジタル出力回路をオン制御する際、スイッチ素子2とスイッチ素子3を同時にオンさせるのではなく、スイッチ素子2、スイッチ素子3の順にオンさせる。スイッチ素子2がオンかつスイッチ素子3がオフの状態で電圧検知回路5が電圧を検出すれば異常、電圧を検出しなければ正常と判断する。   An example of this failure detection method is shown in FIG. In the digital output circuit of FIG. 3, a voltage detection circuit is connected to the output side of each of the two switch elements. In the case of detecting a failure of the switch element 2 in this circuit configuration, the switch element 2 is turned on and off while the switch element 3 is turned off. If the voltage detection circuit 4 detects a voltage with the switch element 2 turned on, and the voltage detection circuit 4 does not detect a voltage with the switch element 2 turned off, the switch element 2 is determined to be normal, and other states Is judged abnormal. The failure detection of the switch element 3 is performed at the timing when the digital output circuit is controlled to be turned on. When the digital output circuit is turned on, the switch element 2 and the switch element 3 are not turned on at the same time, but are turned on in the order of the switch element 2 and the switch element 3. If the voltage detection circuit 5 detects a voltage while the switch element 2 is on and the switch element 3 is off, it is judged abnormal, and if no voltage is detected, it is judged normal.

しかし、この方式ではデジタル出力回路をオン制御するタイミングでしかスイッチ素子3の故障検知が実行できず、デジタル出力回路を長時間オフしたままとするような用途ではスイッチ素子3の故障を潜在化させてしまう危険性がある。   However, in this method, the failure detection of the switch element 3 can be performed only at the timing when the digital output circuit is turned on, and the failure of the switch element 3 is made latent in an application where the digital output circuit is kept off for a long time. There is a risk that

本発明の目的は、簡易な構成で、負荷に対して誤出力することがなく、スイッチ素子の故障検知が任意のタイミングで可能な、デジタル出力回路を提供することにある。   An object of the present invention is to provide a digital output circuit that has a simple configuration, does not erroneously output to a load, and can detect a failure of a switch element at an arbitrary timing.

本発明のデジタル出力回路は、2個のスイッチ素子を直列に接続し、負荷に直流電圧を印加するデジタル出力回路であって、前記スイッチ素子の負荷側の出力端に、ダイオードと直流電源と電圧検知回路とを備えた故障検知回路接続され、前記ダイオードは、一端が2個のスイッチ素子の中間に接続され、且つ、他端が前記負荷に接続されたダイオード、及び、前記スイッチ素子の負荷側の出力端と前記負荷との間に接続された逆電圧印加防止用ダイオードから構成されることを特徴とする。
た、本発明のデジタル出力回路は、3個以上のスイッチ素子が直列に接続されていても良い。
Digital output circuit of the present invention is to connect two switching elements in series, a digital output circuit you apply a DC voltage to a load, the load side of the output end of the switching element, a diode and a DC power supply and A failure detection circuit having a voltage detection circuit is connected , and the diode has one end connected to the middle of two switch elements and the other end connected to the load; and It is characterized by comprising a reverse voltage application preventing diode connected between an output terminal on the load side and the load .
Also, the digital output circuit of the present invention, three or more switching elements may be connected in series.

本発明のデジタル出力回路は、簡易な構成で、負荷に対して誤出力することがなく、スイッチ素子の故障検知が任意のタイミングで可能である。   The digital output circuit of the present invention has a simple configuration, does not erroneously output to the load, and can detect a failure of the switch element at an arbitrary timing.

以下、本発明の実施の形態について図面を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は、本発明の構成を示す回路図である。図1において、デジタル出力回路は、2個の直列に接続されたスイッチ素子2及び3と、スイッチ素子2の出力端に接続された電圧検知回路4、スイッチ素子3の出力端に接続された電圧検知回路5及び直流電源6、スイッチ素子2、3の中間に接続されたダイオード7、負荷への逆電圧印加防止用ダイオード8とから成る。   FIG. 1 is a circuit diagram showing the configuration of the present invention. In FIG. 1, the digital output circuit includes two switch elements 2 and 3 connected in series, a voltage detection circuit 4 connected to the output terminal of the switch element 2, and a voltage connected to the output terminal of the switch element 3. It comprises a detection circuit 5, a DC power source 6, a diode 7 connected between the switch elements 2 and 3, and a diode 8 for preventing reverse voltage application to the load.

スイッチ素子2の故障検知はスイッチ素子3をオフした状態で行なう。スイッチ素子3をオフした状態でスイッチ素子2をオンした時、電圧検知回路4が電圧を検知すれば正常、電圧を検知しなければ異常と判断する。スイッチ素子2をオフした場合は逆に、電圧検知回路4が電圧を検知すれば異常、電圧を検知しなければ正常となる。   Fault detection of the switch element 2 is performed with the switch element 3 turned off. When the switch element 2 is turned on with the switch element 3 turned off, it is determined that the voltage detection circuit 4 is normal if the voltage is detected, and is abnormal if the voltage is not detected. On the contrary, when the switch element 2 is turned off, the voltage detection circuit 4 is abnormal if the voltage is detected, and is normal if the voltage is not detected.

スイッチ素子3の故障検知はスイッチ素子2をオフした状態で行なう。この状態でスイッチ素子3をオンすると電源6、ダイオード7、スイッチ素子3、電圧検知回路5からなる閉回路が成立する。この閉回路によって電圧検知回路5が電圧を検知すればスイッチ素子3は正常、電圧を検知しなければスイッチ素子3は異常である。スイッチ素子3をオフした場合は逆に、電圧検知回路5が電圧を検知すればスイッチ素子3は異常、電圧を検知しなければスイッチ素子3は正常である。   Fault detection of the switch element 3 is performed with the switch element 2 turned off. When the switch element 3 is turned on in this state, a closed circuit including the power source 6, the diode 7, the switch element 3, and the voltage detection circuit 5 is established. If the voltage detection circuit 5 detects a voltage by this closed circuit, the switch element 3 is normal, and if the voltage is not detected, the switch element 3 is abnormal. Conversely, when the switch element 3 is turned off, the switch element 3 is abnormal if the voltage detection circuit 5 detects the voltage, and the switch element 3 is normal if the voltage is not detected.

スイッチ素子2をオフした状態ではスイッチ素子3の出力端に電源6によって負電圧が印加されるが、ダイオード8により負荷には印加されず、負荷に影響を与えることはない。   In a state in which the switch element 2 is turned off, a negative voltage is applied to the output terminal of the switch element 3 by the power supply 6, but is not applied to the load by the diode 8 and does not affect the load.

図2は本発明を利用したデジタル出力回路の電子回路図である。図2の回路では、負荷9に対する出力をスイッチ素子2、3のオン、オフで制御する。このスイッチ素子は半導体でも機械接点式リレーでもよい。   FIG. 2 is an electronic circuit diagram of a digital output circuit using the present invention. In the circuit of FIG. 2, the output to the load 9 is controlled by turning on and off the switch elements 2 and 3. This switch element may be a semiconductor or a mechanical contact type relay.

スイッチ素子2、3の故障検知は以下の手順で行なう。まず、スイッチ素子2、3及び故障検知用スイッチ素子14をオフに制御する。この時、スイッチ素子2が短絡故障していれば、抵抗11、フォトカプラ10を経由して電流が流れ、端子17がGNDと同電位(以下、LOWレベルと表記する)になり、故障検知が可能である。次にスイッチ素子3をオフ制御したまま、スイッチ素子2をオン制御する。スイッチ素子2が開放故障していればフォトカプラ10に電流が流れないので、端子17はLOWレベルとならず故障と判断する。   The failure detection of the switch elements 2 and 3 is performed according to the following procedure. First, the switch elements 2 and 3 and the failure detection switch element 14 are controlled to be off. At this time, if the switch element 2 has a short-circuit failure, a current flows through the resistor 11 and the photocoupler 10, the terminal 17 becomes the same potential as GND (hereinafter referred to as LOW level), and failure detection is performed. Is possible. Next, the switch element 2 is turned on while the switch element 3 is turned off. If the switch element 2 has an open failure, no current flows through the photocoupler 10, so that the terminal 17 is not at the LOW level and is determined to be in failure.

以上の手順でスイッチ素子2の健全性を確認した後、スイッチ素子3の故障検知を行なう。スイッチ素子2、3をオフ制御した状態において故障検知用スイッチ素子14をオン制御する。もし、スイッチ素子3が短絡故障していれば、電源6からダイオード7、スイッチ素子3、抵抗13、フォトカプラ12、スイッチ素子14に電流が流れる。フォトカプラ12に電流が流れた結果、端子18がLOWレベルとなり、故障検知ができる。このときスイッチ素子3の出力端には電源6により負電圧が印加されるが、ダイオード8により遮断されるため、負荷には影響しない。次に、スイッチ素子2をオフ制御したまま、スイッチ素子3をオン制御する。スイッチ素子3が開放故障していれば、フォトカプラ12には電流が流れないので端子18はLOWレベルとならず、故障検知が可能である。   After confirming the soundness of the switch element 2 by the above procedure, the failure of the switch element 3 is detected. In a state where the switch elements 2 and 3 are turned off, the failure detection switch element 14 is turned on. If the switch element 3 has a short circuit failure, a current flows from the power source 6 to the diode 7, the switch element 3, the resistor 13, the photocoupler 12, and the switch element 14. As a result of the current flowing through the photocoupler 12, the terminal 18 becomes the LOW level, and the failure can be detected. At this time, a negative voltage is applied to the output terminal of the switch element 3 by the power supply 6 but is interrupted by the diode 8 so that the load is not affected. Next, the switch element 3 is turned on while the switch element 2 is turned off. If the switch element 3 has an open failure, no current flows through the photocoupler 12, so that the terminal 18 does not go to the LOW level and the failure can be detected.

以上の手順によりスイッチ素子2及び3の故障検知が実現できる。また、この故障検知の間を通じて、負荷に対して誤出力することがない。   The failure detection of the switch elements 2 and 3 can be realized by the above procedure. In addition, there is no erroneous output to the load during this failure detection.

故障検知を行なわない場合はスイッチ素子14をオフ制御する。このとき、抵抗13、フォトカプラ12、抵抗16、ダイオード15はデジタル出力回路の出力を取り込む出力リードバック回路として働く。抵抗13と抵抗16の比を適切に設定すれば、電源1と電源6の電圧が異なっていてもフォトカプラ12を流れる電流は一定とすることができ、回路の設計が容易になる。   When failure detection is not performed, the switch element 14 is turned off. At this time, the resistor 13, the photocoupler 12, the resistor 16, and the diode 15 function as an output readback circuit that captures the output of the digital output circuit. If the ratio of the resistor 13 and the resistor 16 is set appropriately, the current flowing through the photocoupler 12 can be kept constant even if the voltages of the power supply 1 and the power supply 6 are different, and the circuit design becomes easy.

以上の実施例では、スイッチ素子2,3の2個のスイッチ素子を直列に接続する例について説明したが、直列に接続されるスイッチ素子は、2個に限らず3個以上の場合にも同様に本発明を適用することができる。   In the above embodiment, an example in which the two switch elements 2 and 3 are connected in series has been described. However, the number of switch elements connected in series is not limited to two, and the same applies to the case of three or more switch elements. The present invention can be applied to.

図1は、本発明の構成を示す回路図である。FIG. 1 is a circuit diagram showing the configuration of the present invention. 図2は、本発明の実施例を示す電子回路図である。FIG. 2 is an electronic circuit diagram showing an embodiment of the present invention. 図3は、一般的な故障検知機能付デジタル出力回路図である。FIG. 3 is a general digital output circuit diagram with a failure detection function.

符号の説明Explanation of symbols

1 直流電源
2 スイッチ素子
3 スイッチ素子
4 電圧検知回路
5 電圧検知回路
6 直流電源
7 ダイオード
8 ダイオード
9 負荷
10 フォトカプラ
11 抵抗
12 フォトカプラ
13 抵抗
14 スイッチ素子
15 ダイオード
16 抵抗
17 端子
18 端子
DESCRIPTION OF SYMBOLS 1 DC power supply 2 Switch element 3 Switch element 4 Voltage detection circuit 5 Voltage detection circuit 6 DC power supply 7 Diode 8 Diode 9 Load 10 Photocoupler 11 Resistance
12 Photocoupler 13 Resistor 14 Switch element 15 Diode 16 Resistor 17 Terminal 18 Terminal

Claims (2)

2個のスイッチ素子を直列に接続し、負荷に直流電圧を印加するデジタル出力回路であって前記スイッチ素子の負荷側の出力端に、ダイオードと直流電源と電圧検知回路とを備えた故障検知回路接続され、前記ダイオードは、一端が2個のスイッチ素子の中間に接続され、且つ、他端が前記負荷に接続されたダイオード、及び、前記スイッチ素子の負荷側の出力端と前記負荷との間に接続された逆電圧印加防止用ダイオードから構成されることを特徴とするデジタル出力回路。 Connect the two switch elements in series, a digital output circuit you apply a DC voltage to a load, the load side of the output end of the switching element, and a diode and a DC power supply and the voltage detection circuit failure A detection circuit is connected , and the diode has one end connected in the middle of the two switch elements and the other end connected to the load, and an output end on the load side of the switch element and the load A digital output circuit comprising a diode for preventing reverse voltage application connected between and . 請求項1記載のデジタル出力回路において、3個以上のスイッチ素子が直列に接続されていることを特徴とするデジタル出力回路。 In the digital output circuit according to claim 1, the digital output circuit three or more switch elements, characterized in that it is connected to the series.
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JP2011130077A (en) * 2009-12-16 2011-06-30 Yokogawa Electric Corp Digital signal output circuit
JP5576849B2 (en) * 2011-12-09 2014-08-20 株式会社日立製作所 Digital output circuit with failure detection function
AT513940B1 (en) * 2013-01-22 2015-01-15 Siemens Ag Oesterreich Monitoring an electrical component
JP6120723B2 (en) * 2013-08-19 2017-04-26 株式会社日立製作所 Control circuit, control circuit short circuit fault detection method, switch control circuit short circuit fault detection method, and railway signal interlock control system
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