JP2009027872A - Semiconductor power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor power converter that prevents a spread of damage caused by a DC short circuit while having an interlock function for preventing the occurrence of short-circuit faults due to an erroneous gate pulse. <P>SOLUTION: A semiconductor power converter has a pair of switching elements, subjected to on/off control while having a mutually exclusive relationship therebetween, in each phase. The semiconductor power converter is provided with a gate control signal generation circuit 11 for generating a gate reference signal, a gate interlock means 101, which outputs a gate control signal 46 that shifts a switching element 31 from an off-state to an on-state only when the gate reference signal 41 is changed from an off-state to an on-state and a gate feedback signal 53 is in an off-state, and also, holds an on-state of the switching element 31 until the gate reference signal 41 is in an off-state after the switching element 31 is once in an on-state, and a gate interlock monitoring means 102 for detecting an abnormality of the switching elements by monitoring an operating state of the gate interlock means 101. When the gate interlock monitoring means 102 detects an abnormality, the gate reference signal is gate-blocked. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor power conversion device, and more particularly to a semiconductor power conversion device having a plurality of switching elements connected in series between positive and negative DC main circuits for each phase.

  Generally, in a semiconductor power conversion device having a plurality of switching elements connected in series between a positive potential end and a negative potential end in a DC main circuit for each phase, it is necessary to perform on / off control with a mutual reciprocal relationship When the positive and negative switching elements are simultaneously turned on, the DC main circuit positive potential end and the negative potential end are short-circuited, resulting in a device failure.

  In order to prevent this DC short-circuit failure, it has conventionally been provided to provide a gate interlock circuit in which the positive and negative switching elements that need to be controlled on and off with a reciprocal relationship are not simultaneously turned on. It was.

However, in the case of a normal gate interlock circuit, the same problem cannot be avoided if an erroneous pulse occurs due to the influence of noise or the like. For this reason, the gate reference signal of one of the positive side and negative side switching elements that need to be turned on and off with a reciprocal relationship using the gate pulse feedback means is switched from off to on and the other gate feedback signal A gate interlock that causes one switching element to transition from off to on only when the switch is off, and keeps the on state until the gate reference signal is turned off once this one switching element is turned on. A circuit has been proposed (see, for example, Patent Document 1).
JP 2002-165462 (page 4-5, FIG. 1)

  According to the technique disclosed in Patent Document 1, even when an erroneous detection pulse is generated in gate feedback due to noise or the like, it is possible to output a normal gate pulse without being affected by it. However, only using the gate interlock circuit disclosed in Patent Document 1 attempts to supply a normal gate pulse even if a switching element failure occurs, thereby preventing the spread of damage such as a DC short-circuit accident. There is a risk of not being able to.

  The present invention has been made in view of the above problems, and its object is to have a gate interlock function that does not cause a short-circuit fault or the like due to an erroneous gate pulse due to noise or the like, and to prevent the spread of damage due to a DC short-circuit accident. It is an object of the present invention to provide a semiconductor power conversion device that can be used.

  In order to achieve the above object, a semiconductor power conversion device according to a first aspect of the present invention includes at least a pair of switching devices connected in series between the positive and negative of a DC main circuit and controlled to be turned on and off with each other. In a semiconductor power conversion device having an element for each phase, a gate control signal generation circuit that generates a gate reference signal for on / off control of each of the switching elements, and a feedback signal according to the on / off state of each of the switching elements A gate feedback detection means for detecting the switching element, and the one switching element only when the gate reference signal of one of the pair of switching elements is turned on from off and the gate feedback signal of the other switching element is off. After switching from off to on and once turned on, the game Gate interlock means for converting the gate reference signal to output the gate control signal of the switching element so as to maintain the ON state of the switching element until the reference signal is turned off, and the operating state of the gate interlock means And a gate interlock monitoring means for detecting an abnormality of the switching element or its peripheral circuit, and when the gate interlock monitoring means detects an abnormality, the phase to which the switching element determined to be abnormal belongs. The gate reference signal of the switching element is gate-blocked.

  According to a second aspect of the present invention, there is provided a semiconductor power conversion device including, for each phase, at least a pair of switching elements connected in series between positive and negative of a DC main circuit and controlled to be turned on and off with respect to each other. And a gate control signal generating circuit for generating a gate reference signal for controlling on / off of each of the switching elements, and a gate feedback detection for detecting a feedback signal according to the on / off state of each of the switching elements. And one of the pair of switching elements is switched from off to on only when the gate reference signal of one of the pair of switching elements is turned on from off and the gate feedback signal of the other switching element is off. Once turned on, the gate reference signal is turned off. Gate interlock means for converting the gate reference signal to output the gate control signal of the switching element so as to maintain the ON state of the switching element until the gate output signal of each switching element is changed. A gate delay time monitoring means for monitoring a gate delay time until the feedback signal of the switching element changes to detect an abnormality of the switched element or its peripheral circuit, and the gate delay time monitoring means When a gate delay time of a predetermined value or more is detected, the gate reference signal of the switching element of the phase to which the switching element determined to be abnormal belongs is gate-blocked.

  According to the present invention, there is provided a semiconductor power conversion device that has a gate interlock function that does not cause a short-circuit failure or the like due to an erroneous gate pulse due to noise or the like, and that can prevent the spread of damage due to a DC short-circuit accident. Is possible.

Embodiments of the present invention will be described below with reference to the drawings.

  Hereinafter, a semiconductor power conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

  1 is a block configuration diagram of a semiconductor power conversion device according to a first embodiment of the present invention. In FIG. 1, one phase of a three-level inverter is illustrated as an example of a semiconductor power conversion device.

  Between the DC main circuit positive potential end 15 and the DC main circuit negative potential end 16, positive switching elements 31 and 32 and negative switching elements 33 and 34 are connected in series. Each of the switching elements 31, 32, 33, and 34 is usually composed of a self-extinguishing semiconductor element such as an IGBT and a diode connected in reverse parallel thereto, but may be an integral structure. A clamp diode 35 is connected to a connection point between the switching element 31 and the switching element 32 in a direction in which a current flows from the main circuit neutral point 17. Similarly, a connection point between the switching element 33 and the switching element 34. The clamp diode 36 is connected in the direction in which a current flows from the main circuit neutral point 17. An AC output voltage for one phase is obtained from the AC output end 18 that is a connection point between the switching element 32 and the switching element 33.

  The above is the main circuit configuration for one phase of the three-level inverter. If three main circuits for one phase are provided, a three-phase three-level inverter is formed.

  The configuration of the control circuit for controlling the main circuit for one phase of the three-level inverter will be described below.

  The gate control signal generation circuit 11 outputs gate reference signals 41, 42, 43 and 44 modulated by, for example, PWM control according to a voltage reference obtained by a main control unit (not shown). The gate reference signals 41, 42, 43 and 44 are supplied to the gate drive circuits 21, 22, 23 and 24 via the gate interlock circuit 101, respectively, and the outputs of the gate drive circuits 21, 22, 23 and 24 are the switching elements. The gates 31, 32, 33 and 34 are driven. Here, when one of the gate reference signal 41 and the gate reference signal 43 is turned on, the other is turned off so that the other is turned off. Similarly, the gate reference signal 42 and the gate reference signal 44 have a mutually opposite relationship.

  The on / off operation states of the gate drive circuits 21, 22, 23, and 24 are guided to the gate interlock circuit 101 as gate feedback signals 51, 52, 53, and 54, respectively.

  The gate interlock monitoring circuit 102 receives the status signal of the gate interlock circuit 101 as an input and monitors the presence or absence of the abnormality. When an abnormality is recognized, the gate interlock monitoring circuit 102 turns off a predetermined gate reference signal belonging to the relevant phase, All gate reference signals including the other phases of the gate control signal generation circuit 11 are gate-blocked via the circuit 12. The gate block circuit 12 also receives abnormal signals such as device overcurrent and device overvoltage.

  The internal configurations of the gate interlock circuit 101 and the gate interlock monitoring circuit 102 will be described below. First, the internal configuration of the gate interlock processing unit related to the gate reference signal 41 in the gate interlock circuit 101 will be described.

  The gate reference signal 41 is given to one input terminal of the AND circuit 71. An interlocked gate output signal 46, which is the output of the AND circuit 71, is supplied to the gate drive circuit 21, and the switching element 31 is on / off controlled. A gate feedback signal 53 is supplied from the gate drive circuit 23 to one input terminal of the OR circuit 81 through the NOT circuit 61. The output of the OR circuit 81 is given to the other input terminal of the AND circuit 71, and the switching element 31 is changed from OFF to ON only when the gate feedback signal 53 is OFF. The output signal of the AND circuit 71 is given to the other input terminal of the OR circuit 81. After the switching element 31 is once turned on, the ON state is maintained until the gate reference signal 41 is turned off. It is configured.

  The gate interlock processing units for the gate reference signals 42, 43 and 44 also basically have the same configuration as the gate interlock processing unit for the gate reference signal 41. That is, the gate reference signals 42, 43, and 44 are given to one input terminals of the AND circuits 72, 73, and 74, respectively. Interlocked gate output signals 47, 48, and 49, which are the outputs of the AND circuits 72, 73, and 74, are given to the gate drive circuits 22, 23, and 24, respectively, to control the switching elements 32, 33, and 34, respectively. . Gate feedback signals 54, 51 and 52 are supplied from the gate drive circuits 24, 21 and 22 to one input terminals of the OR circuits 82, 83 and 84 via NOT circuits 62, 63 and 64, respectively. The outputs of the OR circuits 82, 83 and 84 are respectively applied to the other input terminals of the above-mentioned AND circuits 72, 73 and 74, and only when the gate feedback signals 54, 51 and 52 are off, the switching elements 32, 33 and 34 is configured to transition from OFF to ON, respectively. The other input terminals of the OR circuits 82, 83 and 84 are supplied with output signals of the AND circuits 72, 73 and 74, respectively, and after the switching elements 32, 33 and 34 are once turned on, the gate reference signal 42 is supplied. , 43 and 44 are configured to hold their ON states until they are turned off.

  Next, the internal configuration of the gate interlock monitoring circuit 102 will be described. In this gate interlock monitoring circuit 102, gate reference signals 41, 42, 43 and 44, which are input signals of the gate interlock circuit 101, are applied to one input terminal of the EXOR circuits 91, 92, 93 and 94, respectively. Then, the gate output signals 46, 47, 48 and 49 after the interlock are supplied to the other input terminals of the EXOR circuits 91, 92, 93 and 94, respectively. With this configuration, the interlock detection signals 96, 97, 98, and 99 that are the outputs of the EXOR circuits 91, 92, 93, and 94 become 1 for the gate drive circuits 23, 24, 21, and 22. Is abnormal, or the switching elements 33, 34, 31 and 32 are abnormal. Therefore, the gate-off determination circuit 108 quickly turns off the gate of a predetermined switching element and blocks all other switching elements to prevent the accident from spreading. Here, the predetermined switching element means a switching element in which an excessive current flows in the switching element when left unattended, but the gate reference signal of all the switching elements in the phase is gate-blocked. You may make it do.

  The operation of the first embodiment in the configuration of one phase of the three-level inverter described above will be described according to the operation time chart shown in FIG.

  As shown in FIG. 2, first, the gate reference signals 41, 42, 43, and 44 are on, on, off, and off, respectively, and the gate output signals 46, 47, 48, and 49 after the interlock are before the interlock. Similarly, consider normal states that are on, on, off, and off, respectively. At this time, the gate feedback signal 51 is on.

  When the gate reference signal 41 is turned off at time t = T1, the interlocked gate output signal 46 is immediately turned off. The gate feedback signal 51 is turned off after a slight gate delay time. Next, at time t = T2, the gate reference signal 43 changes from off to on. At this time, since the gate reference signal 41 having an exclusive relationship with the gate reference signal 43 is OFF, the interlocked gate output signal 48 is also immediately turned ON.

  In the above state, it is assumed that the gate feedback signal 51 is turned on for a short time due to the influence of noise or the like at time t = T3. In this case, the gate output signal 48 after interlocking is kept on by the holding function as described above, and is not affected by the noise. As soon as the gate reference signal 43 changes from on to off at time t = T4, the interlocked gate output signal 48 changes from on to off. Further, when the gate reference signal 41 changes from OFF to ON at time t = T5, the gate feedback signal 53 corresponding to the gate reference signal 43 in the exclusive relationship is OFF, so the gate output signal 46 after the interlock is also immediately turned OFF. It becomes.

  Next, at time t = T6, the gate reference signal 41 changes from ON to OFF, and the interlocked gate output signal 46 also immediately changes from ON to OFF, and then the gate feedback signal 51 does not change from ON to OFF. For example, consider a case where the switching element 31 fails to shut off. In this state, the gate reference signal 43 tries to change from off to on at time t = T7. However, since the instant interlock detection signal 98 changes from OFF to ON when the gate reference signal 43 changes from OFF to ON, a gate block signal is output.

  As described above, in the gate interlock circuit 101, the gate reference signal of one of the positive side and negative side switching elements that need to be turned on and off with an exhaust relationship is switched from off to on, and the other gate feedback. Only when the signal is OFF, one switching element is changed from OFF to ON, and after this one switching element is turned ON, the ON state is maintained until the gate reference signal is turned OFF. The gate interlock monitoring circuit 102 prevents the accident from spreading by performing a gate block when the switching element fails.

  When the gate interlock monitoring circuit 102 is not provided, and the gate reference signal 43 is taken as an example, when the switching element 31 has an element failure such as an interruption failure, the gate drive circuit regardless of whether the gate reference signal 41 is on or off. Since the gate feedback signal 51 from 21 is turned on and the gate reference signal 43 is not turned on by the gate interlock circuit 101 while the gate feedback signal 51 is on, the DC short circuit and the element breakdown mode are Does not occur. However, when the gate reference signal 42 is not gate-blocked, the switching element 32 is normally turned on by the ON signal of the gate reference signal 42 at the next timing. Current continues to flow through the switching element and the load until an overcurrent level is reached. For this reason, depending on the state of the previous switching operation, an excessive load due to current and heat is imposed on the switching element 32, and the switching element 32 also breaks down and causes damage expansion.

  Since the EXOR circuit 93 of the gate interlock monitoring circuit 102 confirms the input / output difference of the gate interlock circuit 101, it is equivalent to monitoring the abnormality of the switching element or the gate substrate and other peripheral circuits. Therefore, as shown in FIG. 2, when the interlock detection signal 98, which is the output of the EXOR circuit 93, is turned on, a gate-off command is input to the gate control generation circuit 11 via the gate-off determination circuit 106, and the gate reference By performing an appropriate gate block that turns off 42, it is possible to prevent a failure of the positive side switching element 32 due to the abnormal load.

  In the first embodiment, since the input / output difference of the gate interlock circuit having the function of holding the gate reference signal is confirmed, not only is it not affected by the noise of the gate feedback signal, but also the gate delay time is reduced. There is a merit that is not affected.

  Further, since the gate interlock monitoring circuit has a simple circuit configuration that is attached to the gate interlock circuit as shown in FIG. 1, it is possible to realize an accident ripple prevention and protection function with good cost performance.

  Hereinafter, a semiconductor power conversion device according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4.

  FIG. 3 is a block diagram of a semiconductor power conversion device according to the second embodiment of the present invention. In the second embodiment, the same parts as those in the block configuration diagram of the semiconductor power conversion device according to the first embodiment of the present invention shown in FIG. The second embodiment differs from the first embodiment in that a gate delay time monitoring circuit 103 having a function of detecting an abnormality in the delay time of each gate reference signal is provided in place of the gate interlock monitoring circuit 102. . The internal configuration of the gate delay time monitoring circuit 103 is as follows.

  On / off delay time abnormality detectors 104, 105, each having the gate output signals 46, 47, 48 and 49 after the interlock as one input and the gate feedback signals 51, 52, 53 and 54 as the other inputs, respectively. 106 and 107 are provided, and the outputs of the on / off delay time abnormality detection units 104, 105, 106 and 107 are supplied to the gate-off determination circuit 108. Here, the on / off delay time abnormality detection units 104, 105, 106, and 107 receive the gate feedback signals 51, 52, 53 after the interlocked gate output signals 46, 47, 48, and 49 are input, respectively. And 54 are turned on / off, and 1 is output to the gate-off determination circuit 108 when each of the gate delay times exceeds a predetermined value.

  Since the gate delay time is determined from the characteristics of the switching element, the switching characteristics of the semiconductor element in the gate substrate in the gate drive circuit, and the control transmission delay time, it is usually a value within a substantially constant range regardless of the energized state of the switching element. It becomes. However, once a failure of a switching element or a failure of a peripheral circuit such as a gate substrate occurs, the gate delay time greatly deviates from a certain range during normal operation. Therefore, the above abnormality monitoring can be performed.

  The operation of the second embodiment in the configuration of one phase of the three-level inverter described above will be described according to the operation time chart shown in FIG.

  As shown in FIG. 4, first, the gate reference signals 41, 42, 43, and 44 are on, on, off, and off, respectively, and the gate output signals 46, 47, 48, and 49 after the interlock are before the interlock. Similarly, consider normal states that are on, on, off, and off, respectively. At this time, the gate feedback signal 51 is on.

  When the gate reference signal 41 is turned off at time t = T1, the interlocked gate output signal 46 is immediately turned off. At time t = T1D, the gate feedback signal 51 is turned off. In this case, the gate delay time is (T1D-T1). If this value is within the normal range, the output of the on / off delay time abnormality detection unit 91 is zero.

  The following operations at times t = T2, T4, and T5 are the same as the operations shown in the first embodiment in FIG.

  Next, at time t = T8, the gate reference signal 41 changes from on to off, and at time t = T8D, the gate feedback signal 51 turns off. At this time, the gate delay time (T8D-T8) deviates from the normal range. It shall be. At this time, the output of the on / off delay time abnormality detection unit 91 becomes 1, and the gate block operation is immediately performed.

  As described above, when the gate delay time between the gate output signal 46 and the gate feedback signal 51 is greatly different from the normal time, it is considered that the switching element 31 or the peripheral circuit of the gate substrate of the gate driving circuit 21 is abnormal. At this time, if the gate-off command is input to the gate control generation circuit 11 via the gate-off determination circuit 108 and an appropriate gate block is performed so as to turn off the gate reference signal 42, the above-described failure expansion can be prevented. Note that the gate reference signal 42 is prioritized as the gate reference signal to be the target of this gate block, but other gate reference signals may be simultaneously gate-blocked.

  According to the second embodiment, by setting the allowable gate delay time to the shortest in the practical range, it becomes possible to quickly detect the abnormality of the switching element or the peripheral circuit, and in some cases, the switching element itself in which the abnormality has occurred It is also possible to protect.

  As described above, in the first and second embodiments, the three-level inverter has been described as an example. However, if the semiconductor power conversion device is configured such that the pair of switching elements on the positive side and the negative side are controlled to be turned on and off with mutual exclusion. It is obvious that the present invention can be applied to a level, four levels or more, and a converter instead of an inverter.

BRIEF DESCRIPTION OF THE DRAWINGS The block block diagram of the semiconductor power converter device which concerns on Example 1 of this invention. The time chart for demonstrating operation | movement of the semiconductor power converter device which concerns on Example 1 of this invention. The block block diagram of the semiconductor power converter device which concerns on Example 2 of this invention. The time chart for demonstrating operation | movement of the semiconductor power converter device which concerns on Example 2 of this invention.

Explanation of symbols

11 Gate control signal generation circuit 12 Gate block circuit 15 DC main circuit positive potential end 16 DC main circuit negative potential end 17 Main circuit neutral point 18 AC output end

21, 22, 23, 24 Gate drive circuit 31, 32, 33, 34 Switching element 35, 36 Clamp diode 41, 42, 43, 44 Gate reference signal 46, 47, 48, 49 Gate output signal 51, 52, 53, 54 Gate feedback signal 61, 62, 63, 64 NOT circuit 71, 72, 73, 74 AND circuit 81, 82, 83, 84 OR circuit 91, 92, 93, 94 EXOR circuit 96, 97, 98, 99 Interlock detection signal

DESCRIPTION OF SYMBOLS 101 Gate interlock circuit 102 Gate interlock monitoring circuit 103 Gate delay time monitoring circuit 104,105,106,107 ON / OFF delay time abnormality detection part 108 Gate-off determination circuit

Claims (5)

A semiconductor power conversion device having at least a pair of switching elements connected in series between the positive and negative of the DC main circuit and controlled to be turned on and off with respect to each other for each phase,
A gate control signal generating circuit for generating a gate reference signal for controlling on / off of each of the switching elements;
Gate feedback detection means for detecting a feedback signal according to the on / off state of each of the switching elements;
Only when the gate reference signal of one of the pair of switching elements is turned off to on and the gate feedback signal of the other switching element is turned off, the one switching element is changed from off to on, and then once turned on. A gate interlock means for converting the gate reference signal and outputting the gate control signal of the switching element so as to maintain the ON state of the switching element until the gate reference signal is turned off.
Gate interlock monitoring means for monitoring the operating state of the gate interlock means and detecting an abnormality in the switching element or its peripheral circuit,
When the gate interlock monitoring means detects an abnormality, the gate reference signal of the switching element of the phase to which the switching element determined to be abnormal belongs is gate-blocked.   2. The semiconductor power conversion device according to claim 1, wherein when the gate interlock monitoring means detects an abnormality, the gate reference signals of all phases are gate-blocked. The gate interlock monitoring means includes
When the gate reference signal of each switching element and the gate control signal of the switching element converted by the gate interlock means are at different levels, the switching element that forms a pair with the switching element or its periphery The semiconductor power conversion device according to claim 1, wherein the circuit is determined to be abnormal. A semiconductor power conversion device having at least a pair of switching elements connected in series between the positive and negative of the DC main circuit and controlled to be turned on and off with respect to each other for each phase,
A gate control signal generating circuit for generating a gate reference signal for controlling on / off of each of the switching elements;
Gate feedback detection means for detecting a feedback signal according to the on / off state of each of the switching elements;
Only when the gate reference signal of one of the pair of switching elements is turned off to on and the gate feedback signal of the other switching element is turned off, the one switching element is changed from off to on, and then once turned on. A gate interlock means for converting the gate reference signal and outputting the gate control signal of the switching element so as to maintain the ON state of the switching element until the gate reference signal is turned off.
A gate delay time for monitoring the gate delay time from when the gate output signal of each switching element changes until the feedback signal of the switching element changes to detect an abnormality in the switched element or its peripheral circuit Monitoring means,
When the gate delay time monitoring means detects a gate delay time greater than or equal to a predetermined value, the gate reference signal of the switching element of the phase to which the switching element determined to be abnormal belongs is gate-blocked. Semiconductor power converter.   5. The semiconductor power conversion device according to claim 4, wherein when the gate delay time monitoring means detects an abnormality, the gate reference signals of all phases are gate-blocked.

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