JP5017153B2 - Asynchronous synchronous communication network conversion device, data conversion method, data conversion program, and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a conversion device for synchronous/asynchronous communication networks which is free from the breakdown of synchronization during communication for delivery of important data. <P>SOLUTION: A start up completion monitoring part 38 on the clock slave side, in response to detecting that a reception buffer clock control part 37 has cleared a reception buffer, transmits a packet showing that it is detected that the reception buffer has been cleared on the clock slave side, from a packet assembling part 26. A start up completion notification detecting part 39 on the clock master side, in response to detecting this packet through a packet disassembling part 38, instructs the reception buffer clock control part 37 to clear a reception buffer part 30. The reception buffer clock control part 37 on the clock master side generates a fixed clock from a variable clock part 32 and clears the reception buffer part 30 upon reception of the instruction from the start up completion notification detection part 39. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to an asynchronous synchronous communication network conversion apparatus, method, program, recording medium, and communication system for connecting legacy devices of a synchronous communication network to an IP communication network, which is an asynchronous communication network, and communicating between the legacy devices.

  Conventionally, there is a communication facility composed of a legacy device and a synchronous communication network. A synchronous communication network is mainly constructed using optical fibers, and voice, 2 Mbps MUX, ITU-T recommendation V. 24, X. Legacy data communication such as 21 is performed.

  In the legacy device of such a synchronous communication network, data communication synchronized with the clock is performed between each other by extracting the synchronous clock from the received data of the counterpart device.

  However, with regard to communication equipment configured with conventional legacy devices and synchronous communication networks, a change to an Internet protocol communication network (hereinafter referred to as an “IP communication network”) that is an asynchronous communication network is desired. This is because the communication infrastructure using optical fibers is used as an IP communication network rather than a synchronous communication network that can connect only special legacy devices that are expensive due to the fact that the product has already been manufactured and sold. However, the number of inexpensive devices that can be connected increases dramatically, and the introduction cost decreases. However, replacing the operating assets of legacy devices with inexpensive IP terminals can result in increased capital investment. Therefore, by introducing a conversion device capable of connecting legacy devices to the IP communication network, only the infrastructure can be transferred to the IP communication network.

  In order for conventional legacy devices to communicate, synchronous communication is realized by the opposing legacy devices being synchronized outside the communication network or by extracting a synchronization clock from received transmission data. On the other hand, in the case of an IP communication network, since this is a completely asynchronous communication network, a synchronous clock cannot be extracted from data, so that legacy devices cannot communicate synchronously.

  Therefore, synchronous communication (matching the interval of data transmitted by the legacy device on the data sending side with the interval of data received by the legacy device on the data receiving side) is possible between each legacy device and the IP communication network. A mechanism as shown in FIG. 10 in which an adapter (IP conversion device) is provided for practical use. FIG. 10 shows a state where such an IP conversion device is connected to the IP communication network. In FIG. 10, IP converters 102 and 103 are interposed between both legacy devices 100 and 101 that perform communication and an IP communication network 104, respectively.

One of the IP conversion apparatuses 102 is called a “clock master”, and receives data transmitted from a legacy device 100 connected thereto by an interface (legacy interface) 107 and receives a variable clock 109. Is sent to the IP network 104 according to a fixed clock supplied from the network. The other IP conversion apparatus 103 is called a “clock slave” and temporarily stores data received from the clock master 102 through the IP communication network in the reception buffer 105, and reads the data from the reception buffer 105 to read the legacy device 101. The period of the variable clock supplied to the interface (legacy interface) 106 to be transmitted is adjusted so that the amount of data staying in the reception buffer 105 is stabilized at just the intermediate value of the capacity of the reception buffer 105. . As a result, in spite of the fact that the IP communication network 104 does not have a function of performing synchronous communication, the clock master 102 captures data from the legacy device 100 and the clock slave 103 transmits data to the legacy device 101. It is possible to synchronize.

  Such synchronization is also performed in reverse communication. That is, the clock slave 103 receives the data sent from the legacy device 101 by the interface (legacy interface) 107 and sends it to the IP network 104 according to the variable clock of the same interval as that supplied to the interface 106. To do. The clock master 102 temporarily retains the data received from the clock master 102 through the IP communication network 104 in the reception buffer 105 and is supplied by the interface (legacy interface) 106 supplied with the same fixed clock as that supplied to the interface 107. It is read out and sent to the legacy device 100. This makes it possible to synchronize the cycle in which the clock slave 103 fetches from the legacy device 101 with the cycle in which the clock master 102 sends data to the legacy device 100.

  Both the IP conversion devices 102 and 103 have the same configuration. That is, when the IP converters 102 and 103 are set as clock slaves, the buffer monitoring variable clock control unit 108 that measures the amount of data staying in the reception buffer 105 (reception buffer amount) operates and is controlled thereby. The variable clock unit 109 supplies a variable clock controlled by the buffer monitoring variable clock control unit 108 to the interfaces 106 and 107. On the other hand, when the IP converters 102 and 103 are designated as clock masters, the buffer monitoring variable clock control unit 108 is stopped, and the variable clock unit 109 controlled thereby is connected to each interface 106 and 107. In contrast, a fixed clock is supplied.

Therefore, if the reception buffer amounts of the reception buffers 105 of both IP conversion apparatuses 102 and 103 match at the start of communication between both legacy devices 100 and 101, the clock slave 103 adjusts the variable clock. Thus, the reception buffer amount of the reception buffer 105 is adjusted so as to be stabilized just at the intermediate value of the capacity of the reception buffer 105, so that the reception buffer amount of the reception buffer 105 of the clock master 102 is also an intermediate value of the capacity of the reception buffer 105. The value should be stable.
JP-A-9-252292 JP 2002-217945 A

  However, at the start of communication, the reception buffer amount of the reception buffer 105 of the clock master 102 and the reception buffer amount of the reception buffer 105 of the clock slave 103 are the respective states at the time of connection (load of the IP communication network, communication line Depending on the failure, the state of the device, etc.), it is often quite different. For example, such a situation occurs when the timing after the start of communication is earlier than that of the clock slave 103 than that of the clock master 102.

  Therefore, even if the clock slave 103 adjusts the variable clock and the reception buffer amount of the reception buffer 105 is adjusted so as to be stabilized at an intermediate value of the capacity of the reception buffer 105, the reception of the reception buffer 105 of the clock master 102 is performed. The buffer amount may become stable near the upper limit value or the lower limit value of the capacity of the reception buffer 105.

  By the way, the reason why the reception buffer amount is stabilized at the intermediate value of the capacity of the reception buffer 105 is that fluctuations in the reception buffer amount inevitably occurring during communication are the same both in the direction in which the reception buffer amount increases and in the direction in which it decreases. It is because it can absorb to the extent.

  On the other hand, if the reception buffer amount becomes stable in the vicinity of the upper limit value, a slight fluctuation occurs in the direction in which the reception buffer amount increases, and overflow occurs and synchronization is broken. On the contrary, if the reception buffer amount becomes stable near the lower limit value, even if a slight fluctuation occurs in the direction in which the reception buffer amount decreases, the underflow occurs and the synchronization is broken.

  When synchronization failure occurs in this way, the reception buffers 105 of both IP conversion apparatuses 102 and 103 are once cleared, so that the reception buffer amounts of the reception buffers 105 of both IP conversion apparatuses 102 and 103 match. Since this is realized, the reception buffer amount of the reception buffer 105 of the clock master 102 is stabilized at an intermediate value of the capacity of the reception buffer 105 thereafter.

  FIG. 11 is a graph showing the state where the reception buffer amount of the reception buffer 105 of the clock master 102 is cleared due to an overflow as described above and then stabilized at the intermediate value, with the horizontal axis as the time axis. is there. That is, in FIG. 11, the reception buffer amount of the reception buffer 105 increases from the start of communication (a), and the adjustment of the variable clock in the clock slave 103 is started before and after the intermediate value (C0). When the rate of change decreases (b) and the reception buffer amount of the reception buffer 105 of the clock slave 103 stabilizes at an intermediate value, the reception buffer amount of the reception buffer 105 of the clock master 102 also stabilizes at any value. (C). However, for the reasons described above, the stable value is assumed to be in the vicinity of the upper limit value (Cmax). Then, after that, the reception buffer amount reaches the upper limit value (Cmax) only after the reception buffer amount is slightly fluctuated (overflow) (d). When this is automatically detected, the reception buffer 105 is cleared in both the IP conversion devices 102 and 103. As a result, the reception buffer amounts of the reception buffers 105 of both the IP converters 102 and 103 are forcibly made equal, so that when the reception buffer amount of the reception buffer 105 increases again thereafter (e), the clock slave 103 Similar to the above, the reception buffer amount of the reception buffer 105 of the clock master 102 is also stabilized at the intermediate value (C0).

  However, once an overflow occurs and synchronization fails, subsequent synchronization is guaranteed, but since this overflow occurs due to network fluctuations, it cannot be predicted when it will occur, and overflow is actually important. If this occurs during communications that exchange data, there is a problem that such important information is lost.

  Therefore, this proposal is an asynchronous synchronous communication in which synchronization is not broken in the middle of communication in which important data is being transferred by automatically executing a process (startup process) for clearing the reception buffers of both IP exchanges immediately after the start of communication. An object is to provide a network conversion device, a data conversion method, a data conversion program, and a communication system.

Using the asynchronous synchronous communication network conversion device, data conversion method, data conversion program, and communication system according to the present invention configured to achieve the above object, a synchronous communication network that transfers data in synchronization with a clock signal, respectively. A pair of conversion devices (computers) connected to the asynchronous communication network and connected to the asynchronous communication network composed of devices that asynchronously transfer data are respectively connected to a clock unit that outputs a clock at a specified interval. A synchronous communication data receiver that receives the synchronous communication data received from the synchronous communication device and transmits the synchronous communication data at intervals according to the clock supplied from the clock unit; and the synchronous communication transmitted from the synchronous communication data receiver A transmission converter that packetizes data and transmits it to the asynchronous communication network, a buffer, and a packet received from the asynchronous communication network. A synchronous converter that extracts synchronous communication data from the receiver and stores the synchronous communication data in the buffer; and synchronous communication that transmits the synchronous communication data read from the buffer to the synchronous communication device at intervals according to a clock supplied from the clock unit A data transmission unit. Further, one of the conversion devices monitors the amount of data in the buffer, executes a startup process for clearing the buffer at a predetermined timing after the start of communication, and then the amount of data in the buffer reaches a predetermined value. A buffer clock control unit for supplying a clock from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at an interval adjusted to be stable; and the buffer clock control unit includes the start-up process. And a startup monitoring unit that sends out a packet including a startup completion notification from the transmission conversion unit, and the other conversion device receives the synchronization from the clock unit at a predetermined fixed interval. Supply a clock to the communication data receiver and the synchronous communication data transmitter A buffer clock control unit that executes the startup process in response to a startup instruction; and detecting a packet including the startup completion notification in the packet received by the reception conversion unit, the buffer clock control unit A start-up completion notification detecting unit for instructing start-up.

  As a result, when the buffer clock control unit of one converter executes the startup process at a predetermined timing after the start of communication, the startup monitoring unit sends a packet including the start-up completion notification from the transmission converter to the other converter. Sent out. This packet is detected by the start-up completion notification detection unit in the other conversion device, and the buffer / clock control unit in the other conversion device executes the start-up process accordingly. As a result, the buffers of both converters are cleared almost simultaneously. Therefore, after that, the buffer / clock control unit of one converter converts the data amount in the buffer from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at an interval adjusted so as to be stabilized at a predetermined value. When control for supplying a clock is executed, both data in the buffer of the other conversion device are stabilized at a predetermined value. Therefore, even if a slight fluctuation of the data amount occurs, it is possible to prevent the synchronization from failing due to the buffer overflowing or underflowing.

  According to the present configuration configured as described above, it is possible to prevent unintentional communication failure during communication in which important data is being exchanged.

  FIG. 1 is an explanatory diagram of a communication system using a synchronous / asynchronous communication network conversion apparatus according to the present invention. In FIG. 1, legacy devices 10-1 and 10-2 as synchronous communication devices of a synchronous communication network are synchronous communication devices that perform synchronous communication of data using a synchronous communication network 11-1 constructed with, for example, an optical fiber. Voice, 2 Mbps MUX, ITU-T recommendation V. A device that performs legacy data communication, such as a multiplex transmission device such as 24, X21, is included.

  In order to connect the synchronous communication networks 11-1 and 11-2 including the legacy devices 10-1 and 10-2 to the IP network 18 including routers and switches as the asynchronous communication network 15, the synchronization of the present invention is performed. IP conversion devices 12-1 and 12-2, which are asynchronous communication network conversion devices, are inserted and connected between the legacy device 10-1. 10-2 and the IP network 18.

  In other words, the IP conversion device 12-1.12-2 of the present embodiment connects the legacy devices 10-1, 10-2 of the synchronous communication networks 11-1, 11-2 via the legacy networks 14-1, 14-2. In addition to the connection, the LAN 16-1.16-2 is connected to the IP network 18 which is the asynchronous communication network 15. A unique IP address is set for each of the IP conversion devices 12-1 and 12-2.

  Here, one of IP conversion apparatuses 12-1 and 12-2 of this embodiment is set in advance as a clock master, and the other is set as a clock slave. In the case of FIG. 1, the IP converter 12-1 is set as the clock master, and the IP converter 12-2 is set as the clock slave. However, the configuration of both IP converters 12-1 and 12-2 is exactly the same.

  That is, FIG. 2 is a block diagram showing a hardware configuration when the IP conversion apparatus 12 according to the present embodiment is configured based on a computer. In FIG. 2, the computer constituting the IP conversion apparatus 12 includes a CPU 36, a RAM 50, a ROM 52, a legacy interface unit 20, and an IP interface unit 22 that are connected to each other through a bus 48.

The ROM 52 stores the conversion program of this embodiment in addition to the BIOS and the OS. When you start the computer, by executing the RAM 50 of the BIOS, after the OS is read disposed RAM 5 0, conversion program of the present invention from the ROM52 with the OS is read into RAM 50, to be executed by the CPU 46.

  FIG. 3 is a block diagram showing the correlation between the functions of the IP conversion device 12 realized together with the interface units 20 and 20 and the RAM 50 when the CPU 46 shown in FIG. 2 executes the conversion program. Note that the IP conversion device 12 may be configured to have the circuit configuration shown in FIG. 3 by a sequencer or a logic circuit.

In FIG. 3, the IP conversion apparatus 12 of this embodiment includes a legacy interface unit 20, a packet assembly unit 26, a LAN interface unit 22, a packet disassembly unit 28, a reception buffer 30, a variable clock unit 32, and a control unit 34. .

  The control unit 34 is a function realized by execution of a program by the CPU, and includes a master / slave setting unit 36, a reception buffer / clock control unit 37, a startup completion monitoring unit 38, and a startup completion detection unit 39. .

  As shown in the communication system of FIG. 1, the master / slave setting unit 36 included in the control unit 34 sets in advance that the IP conversion device 12-1 should function as a clock master, and the IP conversion device 12- For 2, it is preset that it should function as a clock slave. Note that which IP conversion device is set as the clock master or the clock slave is determined every time communication is performed between the IP conversion devices 12 and 12 which are communication partners.

  When the master / slave setting unit 36 sets that the clock master should function, the function of the startup completion monitoring unit 38 is disabled and the function of the startup completion notification detection unit 39 is enabled. When the master slave setting unit 36 sets that the clock slave should function, the function of the startup completion monitoring unit 38 is enabled and the function of the startup completion notification detection unit 39 is disabled.

  The LAN interface unit 22 is an interface that sends the packet received from the packet assembly unit 26 to the LAN connected to the IP communication network 18 and passes the packet received from the LAN to the packet decomposition unit 28.

The packet assembling unit 26 has a function of assembling a packet by adding a header such as UDP / IP / MAC to the data received from the legacy interface 20 and passing it to the LAN interface unit 22. The LAN interface unit 22 and the packet assembly unit 26 correspond to a transmission conversion unit.

Packet decomposition unit 28, a packet received from the LAN interface unit 22, deletes the header, such as UDP / IP / MAC, a function to pass the remaining data to the reception buffer unit 30. The LAN interface unit 22 and the packet decomposition unit 28 correspond to a reception conversion unit.

  The reception buffer unit 30 is a buffer for temporarily storing data received from the packet decomposition unit 28. The reception buffer amount of the reception buffer unit 30 is detected by the function of the reception buffer / clock control unit 37 included in the control unit 34.

The variable clock unit (clock unit) 32 has a clock adjustment mechanism such as VCXO, and the IP conversion device 12 should function as a clock master according to the function of the reception buffer / clock control unit 37 included in the control unit 34. If it is set, a clock with a constant interval according to the standard is generated and supplied to the legacy interface unit 20, and if it is set that the IP converter 12 should function as a clock slave, Generate a clock at an interval specified by the clock control unit 37 and supply it to the legacy interface unit 20.

  The legacy interface unit 20 reads out data from the reception buffer unit 30 at a period synchronized with the clock supplied from the variable clock unit 32, and transmits the data to the legacy device (corresponding to a synchronous communication data transmission unit). The legacy interface unit 20 passes the data (synchronous communication data) received from the legacy device to the packet assembly unit 26 in a cycle synchronized with the clock supplied from the variable clock unit 32 (corresponding to a synchronous communication data receiving unit). ).

  The reception buffer / clock control unit (buffer / clock control unit) 37 included in the control unit (control unit) 34 is set so that the IP conversion device 12 should function as a clock master. The clock is supplied to the legacy interface 20 at the regular interval, so that the synchronous communication data received from the legacy device 10 is transferred to the packet assembly unit 26 by the IP interface unit 22 at the regular interval. 26, the packet assembled as the asynchronous communication data received from the IP network 18 is decomposed by the packet decomposing unit 28, and the extracted data is accumulated in the reception buffer 30. Legacy interface unit 20 at regular intervals It is sent to Luo legacy device 10.

  The reception buffer / clock control unit 37 included in the control unit 34 determines that the reception buffer amount of the reception buffer unit 30 from the start of communication when the IP converter 12 is set to function as a clock slave. Until the intermediate value (C0) of the capacity of the reception buffer unit 30 is reached, the clock output to the variable clock unit 32 is stopped, and when the intermediate value (C0) is reached, the variable clock signal is output at a predetermined center frequency f0. Is output to the legacy interface unit 20. However, if the interval at which the packet decomposing unit 28 writes to the receiving buffer unit 30 and the center frequency f0 are shifted, the receiving buffer amount gradually increases or decreases. The reception buffer / clock control unit 37 detects the reception buffer amount of the reception buffer unit 30 and adjusts the variable clock interval with respect to the reception buffer amount with respect to the variable clock unit 32.

That is, as shown in FIG. 4, when the reception buffer amount gradually increases, when the upper limit value (Cmax) is reached, the variable clock interval (hereinafter referred to as clock frequency) is set to the maximum value until the reception buffer amount returns to the intermediate value. (Fmax), when the reception buffer amount returns to the intermediate value (C0), the clock frequency is changed to a clock frequency that is slightly larger than the clock frequency set until the reception buffer amount reached the upper limit value immediately before. This cycle is repeated until the reception buffer amount is stabilized at the intermediate value (C0).

  On the other hand, as shown in FIG. 5, when the reception buffer amount gradually decreases, when the lower limit value (Cmin) is reached, the interval between the variable clocks (hereinafter referred to as clock frequency) until the reception buffer amount returns to the intermediate value. Is set to the minimum value (fmin), and when the reception buffer amount returns to the intermediate value (C0), the clock frequency is slightly smaller than the clock frequency set until the reception buffer amount reached the lower limit value immediately before. The cycle is changed until the reception buffer amount is stabilized at the intermediate value (C0).

  Then, the reception buffer / clock control unit 37 supplies the variable clock from the variable clock unit 32 to the legacy interface unit 20 in this way, so that the IP packet which is the asynchronous communication data received from the IP network 18 is converted into the packet decomposition unit. 28, the data accumulated in the reception buffer 30 is sent from the legacy interface unit 20 to the legacy device 10 at the variable clock interval, and the synchronous communication data received from the legacy device 10 is sent to the IP interface unit. The packet is transferred to the packet assembling unit 26 at the interval of the variable clock by 22 and the packet assembled by the packet assembling unit 26 is sent to the IP network 18.

  In addition to the above, the reception buffer / clock control unit 37 according to the present embodiment has an intermediate reception buffer amount after the start of communication when the IP converter 12 is set to function as a clock slave. Immediately after reaching the value (C0), the reception buffer 30 is once cleared, and until the amount of the reception buffer reaches the intermediate value (C0), the output of the variable clock is stopped and reaches the intermediate value (C0). Then, the output of the variable clock and the clock frequency adjustment described above are started. As described above, the output of the variable clock is stopped until immediately after that until the amount of the reception buffer reaches the intermediate value (C0), and the output of the variable clock is started once the intermediate value (C0) is reached. The process of clearing is called “startup”.

  The start-up completion monitoring unit 38, which is valid only in the IP converter 12 that should function as a clock slave, monitors the start-up execution by the reception buffer / clock control unit 37 as described above (FIG. 6: S02), and executes the start-up. Is not detected (FIG. 6: S02: No), the value “0” indicating that startup has not been completed is incorporated in the “completion status (see FIG. 8)” in the control data of the packet assembled by the packet assembly unit 26 (see FIG. 6). FIG. 6: S04). On the other hand, when the execution of startup is detected (FIG. 6: S02: Yes), the value “1” indicating the completion of startup is displayed in the “completion status (see FIG. 8)” in the control data of the packet assembled by the packet assembly unit 26. ”.

  The start-up completion notification detection unit 39, which is valid only in the IP conversion unit 12 that should function as the clock master, sets the value of “completion status (see FIG. 8)” in the control data of the packets sequentially received by the packet decomposition unit 28. When monitoring is performed (FIG. 7: S11) and a packet whose value of “completion status (see FIG. 8)” is “1” (FIG. 7: S11: Yes), the reception buffer / clock control unit 37 is A startup is instructed (FIG. 7: S12).

  The reception buffer / clock control unit 37 instructed to start up by the startup completion notification detection unit 39 once clears the reception buffer unit 30 and thereafter, the fixed clock from the variable clock unit 32 to the legacy interface unit 20 as before. Continue to supply.

According to the present embodiment configured as described above, in the IP conversion device 12 set to function as a clock slave, the reception buffer / clock control unit 37 sets the reception buffer amount after the start of communication to the intermediate value (C0). Until the intermediate value (C0) is reached, the output of the variable clock and the above-described clock frequency adjustment are started. However, once the amount of the reception buffer exceeds the intermediate value (C0), it is variable. When the clock is output, the packet is sent to the IP conversion device side on the clock master side (until then, the fixed data is output), so the reception buffer amount becomes the intermediate value (C0). Start up at the earliest possible timing after exceeding, and then variable until the reception buffer amount reaches the intermediate value (C0) after starting communication When the output of the lock is stopped and the intermediate value (C0) is reached, the output of the variable clock and the above-described clock frequency adjustment are restarted until the reception buffer amount is stabilized at the intermediate value as shown in FIGS. Adjust the clock frequency of the variable clock.

  On the other hand, in the IP converter 12 set to function as the clock master, the reception buffer / clock control unit 37 supplies the fixed clock from the variable clock unit 32 to the legacy interface unit 20 after the start of communication. Changes in the reception buffer amount of the unit 30 are as shown in FIGS. In the meantime, when the startup notification detection unit 39 detects a packet whose “completion status (see FIG. 8)” value is “1”, the reception buffer / clock control unit 37 clears (starts up) the reception buffer unit 30. Therefore, the reception buffer amount temporarily becomes the minimum value (Cmin). Thereafter, the reception buffer / clock control unit 37 causes the reception buffer / clock control unit 37 to supply the fixed clock from the variable clock unit 32 to the legacy interface unit 20, so that the reception buffer amount of the reception buffer unit 30 is increased from the clock slave. It rises depending on the amount of data transmitted (data transmission interval) (c in FIG. 9). However, since the buffer units 30 of both IP converters 12 are started up almost simultaneously, when the buffer unit 30 on the clock slave side becomes stable at the intermediate value, the buffer unit 30 on the clock master side also becomes the intermediate value. And become stable (d in FIG. 9).

  As described above, according to the present embodiment, loss of important data due to buffer overflow or underflow that occurs unintentionally can be prevented, and early stabilization of communication becomes possible.

  Further, even when the apparatus is not started up, an abnormality or the like of the IP communication network 18 occurs, and even when the recovery is performed from there, the reception buffer amounts of the reception buffer units 30 of both the IP conversion apparatuses 12 are almost the same when the LAN line is recovered. Therefore, very stable communication is possible.

  In addition, by inserting a completion status in the header portion of an IP packet that is already used in data communication, communication that does not limit the bandwidth becomes possible.

Block diagram of a communication system according to an embodiment Block diagram showing a hardware configuration of a computer constituting the IP conversion apparatus Block diagram showing the correlation of each function for operating the IP converter Time chart showing clock slave synchronization control of this embodiment when the amount of reception buffer increases at startup Time chart showing the clock slave synchronization control of this embodiment when the amount of reception buffer decreases at startup Flow chart showing the operation of the control unit on the clock slave side Flow chart showing operation of control unit on clock master side Diagram showing the structure of an IP packet The graph which shows the change of the receiving buffer amount by the side of a clock master in embodiment Block diagram showing a communication system to which an IP converter is connected The graph which shows the change of the receiving buffer amount in the conventional IP converter

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Legacy apparatus 12 IP converter 18 IP communication network 20 Legacy interface 22 IP interface part 26 Packet assembly part 28 Packet disassembly part 30 Reception buffer part 32 Variable clock part 34 Control part 37 Reception buffer clock control part 38 Startup completion monitoring part 39 Startup completion notification detector 46 CPU
52 ROM

Claims (5)

A synchronous communication device of a synchronous communication network that transfers data in synchronization with a clock signal is connected to an asynchronous communication network composed of devices that transfer data asynchronously, and the synchronous communication devices are mutually connected via the asynchronous communication network. Asynchronous synchronous communication network conversion device for transferring data to
A master-slave setting unit that sets either the clock master or the clock slave in relation to the conversion device of the other party,
A clock unit that outputs a clock at a specified interval;
A synchronous communication data receiving unit that receives the synchronous communication data received from the synchronous communication device, and transmits the synchronous communication data at intervals according to the clock supplied from the clock unit;
A transmission converter that packetizes the synchronous communication data sent from the synchronous communication data receiver and transmits the packet to the asynchronous communication network;
A buffer,
A reception conversion unit that extracts synchronous communication data from a packet received from the asynchronous communication network and stores it in the buffer;
A synchronous communication data transmitter for transmitting synchronous communication data read from the buffer to the synchronous communication device at intervals according to the clock supplied from the clock unit;
When set as a clock slave by the master-slave setting unit, the amount of data in the buffer is monitored, and a startup process is performed to clear the buffer at a predetermined timing after the start of communication. A clock is supplied from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at intervals adjusted so that the data amount is stabilized at a predetermined value, and the master slave setting unit causes the clock master to When set, a buffer for supplying a clock from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at a predetermined fixed interval and executing the start-up process in response to a start-up instruction・ Clock controller
This is valid when set as a clock slave by the master / slave setting unit, and when the buffer / clock control unit detects that the startup process has been executed, the startup conversion unit transmits a packet including a startup completion notification from the transmission conversion unit. A monitoring unit;
Effective when the master / slave setting unit sets the clock master, and detects a packet including the startup completion notification in the packet received by the reception conversion unit, the buffer / clock control unit receives the startup signal. A conversion apparatus for an asynchronous synchronous communication network, comprising: a start-up completion notification detection unit that issues an instruction. When the master / slave setting unit sets the buffer / clock control unit as a clock slave, the synchronous clock data from the clock unit until the data amount in the buffer reaches a predetermined value from the start of communication. The supply of the clock to the reception unit and the synchronous communication data transmission unit is stopped, and when the data amount reaches a predetermined value, the data from the buffer is adjusted so that the data amount in the buffer is stabilized at the predetermined value. After supplying the clock to the synchronous communication data receiving unit and the synchronous communication data transmitting unit and executing the startup process, again from the clock unit until the data amount in the buffer reaches a predetermined value The supply of the clock to the synchronous communication data receiving unit and the synchronous communication data transmitting unit is stopped, and the data amount is predetermined. The clock is supplied from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at intervals adjusted so that the amount of data in the buffer is stabilized at a predetermined value when The asynchronous synchronous communication network conversion device according to claim 1. A pair of conversions connected to each other through an asynchronous communication network composed of devices that transfer data asynchronously, as well as connected to a synchronous communication device of a synchronous communication network that transfers data in synchronization with a clock signal. A communication system comprising devices,
Each of the converters receives a clock unit that outputs a clock at an instructed interval, and synchronous communication data received from the synchronous communication device, and at an interval according to the clock supplied from the clock unit. A synchronous communication data receiving unit to be transmitted, a transmission conversion unit for packetizing the synchronous communication data transmitted from the synchronous communication data receiving unit and transmitting the packet to the asynchronous communication network, a buffer, and a packet received from the asynchronous communication network A reception conversion unit that extracts synchronous communication data and stores the synchronous communication data in the buffer, and synchronous communication data transmission that transmits the synchronous communication data read from the buffer to the synchronous communication device at intervals according to the clock supplied from the clock unit And further,
One of the conversion devices monitors the amount of data in the buffer, executes a startup process for clearing the buffer at a predetermined timing after the start of communication, and then stabilizes the amount of data in the buffer at a predetermined value. A buffer clock control unit for supplying a clock from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at intervals adjusted as described above, and the buffer clock control unit executes the startup process A start-up monitoring unit that sends a packet including a start-up completion notification from the transmission conversion unit,
The other conversion device supplies a clock from the clock unit to the synchronous communication data reception unit and the synchronous communication data transmission unit at a predetermined fixed interval, and executes a startup process in response to a startup instruction A clock control unit, and a startup completion notification detection unit that performs the startup instruction to the buffer clock control unit when a packet including the startup completion notification is detected in the packet received by the reception conversion unit. A communication system characterized by the above. Each of them is connected to a synchronous communication device of a synchronous communication network that transfers data in synchronization with a clock signal, and is connected to each other through an asynchronous communication network composed of devices that transfer data asynchronously. A clock unit for outputting a clock at an instructed interval; a synchronous communication data receiving unit for receiving synchronous communication data received from the synchronous communication device; and transmitting at an interval according to a clock supplied from the clock unit; The synchronous communication data sent from the synchronous communication data receiving unit is packetized and transmitted to the asynchronous communication network, the transmission conversion unit, the buffer, and the synchronous communication data is extracted from the packet received from the asynchronous communication network The reception conversion unit stored in the buffer and the same read out from the buffer at intervals according to the clock supplied from the clock unit. In a communication system comprising a pair of converters including a synchronous communication data transmission unit for transmitting communication data to the synchronous communication device, and a control unit for controlling the clock unit and the buffer, via the asynchronous communication network A data conversion method for transferring data between synchronous communication devices,
The control unit of one of the conversion devices performs a startup process for clearing the buffer at a predetermined timing after the start of communication while monitoring the amount of data in the buffer, and converts a packet including a startup completion notification to the transmission conversion The clock is supplied from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at intervals adjusted so that the amount of data in the buffer is stabilized at a predetermined value. ,
When the control unit of the other conversion device detects a packet including the start-up completion notification in the packet received by the reception conversion unit, the control unit executes the start-up process, and then from the clock unit at a predetermined fixed interval A data conversion method comprising: supplying a clock to the synchronous communication data receiving unit and the synchronous communication data transmitting unit. A clock unit for outputting a clock at an instructed interval; a synchronous communication data receiving unit for receiving synchronous communication data received from the synchronous communication device; and transmitting at an interval according to a clock supplied from the clock unit; The synchronous communication data sent from the synchronous communication data receiving unit is packetized and transmitted to the asynchronous communication network, the transmission conversion unit, the buffer, and the synchronous communication data is extracted from the packet received from the asynchronous communication network A computer having a reception conversion unit that accumulates in a buffer and a synchronous communication data transmission unit that transmits synchronous communication data read from the buffer to the synchronous communication device at intervals according to a clock supplied from the clock unit;
Master / slave setting unit that sets either the clock master or the clock slave in relation to the conversion device of the other party,
When set as a clock slave by the master-slave setting unit, the amount of data in the buffer is monitored, and a startup process is performed to clear the buffer at a predetermined timing after the start of communication. A clock is supplied from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at intervals adjusted so that the data amount is stabilized at a predetermined value, and the master slave setting unit causes the clock master to When set, a buffer for supplying a clock from the clock unit to the synchronous communication data receiving unit and the synchronous communication data transmitting unit at a predetermined fixed interval and executing the start-up process in response to a start-up instruction・ Clock controller,
This is valid when set as a clock slave by the master / slave setting unit, and when the buffer / clock control unit detects that the startup process has been executed, the startup conversion unit transmits a packet including a startup completion notification from the transmission conversion unit. A monitoring unit, and
Effective when the master / slave setting unit sets the clock master, and detects a packet including the startup completion notification in the packet received by the reception conversion unit, the buffer / clock control unit receives the startup signal. A data conversion program that functions as a start-up completion notification detection unit that gives instructions.

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