JPS63209343A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To attain bit buffer capacity in matching with jitter caused in a line by increasing the capacity of a bit buffer when the phase of a signal to latch a parallel signal and that of a reference clock signal are coincident. CONSTITUTION:When the phase of a signal 105 latched in a latch circuit 2 and that of a reference clock signal 106 are coincident and a binary '1' pulse is outputted from an AND circuit 10, the Q output of the FF circuit 11 changes from 0 to 1. Further, the inverse of Q output goes also from 1 to 0. Thus, a pulse is outputted from an AND circuit 13 and inputted to counters 6, 7, then the circuits 6, 7 are counted up. As a result, the period of the counter circuits 4, 5 is incremented by one and the capacity of the bit buffer is incremented by one bit. Thus, jitter of the actual circuit is detected to be added by the bit buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bit buffer circuit used for completely absorbing phase jitter of a received signal in a digital transmission system.

(Prior Art) In a conventional bit buffer circuit, a value whose capacity is calculated in advance is fixedly used.

(Problems to be Solved by the Invention) The capacity of the bit buffer is proportional to the magnitude of phase jitter, and if the capacity is thick, the amount of pit delay will also increase.

Therefore, in conventional fixed-capacity bit buffers, the capacity is calculated in advance, so if the actual line phase jitter is much smaller than the calculated value, unnecessary bit delay will occur. It has the disadvantage of being

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks, and to provide a bit buffer circuit in which the bit buffer capacity is set in accordance with the jitter occurring in an actual line.

(Means for Solving the Problems) In order to achieve the above object, the bit buffer circuit according to the present invention converts received signals into serial-parallel signals during a certain training time in a bit buffer circuit that absorbs phase jitter from received signals. A signal for latching the converted parallel signal and a signal for latching the parallel signal after conversion.
The phase difference of the reference clock signal for serial conversion is compared, and when the phase of the signal for launching the parallel signal and the reference clock signal match, the phase of the reference clock signal is shifted, and when they match again, the phase of the bit buffer is changed. It is constructed to increase capacity.

(Example) The present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a bit buffer circuit according to the present invention.

A reception clock signal 102 generated from a reception signal 101 operates a counter circuit 4 and is applied to an address signal 201'ii serial-parallel conversion circuit l. Serial-
The parallel conversion circuit Ml performs serial-to-parallel conversion on the received signal 101 and inputs the parallel signal to the latch circuit 2 via the signal line group 103i.

The counter circuit 4 outputs a clock signal 105'i.

The received signal 103 is applied to the latch circuit 2 via the signal line 105 and parallel-converted thereby, and is launched into the latch circuit 2.

A signal 112 is a read clock signal for the bit buffer, which operates the counter circuit 5 and provides the address signal 203' to the parallel-serial conversion circuit 3. The signal group 104 output from the latch circuit 2 is input to the parallel-serial circuit 3, subjected to parallel-to-serial conversion, and output to the signal line 113, resulting in a waveform with phase jitter absorbed.

A clock signal 105 outputted from the counter circuit 4 and caused to be latched by the latch circuit 2 is inputted to the AND circuit 10.

Furthermore, the read reference clock signal 106 output from the counter circuit 5 is also input to the AND circuit FNIIO.

When the phases of both the clock signal 105 for latch and the reference clock signal 106 match, the AND circuit 10
A pulse with a binary value of "1" is output and applied to two inputs of the flip-flop circuit 11. It is also input to the AND circuit 13.

The training time counter circuit 9 outputs a preset training time, and by outputting a binary value "1" to the signal line 107, the flip-flop circuit 11 is enabled to operate during that period. When the AND circuit 10 does not output the binary value "l", the flip-flop circuit 11 stands by in the state of Q="1" (108) and Q=O. The signal line 107 of the training time counter circuit 9 is also connected to one input of the AND circuit 13.

When a match is detected and a pulse with a binary value "l" is output from the AND circuit 10, the output Q of the flip-flop circuit 11
, Q is inverted. That is, Q=“0” and Q=“l”. When the Q output changes from l'' to 0'', the pulse generating circuit 8 generates a pulse and controls the counter circuit 5.

As a result, the reference clock signal 106 output from the counter circuit 5 is shifted, and the bit buffer is centered. Note that since the Q output changes from 0'' to 1'', no pulse is output from the AND circuit 13.

Next, when the phases of the signals 105 and 106 match again and the AND circuit 10 outputs a pulse with the binary value "'1", the Q output of the flip-flop circuit 11 changes from 0" to "l".
The Q output changes from 1" to 0". Therefore, a pulse is output from the AND circuit 13 and input to the counter circuits 6 and 7, so that the counter circuits 6 and 7 count up. As a result, the periods of the counter M4 and the counter circuit 5 increase by one, and the capacity of the bit buffer increases by one bit.

As described above, the jitter of the actual circuit is detected and a bit buffer is added.

The above operations are repeated throughout the training period.

(Effects of the Invention) As described above, the present invention compares a signal for causing a latch circuit to latch a received signal with a reference clock signal for parallel-to-serial conversion.

Since it is configured to increase the number of bit buffers in a predetermined procedure when there is a match, it is possible to set an appropriate value and has the effect of reducing the amount of unnecessary pit delay.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of a bit buffer circuit according to the present invention. 1... Serial-parallel conversion circuit 2... Latch circuit 3... Parallel-serial conversion circuit 4.5, 6.7... Counter circuit 8... Pulse generation circuit 9... Training time counter Circuit 10.13...
・AND circuit

Claims (1)

[Claims] In a bit buffer circuit that absorbs phase jitter from a received signal, during a certain training period, there are two signals: a signal for latching the parallel signal after serial-to-parallel conversion of the received signal, and a signal for latching the parallel signal after converting the received signal from parallel to serial. Compare the phase difference of the reference clock signals of
A bit buffer characterized in that when the signal for latching the parallel signal and the reference clock signal match in phase, the phase of the reference clock signal is shifted, and when they match again, the capacity of the bit buffer is increased. circuit.