JP5054993B2 - Conversion device, method, program, recording medium, and communication system for synchronous / asynchronous communication network - Google Patents

Description

The present invention relates to a synchronous asynchronous communication network conversion apparatus and method for connecting a legacy multiplex communication apparatus that synchronously transmits multiframe data in a synchronous communication network to an IP communication network that is an asynchronous communication network and communicating between legacy devices, Patent application title: PROGRAM, RECORDING MEDIUM, AND COMMUNICATION SYSTEM, CONVERSION DEVICE FOR SYNCHRONIZATION AND ASYNCHRONOUS COMMUNICATION NETWORK FOR COMMUNICING MULTI-FRAME DATA BETWEEN LAST MULTIPLE COMMUNICATION DEVICES OF SYNCHRONIZATION COMMUNICATION NETWORK WITHOUT SYNC , Method, program, recording medium, and communication system.

  Conventionally, there is a communication facility consisting of legacy equipment and a synchronous communication network. A synchronous communication network is mainly constructed with optical fibers, and multiple transmission devices such as 2.048 Mbps and 1.544 Mbps used for circuit switching are accommodated. In addition, legacy data communication for transmitting multi-channel data of a plurality of channels in synchronization with a clock signal is performed.

  In the legacy multiplex transmission device of such a synchronous communication network, data communication synchronized with the clock is performed between each other by extracting the synchronous clock from the received data of the counterpart device.

However, with regard to communication equipment configured with conventional legacy devices and synchronous communication networks, a change to an Internet protocol network (hereinafter referred to as “IP communication network”), which is an asynchronous communication network, is desired. This is because the optical fiber communication infrastructure is used as an IP communication network rather than a synchronous communication network in which only special legacy equipment, which is expensive due to the end of manufacture and sale of products, can be connected as a terminal. However, since the number of devices that can be connected has increased dramatically and the cost of the devices has decreased, it has become the mainstream in recent years.
JP-A-9-252292 JP 2002-217945 A

  However, in the case of a newly installed optical fiber, there is no problem, but in the case of an existing synchronous communication network in which a large amount of legacy equipment is already connected, for example, a communication facility in which a trunk optical fiber cable is installed along a highway, the synchronous communication network is changed to an asynchronous communication network. It is very difficult to change to the IP communication network, because all legacy multiplex transmission devices used for circuit switching, which are existing synchronous communication terminals, cannot be used.

  In other words, a synchronous clock can be extracted from transmission data in a synchronous communication network. However, in the case of an IP communication network, a synchronous clock cannot be extracted from data because it is a completely asynchronous communication network. Synchronous communication is not possible.

  In the case of an IP communication network, even if data is transmitted at regular intervals, data cannot be received at regular intervals due to delays or fluctuations in the communication network. It is very difficult to perform stable synchronous communication via the Internet. Even if legacy synchronous communication is realized via an IP communication network, a transmission error due to loss of synchronization regularly occurs or clock control occurs frequently frequently, and stable operation is not achieved.

  For this reason, when realizing synchronous communication between legacy devices in the IP communication network, it is assumed that the opposing legacy device is synchronized outside the IP communication network, and only between the IP communication network and the legacy device. It was difficult to realize the synchronous communication.

  In particular, when realizing synchronous communication between legacy multiplex communication devices used for circuit switching for transmitting multi-frame data of a plurality of channels in synchronization with a clock signal in an IP communication network, an IP packet in which multi-frame data is distributed in channels. As the IP packet is sent to the IP communication network, the reception state of the IP packet is random for each channel, and it is difficult to ensure synchronization only by the IP communication network, and synchronization is performed in units of channels by network synchronization outside the IP communication network. Therefore, the change to the IP communication network is made more difficult.

The present invention provides a synchronous asynchronous system that realizes stable synchronous communication between synchronous multiplex communication apparatuses by transmitting multi-frame data of a plurality of channels by a synchronous communication network to an IP communication network by channel distribution without requiring external network synchronization. It is an object of the present invention to provide a communication network conversion device, method, program, recording medium, and communication system.

(apparatus)
The present invention provides a conversion device for a synchronous asynchronous communication network. The present invention is inserted and connected between a synchronous multiplex communication apparatus that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that asynchronously transfer data, and a plurality of synchronous multiplex In a synchronous / asynchronous communication network converter for transferring data between communication devices,
Three sets of synchronous multiplex communication device and conversion device are grouped as one group, the master-slave relationship of clock synchronization of either clock master, first clock slave or second clock slave is set, and first and second clock slaves are set The conversion device sets a specific one channel among the assigned channels from the conversion device that has set the clock master as the first master channel, and the conversion device that sets the second clock slave starts from the conversion device that sets the first clock slave. A master / slave setting unit for setting a specific one of the assigned channels as the second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission converter that generates multi-frame data received from a synchronous multiplex communication apparatus and distributes the multi-frame data to each transmission buffer and then generates asynchronous transmission data from transmission buffer data and transmits the data to the asynchronous communication network at regular intervals. When,
Asynchronous data channel-distributed from the asynchronous communication network is received and accumulated in the reception buffer, and multi-frame data is generated from the accumulation data in the reception buffer in synchronization with the clock signal of the variable clock unit and transmitted to the synchronous multiplex communication device. A reception conversion unit;
A clock that is valid in the setting state of the clock master and is activated when the variable clock unit is fixed at a predetermined center frequency fo when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value. A master synchronization control unit;
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in each reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control unit for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value later, and synchronizing the clock with another conversion device in the setting state of the clock master;
It becomes effective in the setting state of the second clock slave, and when the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A second clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value, and to synchronize the clock with another conversion device in a setting state of the second clock slave;
It is provided with.

  Here, in the case where a plurality of conversion devices are formed as one group, a plurality of groups are constructed, and the conversion device in which the clock master is set is included as a common conversion device for all groups.

The first and second clock slave synchronization control units are
If the reception buffer amount C exceeds the upper limit value Cmax of the allowable range of buffer fluctuation after the clock frequency is started from the center frequency fo, it is changed to a predetermined maximum adjustment frequency fmax, and the reception buffer amount C returns to the center value fo after the change. The process of changing the maximum adjustment frequency fmax to the frequency (fo + α) obtained by adding the predetermined offset frequency α to the center frequency fo is repeated while sequentially increasing the offset frequencies as α, 2α, 3α,.
On the other hand, if the reception buffer amount C falls below the lower limit value Cmin of the buffer fluctuation allowable range after the clock frequency fo is started from the center frequency, the reception buffer amount C is changed to the predetermined minimum adjustment frequency fmin. The process of changing the minimum adjustment frequency fmin to the frequency (fo-α) obtained by subtracting the predetermined offset frequency α from the center frequency fo is sequentially increased as α, 2α, 3α,. Repeat while.

  The conversion device of the present invention is further effective in the setting state of the second clock slave, measures the packet reception density of the second master channel, and when the abnormality detection state of the packet reception density continues for a predetermined time, the reception buffer amount A clock master monitoring unit is provided for switching the reception buffer for measuring from the reception buffer of the second master channel to the reception buffer of the first master channel.

  The clock master monitoring unit measures the number of packets received per unit time as the packet density.

  The clock master monitoring unit sequentially activates a plurality of counters at a time interval T2 shorter than the unit time T1, counts the number of packets in parallel, and sequentially updates the packet density according to the number of packets of the counter reaching the unit time.

  The clock master monitoring unit switches from the current reception buffer to the reception buffer before switching when detecting a packet reception density abnormality measured for the reception buffer after switching after switching to the reception buffer by detecting the packet reception density abnormality. return.

  After switching to the reception buffer due to packet reception density abnormality detection, the clock master monitoring unit receives the pre-switching reception from the current reception buffer when the normal detection state of the packet reception density of the reception buffer before switching continues for a predetermined time. Return to buffer.

  The synchronous multiplex communication device is a device having a legacy interface, and the asynchronous communication network device is a device having an IP interface.

(Method)
The present invention provides a conversion method for a conversion apparatus. The present invention is inserted and connected between a synchronous multiplex communication apparatus that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that asynchronously transfer data, and a plurality of synchronous multiplex In a conversion method of a conversion device for transferring data between communication devices,
Three sets of the synchronous multiplex communication device and the conversion device are grouped as one group, and the clock synchronization dependency of the clock master, the first clock slave or the second clock slave is set, and the first and second clock slaves are set. The converting apparatus sets a specific one channel among the allocated channels from the converting apparatus that has set the clock master as the first master channel, and the converting apparatus that sets the second clock slave sets the first clock slave. A master-slave setting step of setting a specific one channel among the assigned channels from the converted converter as the second master channel;
A transmission conversion step of generating asynchronous transmission data from the accumulated data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network after the multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer; ,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
The clock master that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value. A synchronous control step;
It becomes effective in the setting state of the first clock slave, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with another conversion device in the set state of the clock master;
It becomes effective in the setting state of the second clock slave, and when the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A second clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with another conversion device in the setting state of the second clock slave;
It is provided with.

(program)
The present invention provides a program executed by a computer of a conversion apparatus. The program of the present invention is inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network configured by devices that transfer data asynchronously. To a computer of a conversion device that transfers data between synchronous multiplex communication devices,
Three sets of the synchronous multiplex communication device and the conversion device are grouped as one group, and the clock synchronization dependency of the clock master, the first clock slave or the second clock slave is set, and the first and second clock slaves are set. The converting apparatus sets a specific one channel among the allocated channels from the converting apparatus that has set the clock master as the first master channel, and the converting apparatus that sets the second clock slave sets the first clock slave. A master-slave setting step of setting a specific one channel among the assigned channels from the converted converter as the second master channel;
A transmission conversion step of generating asynchronous transmission data from the accumulated data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network after the multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer; ,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
The clock master that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value. A synchronous control step;
It becomes effective in the setting state of the first clock slave, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with another conversion device in the set state of the clock master;
It becomes effective in the setting state of the second clock slave, and when the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A second clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with another conversion device in the setting state of the second clock slave;
Is executed.

(recoding media)
The present invention provides a recording medium storing a program. The recording medium of the present invention is inserted and connected between a synchronous multiplex communication apparatus that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network configured by devices that transfer data asynchronously. A computer of a conversion device for transferring data between the synchronous multiplex communication devices of
Three sets of the synchronous multiplex communication device and the conversion device are grouped as one group, and the clock synchronization dependency of the clock master, the first clock slave or the second clock slave is set, and the first and second clock slaves are set. The converting apparatus sets a specific one channel among the allocated channels from the converting apparatus that has set the clock master as the first master channel, and the converting apparatus that sets the second clock slave sets the first clock slave. A master-slave setting step of setting a specific one channel among the assigned channels from the converted converter as the second master channel;
A transmission conversion step of generating asynchronous transmission data from the accumulated data in the transmission buffer at regular intervals and transmitting it to the asynchronous communication network after the multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer; ,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. Receiving conversion step,
The clock master that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value. A synchronous control step;
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A first clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value later, and synchronizing the clock to another conversion device in the setting state of the clock master;
It becomes effective in the setting state of the second clock slave, and when the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started. A second clock slave synchronization control step of controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with another conversion device in the setting state of the second clock slave;
A second reception buffer that measures the reception buffer amount when the packet reception density of the second master channel is measured in the setting state of the second clock slave and the abnormality detection state of the packet reception density continues for a predetermined time. A clock master monitoring step of switching from the reception buffer of the master channel to the reception buffer of the first master channel;
A program for executing is stored.

(system)
The present invention provides a communication system. The present invention
A master converter set as a clock master connected to an asynchronous communication network composed of devices that asynchronously transfer data to a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal;
A first slave conversion device in which another synchronous multiplex communication device is set as a first clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a first master channel;
A second slave conversion device in which another synchronous multiplex communication device is set as a second clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a second master channel;
In a communication system for transferring data between a plurality of synchronous multiplex communication devices,
Master converter is
A master-slave setting unit that sets the clock master in itself, with three sets of the synchronous multiplex communication device and the conversion device as one group,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission conversion unit that generates multi-frame data received from the synchronous multiplex communication device by channel distribution and accumulates in each transmission buffer, then generates asynchronous transmission data from the accumulated data in the transmission buffer at regular intervals and transmits the data to the asynchronous communication network; ,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
The clock master that is enabled in the setting state of the clock master and starts the variable clock unit at a predetermined center frequency when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value. A synchronization controller;
With
The first slave converter is
Master that sets three groups of synchronous multiplex communication device and conversion device as one group, sets a first clock slave to itself, and sets a specific one channel among assigned channels from the clock master conversion device as a first master channel A slave setting section;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission converter that generates multi-frame data received from a synchronous multiplex communication apparatus and distributes the multi-frame data to each transmission buffer and then generates asynchronous transmission data from transmission buffer data and transmits the data to the asynchronous communication network at regular intervals. When,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
When the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started, and after the start, the reception buffer amount is stabilized at the center value. A first clock slave synchronization control unit that controls the clock frequency of the variable clock unit to synchronize the clock with another communication system in the set state of the clock master;
With
The second slave converter is
Three sets of conversion devices are set as one group, and the second clock slave is set in itself, and one specific channel among the assigned channels from the clock master conversion device is set as the first master channel, and the first clock slave conversion is performed. A master / slave setting unit for setting a specific one of the allocated channels from the device as the second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
A transmission converter that generates multi-frame data received from a synchronous multiplex communication apparatus and distributes the multi-frame data to each transmission buffer and then generates asynchronous transmission data from transmission buffer data and transmits the data to the asynchronous communication network at regular intervals. When,
Asynchronous data distributed from the asynchronous communication network is received and stored in each receive buffer. Multiframe data is generated from the stored data in the receive buffer in synchronization with the clock signal of the variable clock unit, and transmitted to the synchronous multiplex communication device. A receiving conversion unit,
When the reception buffer amount stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and started, and after startup, the reception buffer amount is stabilized at the center value. A second clock slave synchronization control unit configured to control the clock frequency of the variable clock unit to synchronize the clock with another communication system in the setting state of the second clock slave,
A second reception buffer that measures the reception buffer amount when the packet reception density of the second master channel is measured in the setting state of the second clock slave and the abnormality detection state of the packet reception density continues for a predetermined time. A clock master monitoring unit for switching from the reception buffer of the master channel to the reception buffer of the first master channel is provided.

  According to the present invention, the conversion device of the present invention is inserted between a synchronous multiplex communication device, which is a legacy device that synchronously communicates multi-channel data of a plurality of channels, and an IP communication network, which is an asynchronous communication network, and three conversion devices are provided. By setting the clock master, the first clock slave, and the second clock slave as a group, the converter that has set the first clock slave is synchronized with the clock of the converter that has set the clock master, and the first Cascade synchronization can be realized in which the converter that has set the second clock slave is clock-synchronized with the clock of the converter that has set the clock slave.

  In addition, the clock synchronization control of the conversion apparatus in which the first and second clock slaves are set is such that the reception buffer amount of a specific channel that accumulates packet data that has been distributed and transmitted from the conversion apparatus on the clock master side is set to a specified value (center value). By adjusting the clock frequency to be stabilized (learning processing), the clock slave side can be artificially synchronized with the clock master side. From the perspective of a synchronous multiplex communication device that is a legacy device, it is as if it were connected via a synchronous communication network. High-quality synchronous communication using multiframe data can be realized by an IP communication network which is an asynchronous communication network.

  For this reason, even if an existing synchronous communication network is changed to an IP communication network that is an asynchronous communication network, by using the conversion device of the present invention, the existing legacy communication network is not required outside the IP communication network. The device can be used by connecting the synchronous multiplex communication device to the IP communication network as it is, and there is no obstacle when changing the existing optical fiber infrastructure from the synchronous communication network to the IP communication network. In addition, various advantages can be obtained in that the cost of equipment is reduced.

  When there are more than three synchronous multiplex communication devices, the conversion devices set with the clock master are shared and grouped by combining the other two conversion devices. For each group, the clock master, the first clock slave, By establishing cascade synchronization in the order of the second clock slaves, it is possible to extendly connect a large number of synchronous multiplex communication devices to the IP communication network.

Further, when a communication error of the second master channel is detected in the conversion device that has set the second clock slave, a simple process of switching to the reception buffer of the first master channel to which the channel from the conversion device that has set the clock master is assigned. Thus, stable clock synchronization can be maintained by reliably avoiding loss of clock synchronization with respect to a communication abnormality of the converter that has set the first clock slave on the clock master side.

  FIG. 1 is an explanatory diagram of a communication system using the synchronous / asynchronous communication network conversion apparatus of the present invention. In FIG. 1, legacy multiplex transmission apparatuses 10-1 to 10-5 are devices that perform data synchronous communication using a synchronous communication network constructed of, for example, optical fibers. In this embodiment, a legacy interface of 2.048 Mbps is used. Is used for a multiplex transmission apparatus that performs time division multiplex transmission of multi-frame data for 30 channels in synchronization with a clock using a multi-frame format.

  Here, since the legacy multiplex transmission apparatuses 10-1 to 10-5 synchronously transmit multi-channel data of 30 channels at 2.048 Mbps, the band of 64 Kbps per channel is 64 Kbps.

  The legacy IP converters 12-1 to 12-5 of the present embodiment are inserted and connected between the legacy multiplex transmission apparatuses 10-1 to 10-5 and the IP network 18 composed of routers and switches that are asynchronous communication networks. Mutual communication is performed by channel distributed transmission of multi-frame data via the IP network 18.

  Specifically, the legacy IP converters 12-1 to 12-5 are connected to the legacy multiplex transmission apparatuses 10-1 to 10-5 via the legacy networks 14-1 to 14-5, and the IP network 18 is connected to the LAN 16-. For example, Ethernet (R) or the like is used as a communication protocol for the IP network 18. For this reason, unique IP addresses are set in advance in the legacy IP converters 12-1 to 12-5.

  The conversion between the legacy synchronous communication networks 11-1 and 11-2, which are synchronous communication networks in the present embodiment, and the IP network 18 serving as the asynchronous communication network 15 is for clock synchronization with three legacy IP converters as one group. The control process is performed.

  For example, in the communication system of FIG. 1, the group G1 is configured by three legacy IP converters 12-1, 12-2, and 12-3. For the three legacy IP converters 12-1 to 12-3 included in the group G1, a master-slave relationship for clock synchronization control of a clock master, a first clock slave, and a second clock slave is set in advance. .

  In the group G1, the legacy IP converter 12-1 is set as the clock master, the legacy IP converter 12-2 is set as the first clock slave, and the legacy IP converter 12-3 is set as the second clock slave. .

  When the master-slave relationship is set for clock synchronization in this way, the legacy IP converter 12-2 performs clock synchronization control depending on the clock of the legacy IP converter 12-1 that has set the clock master. The legacy IP converter 12-3 set with the two-clock slave performs clock synchronization control depending on the legacy IP converter 12-2 set with the first clock slave.

  That is, in this embodiment, cascade synchronization is performed in the order of the clock master, the first clock slave, and the second clock slave set in the group G1.

  In the grouping for clock control by the three legacy IP converters, the legacy IP converter 12 set as the clock master in the group G1 for the remaining two legacy IP converters 12-4 and 12-5. The three groups G2 including −1 are configured.

  That is, the communication system according to the present embodiment is configured by successively forming groups including the remaining two legacy IP converters around the legacy IP converter 12-1 in which the clock master is set. Cascade synchronization is realized according to the settings of the 1 clock slave and the second clock slave.

  FIG. 2 is a block diagram showing a functional configuration of the legacy IP conversion apparatus of this embodiment. 2, the legacy IP converter 12 of this embodiment includes a legacy interface 20, an IP interface unit 22, a transmission buffer group 24 including 30-channel transmission buffers 240-1 to 240-30, and a packet assembly unit for 30 channels. A packet assembly group 26 including 260-1 to 260-30, a packet disassembly group 28 including packet decomposition units 280-1 to 280-30 for 30 channels, and reception buffers 300-1 to 300-30 for 30 channels The reception buffer group 30 includes a variable clock unit 32 and a control unit 34.

  The control unit 34 is a function realized by execution of a program by the CPU. The master / slave setting unit 36, the transmission conversion unit 38, the reception conversion unit 40, the clock master synchronization control unit 42, the first clock slave synchronization control unit 44, A two-clock slave synchronization control unit 45, a clock master monitoring unit 46, and a packet density measurement unit 48 are provided.

  The master / slave setting unit 36 provided in the control unit 34 is configured to synchronize clocks of the clock master, the first clock slave, or the second clock slave when three legacy IP conversion devices are grouped as shown in FIG. Set the master-slave relationship.

  Further, in the case of the legacy IP converters 12-2 and 12-3 in which the first clock slave and the second clock slave are set, the master / slave setting unit 36 allocates channels from the legacy IP converter 12-1 in which the clock master is set. A specific one of the channels is set as the first master channel.

  The legacy IP converter 12-2 that has set the first clock slave performs clock synchronization control based on the reception buffer amount of the first master channel.

  At the same time, in the case of the legacy IP converter 12-3 in which the second clock slave is set, the master slave setting unit 36 specifies a specific channel in the assigned channel from the legacy IP converter 12-2 in which the first clock slave is set. One channel is set as the second master channel.

  The legacy IP converter 12-3 that has set the second clock slave performs clock synchronization control based on the reception buffer amount of the second master channel. When communication abnormality occurs in the second master channel, the clock synchronization control is performed based on the reception buffer amount by switching to the reception buffer of the first master channel.

  3 and 4 show the clock master, the master slave setting unit 36 provided in the control unit 34 of FIG. 2 for the three legacy IP converters 12-1 to 12-3 constituting the group G1 of FIG. The functional configuration when the first clock slave and the second clock slave are set is shown.

  In the legacy IP converter 12-1 of FIG. 3, the function as the clock master synchronization control unit 42 of the control unit 34-1 becomes effective by setting the clock master.

  In the legacy IP converter 12-2 of FIG. 3, the function as the first clock slave synchronization control unit 44 of the control unit 34-2 becomes effective by setting the first clock slave. Furthermore, in the legacy IP converter 12-3 of FIG. 4, the function as the second clock slave synchronization control unit 45 of the control unit 34-3 becomes effective by setting the second clock slave.

  FIGS. 5A to 5E are explanatory diagrams of channel management tables 50-1 to 50-5 stored in the legacy IP converters 12-1 to 12-5 of FIG.

  Here, the channel assignment of the legacy IP converters 12-1 to 12-5 in the distributed channel transmission using the IP network 18 will be described with reference to FIG.

  In FIG. 6, when five legacy IP converters 12-1 to 12-5 are performing packet transmission based on channel distribution of multi-channel data of 30 channels, each node is represented by five nodes N1 to N5. It is necessary to construct all point communication (full duplex) of N1 to N5.

In such distributed channel transmission, if the number of nodes is n, the number m of all-point communication paths is calculated by tournament calculation.
m = n (n-1) / 2
Are in a relationship.

  In the present embodiment, since the number of nodes n = 5, the number of paths is m = 10. These ten paths are shown as paths P12 to P15, P23 to P25, P34 to P35, and P45 in FIG.

  Since nodes N1 to N5 perform channel distributed transmission of 30 channels each, if channels are evenly allocated for 4 paths per node, there are 7 channels per path, leaving 2 channels. One channel is additionally allocated to the path, and the path is 8 channels. Note that the actually used channel may be a part of the assigned channel.

  The channel management tables 50-1 to 50-6 shown in FIGS. 5A to 5E are set based on the channel distributed transmission paths and channel assignments shown in FIG.

  FIG. 5A shows a channel management table 50-1 stored in the legacy IP converter 12-1 set as the clock master of the group G1, and the four paths P12 and P13 from the node N1 shown in FIG. , P14, and P15, 8 channels, 7 channels, 7 channels, and 8 channels are assigned as indicated by the channel numbers. Further, channel number = 1 is set as a master channel for measuring the reception buffer amount at the time of start-up.

  FIG. 5B is a channel management table 50-2 stored in the legacy IP converter 12-2 set as the first clock slave of the group G1, and the four paths P12 from the node N2 shown in FIG. , P23, P24, and P25 are assigned as shown in the channel numbers, 8 channels, 8 channels, 7 channels, and 7 channels.

  Further, in order to measure the reception buffer amount for clock synchronization control, one of the eight channels assigned to the path P12 from the legacy IP converter 12-1 that has set the clock master is set as the first master channel. Therefore, the first master channel number = 1 is set.

  FIG. 5C shows a channel management table 50-3 stored in the legacy IP converter 12-3 set as the second clock slave of the group G1, and the four paths P13 from the node N3 shown in FIG. , P23, P34, and P35, 7 channels, 8 channels, 8 channels, and 7 channels are assigned as indicated by the channel numbers.

  Also, in order to measure the reception buffer amount for clock synchronization control, one of the 8 channels assigned to the path P23 from the legacy IP converter 12-2 that has set the first clock slave is set as the second master channel. In order to set, the second master channel number = 8 is set.

  Further, among the 7 channels assigned to the path P13 from the legacy IP converter 12-1 that has set the clock master for switching the reception buffer for clock synchronization control when a communication error occurs in the second master channel. Is set to the first master channel, the first master channel number = 1 is set.

  FIGS. 5D and 5E are channel management tables 50-4 and 50-5 of the legacy IP converters 12-4 and 12-5 set as the first and second clock slaves in another group G2. Thus, even if the groups are different, it is the same legacy IP converter 12-1 that is set as the clock master, and the channel management tables 50-4 and 50-5 are as shown in FIG. Channel assignment based on the paths of the nodes N4 and N5 and setting of the first master channel number and the second master channel number are performed.

  6 shows an example of a path configuration based on all-point communication of five legacy IP converters 12-1 to 12-5, but an arbitrary number is necessary as long as it does not exceed the bandwidth of the IP network 18. It can be.

  Referring to FIG. 2 again, the transmission conversion unit 38 provided in the control unit 34 receives the 30-channel multi-frame data received from the legacy multiplex transmission apparatus 10 in synchronization with the clock at the legacy interface unit 20, and receives 30 channels. Are stored in each of the transmission buffers 240-1 to 240-30, and then correspond to each of the packet assembling units 260-1 to 260-30 at a fixed time interval determined by the protocol of the IP interface unit 22, for example, the Ethernet protocol. An IP packet is generated from the accumulated data in the transmission buffers 240-1 to 240-30 and transmitted to the IP network 18. Transmission in which the 30-channel multi-frame data is converted into 30 IP packets and transmitted to the IP network is called channel distributed transmission.

  The reception conversion unit 40 provided in the control unit 34 receives the IP packet that has been channel-distributed and transmitted via the IP network 18 by the IP interface unit 22, and each of the packet decomposition units 280-1 to 280-30 receives each packet. After disassembling the packet data for each channel and accumulating it in the corresponding reception buffers 300-1 to 300-30, 30 channels from the accumulation of the reception buffers 300-1 to 300-30 in synchronization with the clock of the variable clock unit 32. Multi-frame data in which the frames are time-divisionally arranged are generated by the legacy interface unit 20 and transmitted to the legacy multiplex transmission apparatus 10.

  The clock master synchronization control unit 42 provided in the control unit 34 becomes valid in the setting state of the clock master like the legacy IP converter 12-1 in FIG. 3, and the legacy IP converter 12-1 set as the clock master. One of the assigned channels, for example, channel number = 1 is set as the master channel, and the variable clock unit when the reception buffer amount received by the reception buffer 300-1 of this master channel reaches a predetermined center value 32 is fixedly set to a predetermined center frequency f0 and activated.

  That is, in the legacy IP converter 12 set as the clock master, the clock frequency of the variable clock unit 32 is fixed to the center frequency fo, and the slave side is clock-synchronized with this clock frequency.

  The first clock slave synchronization control unit 44 provided in the control unit 34 becomes effective in the setting state of the first clock slave like the legacy IP converter 12-2 of FIG.

  As described above, the first clock slave synchronization control unit 44 enabled by the setting of the first clock slave sets the specified one channel of the assigned channels of the legacy IP converter 12-1 set as the clock master. When the reception buffer amount accumulated in the reception buffer of one master channel, for example, the reception buffer 300-1, reaches a predetermined center value Co, the variable clock unit 32 is set to the center frequency fo and started. The clock frequency of the variable clock unit 32 is controlled so that the amount C is stabilized at the center value Co, and the clock is synchronized with the legacy IP converters 12-1 in the group which is the setting state of the clock master.

  The clock slave synchronization control unit 45 provided in the control unit 34 becomes effective in the setting state of the second clock slave in the group like the legacy IP converter 12-3 in FIG.

  The second clock slave synchronization control unit 45 enabled by the setting of the second clock slave is a specific one channel among the assigned channels of the legacy IP converter 12-2 in which the first clock slave serving as the clock master is set. When the reception buffer amount stored in the reception buffer of the second master channel, for example, the reception buffer 300-1, reaches a predetermined center value Co, the variable clock unit 32 is set to the center frequency fo and started. Later, the clock frequency of the variable clock unit 32 is controlled so that the reception buffer amount C is stabilized at the center value Co, and the clock is synchronized with the other legacy IP converters 12-2 in the group in the setting state of the first clock slave. .

  Here, details of the clock slave synchronization control in the first clock slave synchronization control unit 44 and the second clock slave synchronization control unit 45 are as follows. First, when the system is started up when the power is turned on, the system starts up with the frequency f of the variable clock unit 32 set to the center frequency fo.

  After startup, when the reception buffer amount in the reception buffer of the first master channel or the second master channel to be detected exceeds the upper limit value Cmax of the preset buffer fluctuation allowable range, it is changed to a predetermined maximum adjustment frequency fmax To do.

    After the change to the maximum adjustment frequency fmax, when the reception buffer amount C returns to the center value Co, the maximum adjustment frequency fmax is changed to the frequency (fo + α) obtained by adding the predetermined offset frequency α to the center frequency fo, and the offset frequency In accordance with the number of adjustments n, α is repeated for the first time, 2α for the second time, 3α for the third time, and the like, and the same processing is repeated to stabilize the reception buffer amount C at the center value Co.

  Further, when the reception buffer amount C decreases when the variable clock unit 32 is started up, the reception buffer amount C is changed to a predetermined minimum frequency fmin when the reception buffer amount C falls below the lower limit value Cmin of the buffer fluctuation allowable range.

  When the reception buffer amount C returns to the center value Co after this change, the minimum frequency fmin is changed to a frequency (fo-α) obtained by subtracting a predetermined offset frequency α from the center frequency fo, and the offset frequency for subtracting such processing. Is repeated such that the first time is α, the second time is 2α, the third time is 3α,..., And the clock frequency is controlled so that the reception buffer amount C is stabilized at the center value Co.

  Such a clock slave synchronization control is a legacy IP conversion in which the first clock slave synchronization control unit 44 and the second clock slave of the legacy IP converter 12-2 in which the first clock slave shown in FIGS. 3 and 4 is set are set. The legacy IP converter 12-2 is synchronized with the legacy IP converter 12-1 that has set the clock master, and the second clock slave is set. The legacy IP converter 12-3 can realize cascade synchronization control that is clock-synchronized with the legacy IP converter 12-2 in which the first clock slave is set.

  Referring to FIG. 2 again, the clock master monitoring unit 46 and the packet density measuring unit 48 of the control unit 34 are the legacy IP converter in which the second clock slave is set by the master / slave setting unit 36, specifically, FIG. It becomes effective in the legacy IP converter 12-3 shown.

  The clock master monitoring unit 46 that is enabled in the legacy IP converter 12-3 that has set the second clock slave has a specific 1 in the assigned channel in the legacy IP converter 12-2 that has set the first clock slave that is the clock master. For detection of an abnormality in the reception buffer corresponding to the second master channel, which is a channel, the second master channel that performs clock synchronization when the abnormality detection state continues for a predetermined time is determined to have failed, and for clock synchronization control Corresponding to the first master channel that is a specific channel of the assigned channel to the legacy IP converter 12-1 that sets the clock master from the reception buffer of the second master channel so far as the reception buffer for measuring the reception buffer amount Switch to the received buffer.

  As a result, in the cascade synchronization in the order of the clock master, the first clock slave, and the second clock slave in the group, when the function as the clock master by the first clock slave fails, the first master channel is controlled for clock control. Switch the receive buffer to maintain clock synchronization.

  The detection of abnormality in the reception buffer of the second master channel in the clock master monitoring unit 46 is determined based on the measurement result by the packet density measuring unit 48. The packet density measuring unit 48 measures the number of packets received per unit time as the packet density for the reception buffer of the second master channel.

  FIG. 7 is an explanatory diagram of measurement processing by the packet density measurement unit 48 of the present embodiment. The packet density is, for example, the number of packets received in a unit time of about several hundred ms. In FIG. 7, T1 = 300 ms is set as the unit time T1, and IP packets received for the second master channel during this time. Is counted as the packet density.

  The packet density in this embodiment is counted at a constant interval time T2 of about several tens of ms. In the example of FIG. 7, the packet density is counted at intervals of T2 = 30 ms.

  Here, the unit time T1 for measuring the packet density is set by setting a longer time such as T1 = 300 ms so as not to erroneously determine the packet density due to fluctuations in IP packet reception.

  On the other hand, since it is necessary to promptly determine the channel abnormality from the packet density, it is necessary to update the packet density early. Therefore, the constant interval time T2 that is the packet density measurement interval is as short as T2 = 30 ms. Yes.

  Therefore, in the packet density measuring unit 48 of the present embodiment, a plurality of counters are sequentially activated at a time interval T2 shorter than the unit time T1 for counting the number of packets, and the number of packets is counted in parallel. The packet density is sequentially updated according to the number of packets in the counter that has reached.

  Referring again to the clock master monitoring unit 46 in FIG. 2 of the present embodiment, the packet density for the reception buffer corresponding to the first master channel or the second master channel measured by the packet density measuring unit 48 is a predetermined threshold value. If it falls within this range, it is determined that communication is normal, and if it deviates from this threshold range, it is determined that communication is abnormal.

  As a packet density threshold value for discriminating between normal communication and abnormal communication, the number of packets per short time that should be expected if normal is calculated from the transmission interval of IP packets to the IP network 18 is used as a reference packet density. On the other hand, the range of 80% to 120% is regarded as normal communication, and 80% or less or 120% or more is determined as communication abnormality.

When the clock master monitoring unit 46 determines that the communication error of the second master channel has occurred, the reception buffer of the second master channel that caused the communication error is switched to the reception buffer of the first master channel. There are two methods: (1) 0 system / 1 system switching (2) N system / E system switching.

  In the 0/1 system switching, the 0 system is the active system, the 1 system is the standby system, the system is switched from the 0 system to the 1 system when an abnormality is detected, and the 1 system switching is maintained as it is even if the 0 system abnormality is recovered. This is a method of switching to the 0 system when a communication error of the 1 system occurs during the subsequent operation.

  This 0-system / 1-system switching will be described with reference to buffer switching by the clock master monitoring unit 46 of the present embodiment. When an abnormal packet reception density is detected in the reception buffer corresponding to the second master channel that is 0-system during operation. Then, the reception buffer of the first master channel that becomes the first system is switched. When an abnormality in the packet reception density measured for the 1-system reception buffer is detected during the operation after the switching, the system switches to the 0-system reception packet.

  On the other hand, the N system / E system is switched when the N system is the active system and the E system is the standby system. When a communication abnormality is detected in the N system, the system is switched to the E system. This is a method of switching from the E system to the N system when it is determined that the abnormality has recovered and returned to normal.

  The N-system / E-system switching will be described with reference to buffer switching by the clock master monitoring unit 46 of the present embodiment. The detection of the packet reception density of the reception buffer corresponding to the second master channel, which is the N-system, detects the E-system switching. After switching to the reception buffer of one master channel, the packet reception density of the N-system reception buffer in which communication abnormality has occurred is monitored, and if the normal detection state continues for a predetermined time and communication is determined to be normal, the E-system reception buffer Is switched back to the normal N-system reception buffer after the abnormality is recovered.

  8 shows the control of the first clock slave synchronization control unit 44 and the second clock slave synchronization control unit 45 of the legacy IP converters 12-2 and 12-3 in which the first clock slave and the second clock slave of FIG. 4 are set. This is a time chart showing a case where the reception buffer amount increases at the time of startup after power-on or recovery from a system abnormality. The difference between the first clock slave synchronization control unit 44 and the second clock slave synchronization control unit 45 is whether the channel for measuring the reception buffer amount is the first master channel or the second master channel.

  FIG. 8A shows the reception buffer amount C, and FIG. 8B shows the clock frequency. At the time of start-up, when the reception buffer amount C reaches a predetermined center value Co as shown at time t0 in FIG. 8A, the clock of the variable clock unit 32-2 as shown in FIG. 8B. The frequency f is set to the center frequency fo, and start-up processing for sending the data stored in the reception buffer 30-2 to the legacy multiplex transmission apparatus 10-2 is started.

  At this time, if the clock frequency on the clock master side is higher than the clock frequency on the clock slave side, in the data transmission to the legacy multiplex transmission apparatus 10-2 by the clock of the center frequency fo set at the time of start-up, the reception buffer 30- Since the data reading is delayed with respect to the accumulation of the data received from the IP network 18 side for 2, the reception buffer amount C increases as time elapses.

  When the reception buffer amount C increases and exceeds the upper limit value Cmax at time t1, the clock frequency f is changed from the center frequency fo to the maximum adjustment frequency fmax, whereby the reception buffer 30-2 changes to the legacy multiplex transmission apparatus 10-2. Speed up data transmission for. For this reason, the reception buffer amount starts to decrease from time t1, and returns to the center value Co again at time t2.

  At time t2, the clock frequency f is changed from the maximum adjustment frequency fmax so far to a frequency (fo + α) shifted by a predetermined offset frequency α to the plus side with respect to the center frequency fo.

  In this way, by changing to the frequency (fo + α) obtained by adding the offset frequency α to the center frequency fo, the reception buffer amount starts increasing again at a moderate rate compared to the case of the center frequency fo at time t0, and at time t3. The upper limit value Cmax is reached. Also in this case, similarly to the time t1, the clock frequency is changed to the maximum adjustment frequency fmax, thereby reducing the reception buffer amount again and returning to the center value Co at the time t4.

  At time t4, the clock frequency f is changed to a frequency (α + 2α) obtained by adding a frequency n · α obtained by multiplying the center frequency by the offset frequency α and the number of adjustments n. As a result, the increase in the reception buffer amount from time t4 becomes more gradual and reaches the upper limit value Cmax at time t5. At time t5, the clock frequency is changed again to the maximum adjustment frequency fmax, and the reception buffer amount is returned to the center value Co at time t6. In this case, the clock frequency f is changed to the frequency (fo + 3α).

  When the frequency is changed to frequency (fo + 3α) at time t6, the reception buffer amount C is stabilized at the center value Co in this example. The state in which the reception buffer amount is stable at the center value Co is received based on the amount of data stored in the reception buffer 30-2 upon reception of the IP packet from the IP network 18 and the clock frequency (fo + 3α) of the variable clock unit 32-2. This is a case where the amount of data sent from the buffer 30-2 to the legacy multiplex transmission device 10-2 matches, and this is eventually clocked to the clock frequency of the variable clock unit 32-1 on the clock master side via the IP network 18. This means that the state where the clock frequency of the variable clock unit 32-2 on the slave side is synchronized is established.

  Thus, in this embodiment, the adjustment of the clock frequency for stabilizing the reception buffer amount at the center value by the first clock slave synchronization control unit 44 of the legacy IP converter 12-2 in which the clock slave is set. Through the learning process, it is possible to realize clock synchronization control that synchronizes the clock frequency on the clock slave side with the clock frequency on the clock master side.

  Here, the frequency change of the maximum adjustment frequency fmax with respect to the center frequency fo of the clock frequency f in FIG. 8B is, for example, +100 ppm, and the change width of the minimum adjustment frequency fmin with respect to the center frequency fo is −100 ppm. The offset frequency α to be adjusted is, for example, a resolution of α = 0.1 ppm.

In addition, ppm is frequency accuracy, and when this is expressed by frequency change width ± Δf, between frequency angle ppm and frequency error, (frequency accuracy ppm) = Δf / (fo × 10 ⁻⁸ )
For example, when fo = 2 MHz and ppm = 100, Δf = 5 KHz, and the offset frequency α serving as the adjustment resolution is α = 50 Hz.

  In FIG. 8, the clock frequency is stabilized by three adjustment processes. However, since the resolution is actually α = 0.1 ppm, it depends on the clock deviation at the time of startup. In order to obtain a synchronized state in which the clock frequency on the slave side is stabilized by the clock slave synchronization control of this embodiment, it usually takes a processing time of several hours to several tens of hours.

  However, even if it is such a long time, once it is started and stabilized, the frequency of the + α or −α clock adjustment with respect to the change in the reception buffer amount is about once every several days, for example. Transmission quality comparable to that obtained when clocks are transmitted by an external network to the network to achieve clock synchronization can be ensured.

  FIG. 9 is a time chart showing the clock slave synchronization control of this embodiment when the reception buffer amount decreases at the time of startup.

  In FIG. 9A, the IP interface unit 22 is transferred from the IP network 18 to the reception buffer 30-2 of the legacy IP converter 12-2 on the clock slave side in FIG. -2 starts to accumulate the packet data of the IC packet received, and when the reception buffer amount reaches the center value Co, the clock frequency fo is changed to the center value fo as shown in FIG. And the accumulated data in the reception buffer 30-2 is read from the legacy interface unit 20-2 to the legacy multiplex transmission apparatus 10-2 and transmission of synchronous communication data is started.

  In this case, the clock frequency of the variable clock 32-2 of the legacy IP converter 12-2 for which the clock slave is set is different from the clock frequency of the variable clock unit 32-1 of the legacy IP converter 12-1 for which the clock master is set. If it is high, data transmission from the reception buffer 30-2 to the legacy multiplex transmission apparatus 10-2 is accelerated, so that the reception buffer amount C starts to decrease from time t0 as shown in FIG. Below.

  In this case, the clock frequency f is changed from the center frequency fo to the minimum adjustment frequency fmin, and the transmission amount from the reception buffer 30-2 is reduced. For this reason, the reception buffer amount C starts increasing from time t1 and recovers to the center value Co again at time t2.

  When the center value Co is restored, the clock frequency f is changed to the frequency (fo−α) obtained by subtracting the frequency obtained by multiplying the offset frequency α by one adjustment number from the center frequency fo. As a result, the reception buffer amount C from time t2 decreases, and the rate of decrease becomes more gradual than the first time at time t0. When the frequency falls below the lower limit Cmin again at time t3, the clock frequency f is changed again to the minimum adjustment frequency fmin. The reception buffer amount C is increased from time t3.

  When the reception buffer amount C recovers to the center value Co at time t4, the clock frequency is changed to (fo-2α), and the decreasing rate of the reception buffer amount C from time t4 is further reduced. Similar processing is repeated at times t5 and t6, and when the clock frequency becomes (fo-3α), the reception buffer amount C is stabilized at the center value Co, and the clock on the master slave side is synchronized with the clock master side. Stable state can be created.

  Further, in the present embodiment, as shown in FIG. 8 or FIG. 9, if a stable state that is in a clock synchronization state is obtained through learning processing by clock slave synchronization control after startup, the clock frequency in the stable state, For example, the stable clock frequency (fo + 3α) is stored in the case of FIG. 8, and the stable clock frequency (fo-3α) is stored in the case of FIG.

  When the power is turned on next time or when the communication buffer is restored, when the reception buffer reaches the center value Co, the clock frequency f is set to the stored stable clock frequency instead of the center frequency fo. Start the clock adjustment process. As a result, the clock adjustment processing time at the second and subsequent startups can be greatly reduced.

  Further, as another embodiment of the clock slave synchronization control, the upper and lower limits of the buffer fluctuation allowable range have two levels of large and small, and from the start of the clock frequency until it becomes stable, the lower upper and lower limits are used. After a narrow buffer fluctuation tolerance is set and the clock frequency is stabilized, a wider buffer fluctuation tolerance is set according to the larger upper and lower limit values, thereby shortening the time until the clock frequency stabilizes in a synchronized state. it can.

  According to the clock slave synchronous control in which the buffer upper limit value is set in two stages, in the case of FIGS. 8 and 9, it takes several hours to several tens of hours to reach the stable region of the clock. Depending on the degree of the set value when there are two stages, the time can be significantly shortened until the clock is stabilized, such as several minutes to several tens of minutes.

  Then, after adjusting the clock to the stable region in a short time with the narrow buffer fluctuation allowable range, the upper and lower limits of the buffer fluctuation allowable range are increased to widen the range, thereby generating clock adjustment control in the stable region. The frequency can be suppressed and a more stable clock synchronization state can be secured.

  FIG. 10 is an explanatory diagram of a hardware environment of a computer that realizes the legacy IP converter 12 of FIG. 2 by executing a program. In FIG. 10, the legacy interface unit 20 and the IP interface unit 22 are connected to the bus 56 of the CPU 54 in addition to the RAM 58 and the ROM 60.

  The ROM 60 stores the conversion program of this embodiment in addition to the BOIS and the OS. When the computer is started, the OS is read and arranged in the RAM 58 by executing the BIOS of the ROM 60, and then the conversion program of the present invention is read and arranged from the ROM 60 to the RAM 58 by the execution of the OS and executed by the CPU 54.

  FIG. 11 is a flowchart showing an outline of the conversion processing according to the present embodiment, and it will be described as follows with reference to FIG.

When the legacy IP converter 12 of FIG. 2 is started up by turning on the power, initial setting is first performed in step S1. This initial setting includes (1) clock master slave setting, (2) master channel setting, and (3) clock synchronization control parameter setting.

  The clock master / slave setting is a process of setting the clock master, the first clock slave, or the second clock slave by setting the three legacy IP conversion devices as one group by the master slave setting unit 36.

  The next master channel setting is a setting of the first master channel and the second master channel based on the channel management tables 50-1 to 50-3 shown in FIGS.

That is, the master / slave setting unit 36 sets the first and second clock slaves, and the legacy IP conversion device sets a specific one channel among the assigned channels from the legacy IP conversion device that sets the clock master as the first master channel. The legacy IP converter that has been set to the second clock slave sets one specific channel among the assigned channels from the legacy IP converter that has set the first clock slave to the second master channel. The parameter setting of the synchronization control is a parameter of the clock synchronization control shown in FIGS. 8 and 9. The reception buffer amount is center value Co, upper limit value Cms, lower limit value Cmin, clock frequency is center frequency fo, maximum adjustment The frequency fmx, the minimum adjustment frequency fmin, the offset frequency α, and the like.

  Further, the parameter setting includes setting of upper and lower thresholds of 80% to 120% with respect to a reference value for determining communication abnormality and normality by the clock master monitoring unit 46.

  If the initial setting process in step S1 is completed, the process proceeds to step S2, and it is determined whether or not the setting in the legacy IP converter 12 activated by power-on is the clock master setting. If it is clock master setting, it will progress to step S3, will perform the clock master conversion process by the clock master synchronous control part 42, and will repeat this until there exists a stop instruction | indication in step S4.

  If it is not the clock master setting in step S2, that is, if it is the first clock slave setting or the second clock slave setting, the process proceeds to step S5, and the control process by the first clock slave synchronization control unit 44 as the clock slave conversion process Alternatively, the control process by the second clock slave synchronization control unit 45 is repeated until a stop instruction is issued in step S6.

  FIG. 12 is a flowchart of clock master transmission conversion processing by the transmission conversion unit 38 of the legacy IP converter 12 when the clock master is set.

  In FIG. 12, the clock master transmission conversion process checks whether or not there is a transmission timing at a predetermined time interval according to a predetermined IP protocol, for example, an Ethernet (R) communication protocol, by the IP interface unit 22 in step S1. If it is determined that the packet arrives at step S2, the process proceeds to step S2. At that time, IP packets are generated by the packet assembly units 260-1 to 260-30 from the accumulated data of 30 channels stored in the transmission buffers 240-1 to 240-30, respectively. Then, the packet is transmitted to the IP network 18 and this packet distributed transmission process is repeated until a stop instruction is issued in step S3.

  FIG. 13 is a flowchart showing the clock master reception conversion process of this embodiment, which is the process of the reception conversion unit 40 when the clock master is set by the legacy IP converter 12 of FIG.

  In FIG. 13, first, in step S1, the variable clock unit 32 is fixed and activated at the center frequency fo, and in step S2, it does not depend on the accumulation of reception data from the IP network 18 to the reception buffers 300-1 to 300-30. , Start-up processing is performed for all channels that generate 30-frame multi-frame data and start transmission from the legacy interface unit 20 to the legacy multiplex transmission apparatus 10.

  When the start-up process is completed, the process proceeds to transmission of multi-frame data based on the received and accumulated data of the IP packet by clock synchronization of all channels in step S3, and is repeated until a stop instruction is issued in step S4.

  FIG. 14 is a flowchart showing details of the startup process in step S2 of FIG. In FIG. 14, in the start-up process, the reception buffers 300-1 to 300-30 for all channels are cleared in step S1, and then mark hold data is generated as non-signal data by make busy processing in step S2, for example. The legacy interface unit 20 generates multiframe data in which 30-channel mark hold data is time-divisionally arranged in synchronization with the clock of the variable clock unit 32, and starts synchronous communication with the legacy multiplex transmission apparatus.

  When the legacy IP converter 12 performs distributed channel transmission to the IP network, the packet data accumulation based on the reception of the IP packets to the reception buffers 300-1 to 300-30 at the time of start-up is performed in other legacy IP converters. There are various variations due to variations in the raising operation and variations in the IP network, and even if the power is turned on, the stored data cannot be stored in the reception buffers 300-1 to 300-30.

  Therefore, in this embodiment, as a start-up process at the time of start-up, the legacy multiplex transmission apparatus 10 side synchronizes with the clock in the creation of multi-frame data using mark hold data that does not depend on accumulated data by the make busy process. The transmission of synchronous communication data can be started. Note that the mark hold data generated as no-signal data is all-one data in the case of audio transmission, and this is data indicating a silent state.

  Subsequently, in step S3, it is checked whether there is a reception buffer that has reached the center value Co among the reception buffer amounts of the reception buffers 300-1 to 300-30, and if there is a reception buffer that has reached the center value Co, In step S4, the data stored in the reception buffer is included in the multi-frame data and switched to data read transmission for synchronous communication with the legacy multiplex transmission apparatus 10.

  In step S5, it is checked whether or not make-busy cancellation has been performed for all channels to determine whether or not make-busy cancellation has been performed. In step S6, a transition is made to a normal processing state in which a multi-format frame is generated from the accumulated data in the reception buffer and transmitted on all channels.

  FIG. 15 is a flowchart showing the first clock slave transmission conversion process of the present embodiment. When the first clock slave is set by the legacy IP converter 12 of FIG. 2, the first clock slave synchronization control unit 44 is enabled. This is the processing operation when

  In FIG. 15, the first clock slave transmission conversion process is basically the same as the clock master transmission conversion process of FIG. 12, and the transmission timing at a fixed interval determined by the protocol of the IP interface unit 22 is determined in step S1. In step S2, distributed channel transmission is performed in which IP packets for all channels are generated and transmitted to the IP network, and this is repeated until a stop instruction is issued in step S3.

  The difference in the first clock slave transmission conversion processing is that the first clock slave synchronization control unit 44 controls the clock master side to follow the fixed setting when the clock frequency by the variable clock unit 32 is the clock master. It is only a point that has been done.

  FIG. 16 is a flowchart showing the first clock slave reception conversion process of the present embodiment, which is the processing operation of the reception conversion unit 40 when the first clock slave is set in the legacy IP converter 12 of FIG.

  In FIG. 16, the first clock slave reception conversion process is started by setting the clock frequency of the variable clock unit 32 to the center frequency fo at the start-up associated with power-on in step S1, and the start-up process for all channels in step S2. Do.

  The details of this startup process are the same as those of the clock master in FIG. Next, after shifting to multi-frame transmission by clock synchronization of all channels in step S3, clock synchronization control of the first clock slave is performed in step S4, and the process of step S4 is repeated until a stop instruction is issued in step S5.

  FIG. 17 is a flowchart showing details of the clock synchronization control of the first clock slave in step S4 of FIG.

  In FIG. 17, the clock synchronization control process reads the reception buffer amount C of the reception buffer corresponding to the first master channel preset in step S1, and checks whether the reception buffer amount is the upper limit value Cmax in step S2. Here, the processing of steps S2 to S6 is clock synchronization control when the reception buffer amount C increases from the center value Co shown in the time chart of FIG. 8, and steps S7 to S10 are conversely the reception buffer shown in FIG. The control process is performed when the amount C decreases.

  If it is determined in step S2 that the reception buffer amount has increased to reach the upper limit value Cmax, the process proceeds to step S3. After changing the clock frequency f to the maximum adjustment frequency fmax, the reception buffer amount C is set to the center value in step S4. Check if it has returned to Co.

When returning to the center value Co, the number of adjustments n is incremented by 1 in step S5 (where the initial value is n = 0), and in step S6, the clock frequency f is set to f = fo + n. α
Change to The processes in steps S1 to S6 are repeated until the reception buffer amount C becomes stable at the center value Co.

  On the other hand, if the reception buffer amount has not reached the upper limit value in step S2, it is checked in step S7 whether or not the lower limit value Cmin has been reached. After changing the frequency f to the minimum adjustment frequency fmin, it is determined in step S9 whether or not the reception buffer amount C has returned to the center value Co.

When the value returns to the center value Co, the number of adjustments n is increased by one in step S10, and then the clock frequency is changed to f = fo-n. α
To correct as The processes in steps S1, S2, and S7 to S10 are repeated until the reception buffer amount C is stabilized at the center value Co.

  FIG. 18 is a flowchart showing the second clock slave transmission conversion process in this embodiment, which is a process when the second clock slave is set in the legacy IP converter 12 of FIG. . In FIG. 18, the second clock slave control unit transmission conversion process is basically the same as the first clock slave transmission conversion process shown in FIG.

  FIG. 19 is a flowchart showing the second clock slave reception conversion process of the present embodiment. This process is performed by the reception conversion unit 40 when the first clock slave is set in the legacy IP converter 12 of FIG.

  In FIG. 19, the second clock slave reception conversion process is basically the same as the first clock slave reception conversion process of FIG. 16 from step S1 to S4, and a clock master monitoring process is newly added in step S5.

  The clock synchronization control of the second clock slave in step S4 is different in that the reception buffer for measuring the reception buffer amount for clock synchronization control is the second master channel.

  FIG. 20 is a flowchart showing details of the clock synchronization control of the second clock slave in step S4 of FIG. The clock synchronization control process of FIG. 20 is basically the same as the first clock slave synchronization control process of FIG. 17, and when the reception buffer amount read in step S1 is the reception corresponding to the second master channel in FIG. The difference is reading from the buffer.

  FIG. 21 is a flowchart showing the monitoring process of the clock master in step S6 of FIG. 20, taking 0 system / 1 system switching as an example. In FIG. 21, the clock master monitoring process reads the packet density measurement value in step S1, and determines whether the packet density is in the normal range in step S2.

The normal range of packet density is 80% <normal range <120% relative to the reference value
Therefore, the abnormal range is 80% or less or 120% or more.

  If it is determined in step S2 that the packet density is in the abnormal range, the process proceeds to step S3. If it is determined that the abnormality detection has continued for a certain period of time, the process proceeds to step S4, and whether or not the current 0-system received packet is set. If it is checked and the system is 0, the process proceeds to step S5, and the setting is switched to the setting of the reception buffer for system 1.

  Here, the 0-system reception buffer is a reception buffer corresponding to the second master channel on the first clock slave side, and the 1-system reception buffer is a reception buffer corresponding to the first master channel on the clock master side.

  On the other hand, if it is currently set in the system 1 reception buffer in step S3, the process proceeds to step S6 to switch to the system 0 reception buffer setting. After determining such a packet density abnormality, that is, a communication abnormality and switching the reception buffer, start-up processing is performed in step S7. This startup process has the same contents as the startup process shown in FIG.

  FIG. 22 is a flowchart showing details of another clock master monitoring process in step S6 of FIG. 20, and is characterized in that switching between N system / E system is performed when a communication abnormality is determined.

  In FIG. 22, the clock master monitoring process reads the measured value of the packet density in step S1, and then checks whether the packet density is in the normal range in step S2. If it is abnormal, the process proceeds to step S3. If it is determined that the abnormality continues for a certain time, the system switches from the N-system to the E-system reception buffer in step S4.

  Here, the N-system reception buffer is a reception buffer corresponding to the second master channel on the first clock slave side, while the E-system is a reception buffer for the first master channel on the clock master side. When switching to the setting of the E-system reception buffer in step S4, the process proceeds to step S5 to perform start-up processing and return to normal clock synchronization control that avoids communication abnormality.

  Subsequently, the channel in which communication abnormality has occurred is monitored by the processing in steps S6 to S10, and control is performed to return to the N system when communication returns to normal. That is, in step S6, the reception buffer of the first master channel in which the communication error of the packet density has occurred is measured and read.

  When it is determined in step S7 that the packet density is in the normal range, if it is determined in step S8 that the packet density is in the normal range for a certain period of time, it is determined in step S9 from the current E system to the original N system. The setting is switched to the reception buffer, and a startup process is performed in step S10.

  As a result, after switching from the reception buffer of the second master channel to the reception buffer of the first master channel due to a communication error, when the communication error of the second master channel is resolved and normal communication is resumed, the switched reception buffer is restored to the original reception. Processing to return to the buffer is performed.

  As described above, for clock synchronization control in the clock master monitoring process of this embodiment, communication abnormality is determined based on the packet reception density, which is the number of packets per unit time, for the reception buffer abnormality for which the reception buffer amount is measured. Therefore, it is possible to more reliably determine the soundness of the communication state using the IP packet than when the communication error is determined when the reception buffer amount that is normally performed is zero (buffer empty). By switching only when buffer switching is required, more stable clock synchronization control can be realized through distributed channel transmission of IP packets in the IP network.

  The present invention also provides a conversion program executed by a computer as shown in FIG. 10 used in the legacy IP converter 12 shown in FIG. 2, and this conversion program is shown in the flowcharts of FIGS. Have content.

  The present invention also provides a storage medium storing a conversion program executed by a computer provided in the legacy IP converter 12 of FIG. This storage medium is a card-type storage medium such as a CD-ROM, floppy disk (R), DVD, magneto-optical disk, IC card, etc., a hard disk drive storage device provided inside or outside the computer system, and a program through a line. It includes a database to be held, or another computer system and database, and further a transmission medium on the line.

  The present invention is not limited to the above-described embodiment, includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above-described embodiment.

Here, the features of the present invention are enumerated as follows.
(Appendix)

(Appendix 1) (Device)
Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In a synchronous asynchronous communication network conversion device that transfers data between
The conversion device that sets the master-slave relationship of clock synchronization of any one of the clock master, the first clock slave, and the second clock slave, and sets the first and second clock slaves, with the three sets of the conversion devices as one group. One specific channel among the assigned channels from the conversion device that has set the clock master is set as the first master channel, and the conversion device that has set the second clock slave is from the conversion device that has set the first clock slave. A master / slave setting unit for setting a specific one of the assigned channels as the second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. A clock master synchronization control unit,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. And
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the second clock slave that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after startup and synchronizes the clock with another conversion device in the set state of the first clock slave. A synchronization controller;
A conversion device comprising: (1)

(Appendix 2) (Details of clock slave synchronization control)
In the conversion device according to appendix 1, when a plurality of the conversion devices are grouped as one group, the conversion device in which the clock master is set is included as a common conversion device for all groups. A conversion device. (2)

(Appendix 3) (Details of clock slave synchronization control)
In the conversion device according to attachment 1, the first and second clock slave synchronization control units include:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion device characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially. (3)

(Appendix 4) (Clock master monitoring and buffer switching)
In the conversion apparatus according to attachment 1, the packet reception density of the second master channel is further measured in the setting state of the second clock slave, and the abnormality detection state of the packet reception density continues for a predetermined time. In this case, a conversion apparatus comprising a clock master monitoring unit that switches a reception buffer for measuring a reception buffer amount from the reception buffer of the second master channel to the reception buffer of the first master channel. (4)

(Appendix 5) (Clock master monitoring and buffer switching)
The conversion apparatus according to appendix 4, wherein the clock master monitoring unit measures the number of packets received per unit time as the packet density.

(Appendix 6) (Clock master monitoring and buffer switching)
The conversion device according to appendix 5, wherein the clock master monitoring unit sequentially starts a plurality of counters at a time interval shorter than the unit time, counts the number of packets in parallel, and the packet of the counter that has reached the unit time A conversion apparatus characterized by sequentially updating the packet density according to a number.

(Appendix 7) (Switching between 0 and 1 systems)
In the conversion device according to appendix 4, when the clock master monitoring unit detects an abnormality in the packet reception density measured for the switched reception buffer after switching the reception buffer by detecting the abnormality in the packet reception density, A conversion apparatus characterized by switching from a current reception buffer to a reception buffer before switching.

(Appendix 8) (N / E switch)
In the conversion device according to attachment 4, the clock master monitoring unit switches the reception buffer due to the abnormality detection of the packet reception density, and the normal detection state of the packet reception density of the reception buffer before switching continues for a predetermined time. In this case, the conversion apparatus returns the current reception buffer to the reception buffer before switching.

(Appendix 9) (Legacy IF and IP communication network)
The conversion apparatus according to claim 1, wherein the synchronous multiplex communication device is a device having a legacy interface, and the device of the asynchronous communication network is a device having an Internet protocol interface.

(Appendix 10) (Method)
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In the conversion method of the conversion device for transferring data between,
Three sets of the synchronous multiplex communication device and the conversion device are set as one group, and a clock synchronization subordinate relationship of any one of the clock master, the first clock slave, and the second clock slave is set, and the first and second clock slaves are set. The converting apparatus sets a specific one channel among the allocated channels from the converting apparatus that has set the clock master as the first master channel, and the converting apparatus that sets the second clock slave sets the first clock slave. A master-slave setting step of setting a specific one channel among the assigned channels from the converted converter as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. And controlling the clock frequency of the variable clock unit so that the reception buffer amount is stabilized at the center value after activation, and synchronizing the clock with another synchronous / asynchronous communication converter in the set state of the clock master. Slave synchronization control step;
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the clock frequency of the variable clock unit is controlled so that the amount of the reception buffer is stabilized at the center value, and clock synchronization is performed with another synchronous / asynchronous communication conversion device in the setting state of the second clock slave. A second clock slave synchronization control step;
A conversion method characterized by comprising: (5)

(Appendix 11) (Details of clock slave synchronization control)
The conversion method according to appendix 10, wherein when a plurality of the conversion devices are grouped into one group, the conversion device in which the clock master is set is included as a common conversion device for all groups. Conversion method.

(Appendix 12) (Details of clock slave synchronization control)
In the conversion method according to attachment 10, the first and second clock slave synchronization control steps include:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion method characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially.

(Supplementary note 13) (Clock master monitoring and buffer switching)
In the conversion method according to appendix 1, the packet reception density of the second master channel is further measured when the second clock slave is set, and the abnormality detection state of the packet reception density continues for a predetermined time. And a clock master monitoring step for switching a reception buffer for measuring a reception buffer amount from the reception buffer of the second master channel to the reception buffer of the first master channel. .

(Appendix 14) (Program)
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
The three groups of the synchronous multiplex communication device and the conversion device are set as one group, and a clock synchronization subordinate relationship of the clock master, the first clock slave, or the second clock slave is set, and the first and second clock slaves are set. The set conversion device sets a specific one channel among the assigned channels from the conversion device that sets the clock master as the first master channel, and the conversion device that sets the second clock slave sets the first clock slave as the first master channel. A master-slave setting step of setting one specific channel among the assigned channels from the set conversion device as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. Steps,
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the second clock for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with the other conversion device in the setting state of the second clock slave. Slave synchronization control step;
A program characterized by having executed. (6)

(Appendix 15) (Details of clock slave synchronization control)
In the program according to appendix 14, when a plurality of conversion devices are grouped as one group, the conversion device in which the clock master is set is included as a common conversion device for all groups. Program to do.

(Supplementary Note 16) (Details of clock slave synchronization control)
In the program according to attachment 1, the first and second clock slave synchronization control steps include:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A program characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while sequentially increasing the offset frequency.

(Appendix 17) (Clock master monitoring and buffer switching)
In the program according to attachment 1, when the packet reception density of the second master channel is further measured and the packet reception density abnormality detection state continues for a predetermined time, the second clock channel becomes valid. And a clock master monitoring step of switching a reception buffer for measuring a reception buffer amount from the reception buffer of the second master channel to the reception buffer of the first master channel.

(Appendix 18) (Recording medium)
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
The three groups of the synchronous multiplex communication device and the conversion device are set as one group, and a clock synchronization subordinate relationship of the clock master, the first clock slave, or the second clock slave is set, and the first and second clock slaves are set. The set conversion device sets a specific one channel among the assigned channels from the conversion device that sets the clock master as the first master channel, and the conversion device that sets the second clock slave sets the first clock slave as the first master channel. A master-slave setting step of setting one specific channel among the assigned channels from the set conversion device as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. Steps,
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the second clock for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with the other conversion device in the setting state of the second clock slave. Slave synchronization control step;
A reception buffer that is enabled in the setting state of the second clock slave, measures the packet reception density of the second master channel, and measures the amount of reception buffer when the abnormality detection state of the packet reception density continues for a predetermined time. A clock master monitoring step of switching from the reception buffer of the second master channel to the reception buffer of the first master channel;
The computer-readable recording medium characterized by storing the program which performs. (7)

(Appendix 19) (System)
A master converter set as a clock master connected to an asynchronous communication network composed of devices that asynchronously transfer data to a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal;
A first slave conversion device in which another synchronous multiplex communication device is set as a first clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a first master channel;
A second slave conversion device in which another synchronous multiplex communication device is set as a second clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a second master channel;
In a communication system for transferring data between a plurality of synchronous multiplex communication devices,
The master converter is
A master-slave setting unit that sets a clock master in itself, with three sets of the synchronous multiplex communication device and the conversion device as one group,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. A clock master synchronization control unit,
With
The first slave converter is
Three sets of the synchronous multiplex communication device and the conversion device are set as one group, and the first clock slave is set to itself, and one specific channel among the assigned channels from the clock master conversion device is set as the first master channel. Master / slave setting section to be set,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
When the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated, and after activation, the reception buffer amount is set to the center value. A first clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to be stable, and to synchronize the clock with another communication system in the setting state of the clock master;
With
The second slave converter is
Three sets of the synchronous multiplex communication device and the conversion device are set as one group, and the second clock slave is set in the group, and one specific channel among the assigned channels from the clock master conversion device is set as the first master channel. A master / slave setting unit configured to set and set one specific channel among the assigned channels from the first clock slave conversion device as a second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
When the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated, and after activation, the reception buffer amount is set to the center value. A second clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to be stable, and to synchronize with another communication system in a setting state of the second clock slave;
A reception buffer that is enabled in the setting state of the second clock slave, measures the packet reception density of the second master channel, and measures the amount of reception buffer when the abnormality detection state of the packet reception density continues for a predetermined time. A communication system comprising a clock master monitoring unit for switching from the reception buffer of the second master channel to the reception buffer of the first master channel. (8)

(Appendix 20) (Details of clock slave synchronization control)
In the communication system according to attachment 19, the first clock slave synchronization control unit of the first slave conversion device and the second clock slave synchronization control unit of the second slave conversion device are:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A communication system, wherein the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency is repeated while increasing the offset frequency sequentially.

Explanatory drawing of the communication system using the conversion apparatus of the synchronous asynchronous communication network of this invention The block diagram which showed the function structure of the legacy IP converter by this embodiment The block diagram which showed the function structure of the legacy IP converter which set the clock master of FIG. 2, and the 1st clock slave The block diagram which showed the function structure of the legacy IP converter which set the 1st clock slave of FIG. 2, and the 2nd clock slave Explanatory drawing of the channel management table stored in five legacy IP converters of FIG. Explanatory diagram of channel distributed transmission in the five legacy IP converters of FIG. Explanatory drawing which showed the measurement process of the packet density in this embodiment Time chart showing clock slave synchronization control of this embodiment when the amount of reception buffer increases at startup Time chart showing the clock slave synchronization control of this embodiment when the amount of reception buffer decreases at startup Explanatory drawing of the hardware environment of the computer where the conversion program of this embodiment is executed A flowchart showing an outline of conversion processing according to this embodiment. The flowchart which showed the clock master transmission conversion process of this embodiment The flowchart which showed the clock master reception conversion process of this embodiment The flowchart which showed the detail of the startup process in step S2 of FIG. The flowchart which showed the 1st clock slave transmission conversion process of this embodiment The flowchart which showed the 1st clock slave reception conversion process of this embodiment The flowchart which showed the detail of the clock synchronous control process in step S4 of FIG. The flowchart which showed the 2nd clock slave transmission conversion process of this embodiment The flowchart which showed the 2nd clock slave reception conversion process of this embodiment The flowchart which showed the detail of the clock synchronous control process in FIG.19 S4 The flowchart which showed the detail of the clock master monitoring process in step S6 of FIG. The flowchart which showed the detail of the other clock master monitoring process in step S6 of FIG.

Explanation of symbols

10, 10-1 to 10-5: Legacy multiplex transmission apparatus 11-1, 11-2: Synchronous communication network 12, 12-1 to 12-5: Legacy IP converters 14-1 to 14-5: Legacy network 15 : Asynchronous communication networks 16-1 to 16-5: LAN
18: IP network 20, 20-1 to 20-3: legacy interface unit 22, 22-1 to 22-3: IP interface unit 24: transmission buffer group 26: packet assembly group 28: packet decomposition group 30: reception buffer group 32, 32-1 to 32-3: Variable clock unit 34, 34-1 to 34-3: Control unit 36: Master / slave setting unit 38: Transmission conversion unit 40: Reception conversion unit 42, 42-1: Clock master synchronization Control unit 44: first clock slave synchronization control unit 45: second clock slave synchronization control unit 46: clock master monitoring unit 48: packet density measurement units 50-1 to 50-5: channel management table 54: CPU
56: Bus 58: RAM
60: ROM
62: Buffer fluctuation allowable range 240-1 to 240-30: Transmission buffer 260-1 to 260-30: Packet assembly unit 280-1 to 280-30: Packet decomposition unit 300-1 to 300-30: Reception buffer

Claims (8)

Inserted and connected between a synchronous multiplex communication apparatus that transmits multi-channel data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In a synchronous asynchronous communication network conversion device that transfers data between
The conversion device in which three of the conversion devices are set as one group, the master-slave relationship of the clock synchronization of the clock master, the first clock slave, or the second clock slave is set, and the first and second clock slaves are set. One specific channel among the assigned channels from the conversion device that has set the clock master is set as the first master channel, and the conversion device that has set the second clock slave is from the conversion device that has set the first clock slave. A master / slave setting unit for setting a specific one of the assigned channels as the second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. A clock master synchronization control unit,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. And
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the second clock slave that controls the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after startup and synchronizes the clock with another conversion device in the set state of the first clock slave. A synchronization controller;
A conversion device comprising:
2. The conversion apparatus according to claim 1, wherein when a plurality of groups of the conversion apparatuses are formed as one group, the conversion apparatus set with the clock master is included as a common conversion apparatus for all the groups. Characteristic conversion device.
The conversion device according to claim 1, wherein the first and second clock slave synchronization control units include:
If the receive buffer amount exceeds the upper limit of the allowable range of buffer fluctuation after starting the clock frequency from the center frequency, it is changed to a predetermined maximum adjustment frequency, and the maximum adjustment is made when the receive buffer amount returns to the center value after the change. The process of changing the frequency to a frequency obtained by adding a predetermined offset frequency to the center frequency is repeated while sequentially increasing the offset frequency,
When the reception buffer amount falls below the lower limit value of the buffer fluctuation allowable range after starting the clock frequency from the center frequency, it is changed to a predetermined minimum adjustment frequency, and when the reception buffer amount returns to the center value after the change, the minimum A conversion device characterized by repeating the process of changing the adjustment frequency to a frequency obtained by subtracting a predetermined offset frequency from the center frequency while increasing the offset frequency sequentially.
2. The conversion device according to claim 1, further comprising: valid in the setting state of the second clock slave, measuring a packet reception density of the second master channel, and detecting an abnormality in the packet reception density for a predetermined time. And a clock master monitoring unit that switches a reception buffer for measuring a reception buffer amount from the reception buffer of the second master channel to the reception buffer of the first master channel.
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. In the conversion method of the conversion device for transferring data between,
The three units of the synchronous multiplex communication device and the conversion device are set as one group, and the clock synchronization dependency of the clock master, the first clock slave, or the second clock slave is set, and the first and second clock slaves are set. The converting apparatus sets a specific one channel among the allocated channels from the converting apparatus that has set the clock master as the first master channel, and the converting apparatus that sets the second clock slave sets the first clock slave. A master-slave setting step of setting a specific one channel among the assigned channels from the converted converter as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. And controlling the clock frequency of the variable clock unit so that the reception buffer amount is stabilized at the center value after activation, and synchronizing the clock with another synchronous / asynchronous communication converter in the set state of the clock master. Slave synchronization control step;
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the clock frequency of the variable clock unit is controlled so that the amount of the reception buffer is stabilized at the center value, and clock synchronization is performed with another synchronous / asynchronous communication conversion device in the setting state of the second clock slave. A second clock slave synchronization control step;
A conversion method characterized by comprising:
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
The three of the synchronous multiplex communication system with converter apparatus as a group, the clock master, set one of the clock synchronization dependency of the first clock slave or second clock slave, said first and second clock slave The set conversion device sets a specific one channel among the assigned channels from the conversion device that sets the clock master as the first master channel, and the conversion device that sets the second clock slave sets the first clock slave as the first master channel. A master-slave setting step of setting one specific channel among the assigned channels from the set conversion device as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. Steps,
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the second clock for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with the other conversion device in the setting state of the second clock slave. Slave synchronization control step;
A program characterized by having executed.
Inserted and connected between a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal and an asynchronous communication network composed of devices that transfer data asynchronously. To the computer of the conversion device that transfers data between
The three of the synchronous multiplex communication system with converter apparatus as a group, the clock master, set one of the clock synchronization dependency of the first clock slave or second clock slave, said first and second clock slave The set conversion device sets a specific one channel among the assigned channels from the conversion device that sets the clock master as the first master channel, and the conversion device that sets the second clock slave sets the first clock slave as the first master channel. A master-slave setting step of setting one specific channel among the assigned channels from the set conversion device as the second master channel;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. Steps,
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving conversion step to send to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. Clock master synchronization control step,
It becomes effective in the setting state of the first clock slave, and when the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, the first clock slave synchronization control for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value after activation and synchronizing the clock with another conversion device in the set state of the clock master. Steps,
It becomes effective in the setting state of the second clock slave, and when the amount of reception buffer stored in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated. Then, after starting, the second clock for controlling the clock frequency of the variable clock unit so as to stabilize the reception buffer amount at the center value and synchronizing the clock with the other conversion device in the setting state of the second clock slave. Slave synchronization control step;
A reception buffer that is enabled in the setting state of the second clock slave, measures the packet reception density of the second master channel, and measures the amount of reception buffer when the abnormality detection state of the packet reception density continues for a predetermined time. A clock master monitoring step of switching from the reception buffer of the second master channel to the reception buffer of the first master channel;
The computer-readable recording medium characterized by storing the program which performs.
A master converter set as a clock master connected to an asynchronous communication network composed of devices that asynchronously transfer data to a synchronous multiplex communication device that transfers multi-frame data of a plurality of channels in synchronization with a clock signal;
A first slave conversion device in which another synchronous multiplex communication device is set as a first clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a first master channel;
A second slave conversion device in which another synchronous multiplex communication device is set as a second clock slave connected to the asynchronous communication network, and a specific one of the assigned channels is set as a second master channel;
In a communication system for transferring data between a plurality of synchronous multiplex communication devices,
The master converter is
A master-slave setting unit that sets the clock master in itself, with the three units of the synchronous multiplex communication device and the conversion device as one group,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
It becomes valid in the setting state of the clock master, and when the amount of reception buffer accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is fixed at a predetermined center frequency and activated. A clock master synchronization control unit,
With
The first slave converter is
The three units of the synchronous multiplex communication device and the conversion device are set as one group, and the first clock slave is set to itself, and one specific channel among the assigned channels from the clock master conversion device is set as the first master channel. Master / slave setting section to be set,
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
When the reception buffer amount accumulated in the reception buffer of the first master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated, and after activation, the reception buffer amount is set to the center value. A first clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to be stable, and to synchronize the clock with another communication system in the setting state of the clock master;
With
The second slave converter is
The three units of the synchronous multiplex communication device and the conversion device are set as one group, and the second clock slave is set to itself, and one specific channel among the assigned channels from the clock master conversion device is set as the first master channel. A master / slave setting unit configured to set and set one specific channel among the assigned channels from the first clock slave conversion device as a second master channel;
A variable clock unit capable of variably controlling the frequency of the output clock signal;
Transmission conversion in which multi-frame data received from the synchronous multiplex communication device is channel-distributed and accumulated in each transmission buffer, and then asynchronous transmission data is generated from the accumulated data in the transmission buffer and transmitted to the asynchronous communication network at regular intervals. And
Asynchronous data received from the asynchronous communication network is distributed and stored in each reception buffer, and multiframe data is generated from the data stored in the reception buffer in synchronization with the clock signal of the variable clock unit. A receiving converter for transmitting to the device;
When the reception buffer amount accumulated in the reception buffer of the second master channel reaches a predetermined center value, the variable clock unit is set to the center frequency and activated, and after activation, the reception buffer amount is set to the center value. A second clock slave synchronization control unit configured to control the clock frequency of the variable clock unit so as to be stable, and to synchronize with another communication system in a setting state of the second clock slave;
A reception buffer that is enabled in the setting state of the second clock slave, measures the packet reception density of the second master channel, and measures the amount of reception buffer when the abnormality detection state of the packet reception density continues for a predetermined time. A communication system comprising a clock master monitoring unit for switching from the reception buffer of the second master channel to the reception buffer of the first master channel.

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