JP5008124B2 - Scan clock distribution system and semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a scan clock distribution method and system in which a scan test method, which is an LSI test facilitating technique, is provided, and in particular, an aspect in which there are a plurality of clock domains that define a range of circuits that operate with the same clock (hereinafter, “ The present invention relates to a scan clock distribution method and system according to “multi-clock domain”.

  With the recent increase in scale and integration of LSIs, the importance of LSI test facilitating methods aimed at improving test quality is increasing. Since the improvement of the failure detection rate by the LSI tester apparatus is directly related to the quality of the product, the improvement of the failure detection rate is an important issue. A particularly important issue is to improve the detection rate of a failure in which a signal change is not transmitted on a path between flip-flops within a specified time, that is, a delay fault.

  In addition, the increase in the scale of LSIs has led to the complexity of the functions to be mounted, and the overhead of additional circuits and dedicated test terminals provided to avoid the accompanying difficulty of testing and increase in product shipping test costs. An efficient test design technique that can be minimized is desired.

  Therefore, as a method for testing the above delay fault, there is a transition delay fault test using a scan test method, which will be described below. 1 shows a scan clock distribution system, which shows a typical configuration example of scan clock distribution laid out in accordance with a scan test method that is an LSI test facilitating technique.

  Further, this configuration example has a multi-clock domain and operates at a different clock frequency for each clock domain. Reference numerals 30, 31, and 32 are CTS (Clock Tree Synthesis) buffers, which are used to define a buffer group that constitutes a clock tree in which the skew of the clock signal distributed to the synchronization circuits belonging to each clock domain is minimized by clock tree synthesis. Represents

  Reference numerals 10, 11, and 12 denote 1/2, 1/4, and 1/8 frequency dividers, respectively, that output a frequency-divided signal that is phase-synchronized with the same clock signal as a source. Reference numeral 2 denotes a PLL (Phase Locked Loop) circuit, and a clock signal oscillated by this circuit is a source of a clock signal common to each of the frequency dividers 10, 11, and 12.

N1 represents a node, and in particular represents a branch point that distributes the clock signal transmitted by the PLL circuit 2 to each of the frequency dividers 10, 11, and 12.

  Reference numerals 20, 21, and 22 are selectors that are switched between the normal operation mode and the scan mode, and are arranged in the subsequent stage of each of the frequency dividers 20, 21, and 22. SM indicates a scan mode signal, and SC0, SC1, and SC2 indicate scan clock signals supplied from outside the LSI.

  When the scan mode signal SM is low, the scan clock distribution system 1 enters the normal operation mode, and selectively outputs the frequency-divided signals output from the frequency dividers 10, 11, 12 to the CST buffers 30, 31, 32, respectively. Enter. On the other hand, when the scan mode signal SM is High, the scan mode is entered, and each of the scan clock signals SC0, SC1, SC2 is selectively input to each of the CST buffers 30, 31, 32.

  As described above, the clock signal supply source differs between the normal operation mode and the scan mode, but the clock tree and the CTS buffer, which are the main paths for distributing the clock signal to the synchronization circuit at the end of the clock domain, are shared. It has the composition which becomes.

  N10, N11, N12, and N20, N21, and N22 indicate nodes, and in particular, indicate immediately before the input terminals of the selectors 20, 21, and 22, respectively.

  Reference numerals 40, 41, and 42 denote scan flip-flops (hereinafter also referred to as "scan FFs"), which are synchronous circuits belonging to different clock domains, and specifically, each of the CTS buffers 30, 31, and 32 is distributed. Synchronization is achieved by the clock signal.

  N30, N31, and N32 indicate nodes, and particularly represent immediately before the clock input terminals of the scan FFs 40, 41, and 42.

  According to the conventional technique, a scan clock signal in an LSI scan clock distribution system having a multi-clock domain is supplied from a different external terminal for each clock domain.

  Here, a description of the configuration of the scan clock distribution system 1 shown in FIG. 1 will be added. TM is a test mode signal, SI is a scan-in input signal, and SO is a scan-out output signal.

  The scan FFs 40, 41, and 42 are configured by D-type flip-flops to which data is input via a selector, and the selector is switched between a scan shift mode and a scan capture shift mode.

  Reference numerals 50, 51, 52 and 59 denote combinational circuits to be tested in the scan mode, 70 and 71 denote inverters, and 60 and 61 denote lock-up latches. The lock-up latches 60, 61 are inserted between each of the scan chain consisting of the scan FFs 40, 41, 42 and, if this aspect is described in more detail, two clocks belonging to different clock domains in the multi-clock domain. Inserted between scan FFs.

  N40, N41, and N42 indicate nodes, particularly immediately after the data output terminals of the scan FFs 40, 41, and 42. Similarly, N50, N51, N52, and N59 also indicate nodes, particularly immediately after the data output terminals of the combinational circuits 50, 51, 52, and 59.

  The scan clock distribution system 1 enters the scan shift mode when the scan mode signal SM is High, that is, the scan mode and the test mode signal TM is High, and the shift by the scan chain composed of the scan FFs 40, 41, 42 is performed. A register operation, that is, a scan shift operation is performed.

  On the other hand, when the scan mode (the scan mode signal SM is High) and the test mode signal TM is Low, the scan capture mode is entered, and the scan FFs 40, 41, 42 are combined circuits 59 appearing at nodes N59, N50, N51, The output signals of 50 and 51 are synchronously output to the nodes N40, N41 and N42, so-called launch operation is performed, and then the scan FFs 41 and 42 appear at the nodes N40 and N41 by the previous synchronous output. Based on the output signal, a so-called capture operation is performed in which the output signal as the operation result of the combinational circuits 50 and 51 appearing at the nodes N50 and N51 is latched in the scan FFs 41 and 42 themselves. Details of these operations will be described later using a timing chart.

  FIG. 2 shows a timing chart when the scan clock distribution system 1 of FIG. 1 is in the normal operation mode (SM = “Low” and TM = “Low”).

The clock signal oscillated and output by the PLL circuit 2 has a period T ₀ , is distributed to the frequency dividers 10, 11, and 12, and reaches the nodes N 10, N 11, and N 12 after being divided. At this time, each frequency- _divided signal has periods 2T ₀ , 4T ₀ , and 8T ₀ , and requires delay times t _DV0 , t _DV1 , and t _DV2 based on the node N1 that is a branch point. Furthermore, each frequency-divided signal is distributed to each synchronous circuit (corresponding to each scan FF 40, 41, 42 in this example) via the CTS buffers 30, 31, 32 constituting the clock tree, The terminal nodes N30, N31, and N32 are reached. At this time, delay times t _CTS0 , t _CTS1 , and t _CTS2 are required _{starting from} each of the nodes N10, N11, and N12.

  As described above, the clock distribution to the scan FFs 40, 41, and 42, which are the synchronization circuits at the end of each clock domain constituting the multi-clock domain, is a mode in which the clock reaches each with a fixed delay time from the node N1, That is, an LSI design with phase synchronization is achieved.

As a synchronous operation of the specific data transfer, first scan FF40 captures the signal appearing on the clock edge 2A node base point N59, and to launch the combinational circuit 50 via the delay time t _FF0. Then, combination circuit 50 sends data to the node N50, i.e., next scan FF41 through the delay time _{t CM0.} Therefore, the scan FF 41 captures data according to the clock edge 2B while ensuring the setup time margin t _SETUP , and thus, a series of launch and capture operations are completed. Note that the LSI design is performed so that the transition and propagation of data due to the clock edge next to the clock edge 2A can also secure the hold time margin t _HOLD of the clock edge 2B with respect to the scan FF 41.

Further, the relationship between the clock edge 2B and the clock edge 2C for the scan FF 42 is equal to the relationship between the clock edge 2A and the clock edge 2B of the previous scan FF 41. Here, the delay time t _FF1 is a time for launching data with respect to the clock edge 2B of the scan _FF 42, and the delay time t _CM1 is a propagation time of the combinational circuit 51. Since the selectors 20, 21, and 22 use the same circuit and thus have the same delay time, the relative phase synchronization relationship between the clock domains is not disrupted. Therefore, the delay times of the selectors 20, 21, and 22 are omitted as zero on the timing chart relating to FIG.

  On the other hand, FIG. 3 shows a timing chart in the scan mode (SM = “High”) and in the scan capture mode (TM = “Low”), that is, in the scan capture mode. In particular, the scan clock signals SC0, SC1, and SC2 supplied from outside the LSI are premised on an ideal state in which the phase synchronization between the signals is achieved.

Each of the scan clock signals SC0, SC1, and SC2 has a period of 2T ₀ , 4T ₀ , and 8T ₀ , and delay times t _SC0 , t _SC1 , and t _SC2 based on external terminals supplied from the outside of each LSI. In short, it reaches the nodes N20, N21 and N22. Thereafter, each scan clock signal is distributed to each of the scan FFs 40, 41, and 42 in the multi-clock domain via the CTS buffers 30, 31, and 32 in the same manner as in the normal operation mode, and is sent to the end nodes N30, N31, and N32. Reach.

At this time, since the delay times from the nodes N20, N21, and N22 to the nodes N30, N31, and N32 share the selectors 20, 21, and 22, the nodes N10, N11, and N12 are the base points. The delay times t _CTS0 , t _CTS1 and t _CTS2 are equal. Further, the relative relationship between the delay times t _DV0 , t _DV1 , t _DV2 from the node N1 to the nodes N10, N11, and N12 and the relative relationship between the delay times t _SC0 , t _SC1 , and t _SC2 are equivalent. Assuming that it can be reflected in the LSI design, the relationship between the clock edge 2A and the clock edge 2B of the scan FF 41 in FIG. 2 is the relationship between the clock edge 3A and the clock edge 3B of the scan FF 41 in FIG. This relationship is equivalent in terms of operation margin time such as setup time margin and hold time margin. Similarly, the relationship between the clock edge 2B and the clock edge 2C of the scan FF 42 in FIG. 2 is equivalent to the relationship between the clock edge 3B and the clock edge 3C of the scan FF 42 in FIG.

As a synchronous operation of the specific data transfer, first scan FF40 captures the signal appearing on the clock edge 3A node base point N59, and to launch the combinational circuit 50 via the delay time t _FF0. Then, combination circuit 50 sends data to the node N50, i.e., next scan FF41 through the delay time _{t CM0.} Therefore, the scan FF 41 captures data based on the clock edge 3B while securing the setup time margin t _SETUP , and thus, a series of launch and capture operations are completed. Note that the transition and propagation of data due to the clock edge next to the clock edge 3A also secures the hold time margin t _HOLD of the clock edge 3B with respect to the scan FF 41. Further, the relationship between the clock edge 3B and the clock edge 3C for the scan FF 42 is equal to the relationship between the clock edge 3A and the clock edge 3B of the previous scan FF 41. Here, the delay time t _FF1 is a time for launching data with respect to the clock edge 3B of the scan _FF 42, and the delay time t _CM1 is a propagation time of the combinational circuit 51.

As described above, in FIG. 3, the time for the signal change to propagate on the path between the flip-flops, that is, the delay time _tCM0 and the delay time _tCM1 are propagated within the specified time, and normal launch operation and capture operation are performed. ing. That is, it can be determined that the product is a normal LSI that does not cause a transition delay fault. A series of these tests is a transition delay fault test using a scan test method.

As other conventional techniques, there are Patent Documents 1 and 2 relating to a test method for an LSI having a multi-clock domain.
JP 2003-270301 A (FIGS. 1 and 17) Japanese Patent Laying-Open No. 2005-026335 (FIG. 1)

  However, in the LSI scan clock distribution system having the conventional multi-clock domain as described above, the scan clock signal in the product shipment test is supplied from the LSI tester device via the external terminal, and is supplied to the scan FF for each clock domain. There is a problem that the skew between the scan clock signals is limited to the skew accuracy between the signals generated by the LSI tester device.

This problem will be further described with reference to the timing chart shown in FIG. FIG. 4 shows a timing chart in the scan mode (SM = “High”) and the scan capture mode (TM = “Low”), that is, in the scan capture mode, as in FIG. Therefore, the scan clock signal SC1 supplied from the LSI tester device has a phase delayed from the SC0 by the LSI tester device skew time t _SKEW . Scan clock signal SC2 is in phase synchronization with SC1.

Similarly to FIG. 3, each of the scan clock signals SC0, SC1, and SC2 has a cycle of 2T ₀ , 4T ₀ , and 8T ₀ and has a delay time t _SC0 , t based on an external terminal supplied from outside each LSI. _SC1 and _tSC2 are required to reach the nodes N20, N21, and N22. Thereafter, each scan clock signal is distributed to each of the scan FFs 40, 41, and 42 in the multi-clock domain via the CTS buffers 30, 31, and 32 in the same manner as in the normal operation mode, and is sent to the end nodes N30, N31, and N32. Reach.

However, the phase difference between the nodes N30 and N31 in FIG. 4 (the relationship between the clock edge 4A and the clock edge 4B of the scan FF 41 in FIG. 4) is the phase difference between the end nodes N30 and N31 in FIG. the relationship) between the clock edge 3A and the clock edge 3B of the scan FF 41, becomes further adding relationship the LSI tester skew time _{t sKEW} the scan clock signal SC0 and SC1. As a result, the hold time of the scan FF41 in the state of FIG. 4, shortened by the phase difference _{t SKEW} than the hold time of the scan FF41 in the state of FIG. 3, falls into a state that can not satisfy the hold time margin _{t HOLD.}

Note that the setup time of the scan FF41 in the state of FIG. 4, contrary to the behavior of the hold time, than the setup time of the scan FF41 in the state of FIG. 3 is extended by the phase difference _{t SKEW,} setup time margin _{t HOLD} Will be in a state that has gained more margin.

The scan FF 41 in the state of FIG. 4 cannot satisfy the hole time margin t _HOLD at the clock edge 4B, propagates erroneous data to the next-stage scan FF 42, and cannot perform the expected normal capture operation. The result of the test judgment will be obtained. In other words, despite the fact that the product is a normal LSI that does not cause a transition delay fault, an erroneous shipment as an LSI that has caused a delay fault due to the presence of skew between signals generated by the LSI tester device There arises a problem of obtaining a test determination result. The recent increase in LSI speed due to semiconductor miniaturization tends to promote this problem. In other words, the shortening of the clock period accompanying the increase in the clock domain applied inside the LSI tends to exceed the improvement in the resolution of the skew between signals generated by the LSI tester device.

  It should be noted that the influence caused by the skew between the scan clock signals supplied to the scan FFs for each clock domain further affects the scan shift mode. In other words, the lockup latches 60 and 61 described above are inserted into the gap between the scan FFs 40, 41, and 42 that belong to different clock domains in the multi-clock domain and constitute the scan chain, thereby correcting the previous skew. Regardless, normal scan shift operation is guaranteed. In other words, the influence of the previous skew is avoided by allowing the overhead of a newly provided additional circuit.

  Therefore, it will be shown that the influence of the previous skew can be avoided by explaining the operation of the lock-up latches 60 and 61. Each of the lock-up latches 60 and 61 becomes active when the clock signal output from the inverters 70 and 71 is High, transmits the data signal appearing at the nodes N40 and N41 to the output, and the previous clock signal transitions to Low. The data signal appearing at the immediately preceding nodes N40 and N41 is latched at the moment, and the data signal is held while the previous clock signal is Low.

As shown in FIG. 4, the scan clock signal SC1 is assumed a state in which the phase is delayed by LSI tester skew time _{t SKEW} to SC0, a scan shift operation by paying attention to the lock-up latch 60 and the scan FF40,41 explain. At the moment when the clock signal appearing at the node N30, that is, the clock signal input to the scan FF 40 transitions to High, the scan FF 40 captures, holds and outputs the immediately preceding scan-in input signal SI. At the same time, the lockup latch 60 latches, holds and outputs the data signal appearing at the immediately preceding node N40.

On the other hand, the clock signal appearing at the node N31 inputted to the scan FF 41 is the arrival time difference with respect to the time when the scan clock signal SC0 reaches the scan FF 40 {(t _SC1 + t _CTS1 ) − (t _SC0 + t _CTS0 )} In contrast to this, the LSI tester device skew time _{SKEW is} delayed to make a transition to High. At this time, the lockup 60 holds and outputs the data signal that appeared at the node N40 before the scan FF 40 described above captures and holds the scan-in input signal SI and outputs it to the node N40, and This holding state is maintained while the clock signal appearing at the node N30 is in the high state. Therefore, even if a delay of the clock signal appearing at the node N31 input to the scan FF 41 described above occurs, the scan FF 40 described above captures and holds the scan-in input signal SI and outputs it to the node N40. The data signal appearing at the node N40 can be normally captured and held and output.

  In order to solve the above problem, in a scan clock distribution system that supplies a scan clock signal to a root node of a clock signal supplied to a multi-clock domain in a normal operation mode and a scan clock signal in a scan mode, the scan clock signal supplied to the clock domain is divided. A frequency divider that switches the frequency dividing ratio according to the scan mode is provided.

  The scan clock distribution system according to the present invention includes the frequency divider having the same delay time before and after switching the frequency division ratio.

  The scan clock distribution system according to the present invention is characterized in that the frequency division ratio of the frequency divider is made equal between the clock domains in the scan shift mode.

  In the scan clock distribution system of the present invention, the relative ratios between the clock domains in the frequency division ratio in the normal operation mode and in the scan capture mode are the same, and the scan capture is higher than in the normal operation mode. It is characterized by a small frequency division ratio in mode.

  According to the present invention, there is provided an LSI scan clock distribution system having a multi-clock domain that can eliminate the influence of skew between signals generated by an LSI tester device with respect to a scan clock signal supplied from an external terminal by the LSI tester device. can do.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description will be omitted as necessary for the sake of clarity.

Embodiment 1 FIG.
FIG. 5, ie, 101 shows a scan clock distribution system, which shows a scan clock distribution configuration laid out in accordance with a scan test method that is an LSI test facilitating method according to the first embodiment of the present invention. The connection relationships of the scan FFs and combinational circuits shown after the nodes N13, N14, and N15 are the same as those shown in FIG. However, the lock-up latches 60, 61 and inverters 70 and 71 are removed, scanned inch Ein consisting scan FF40,41,42 therefore does not include a lockup latch while the same scan chain sequence and the order shown in FIG. 1 It is composed. The reason why the lock-up latch is unnecessary is an effect due to the present invention, which will be described later.

Reference numeral 2 denotes a PLL circuit as a clock generation source, 10 denotes a 1/2 frequency divider, SM denotes a scan mode signal, both of which are the same as those shown in FIG. Reference numeral 23 denotes a selector which can be switched between the normal operation mode and the scan mode, and SCK denotes a unique scan clock signal supplied from outside the LSI. The scan clock signal SCK and the clock signal oscillated by the PLL circuit 2 are input to the selector 23 via the nodes N23 and N2, respectively, and output to the node N3.
Reference numerals 111 and 112 denote frequency dividers with frequency division ratio switching. The configurations will be described later with reference to FIGS. 6 and 8, and the operations will be described with reference to FIGS. Incidentally node N3, the scan clock signal SCK or branched clock signal P LL circuit 2, 1 frequency divider 10 of 2 minutes, a branch point to be distributed to each of the division ratio switching with divider 111 But there is.

  The configuration of the frequency divider 111 with frequency division ratio switching will be described with reference to FIG. Reference numerals 206 and 207 denote flip-flop circuits based on a shift register configuration via a NAND circuit 202 and an anti-matching circuit 203. Similarly, FIG. 8 shows the configuration of the frequency divider 112 with frequency division ratio switching. Reference numerals 306, 307, and 308 denote flip-flop circuits. The NAND circuit 302, the anti-matching circuit 303, the AND circuit 304, and the 305 Based on a shift register configuration via a matching circuit. Reference numerals 201 and 301 denote negative circuits, to which a frequency division ratio switching signal is input.

The operation of the frequency divider 111 with frequency division ratio switching will be described with reference to FIG. When the frequency division ratio switching signal is Low, the frequency-divided clock output signal of the frequency divider 111 with frequency division ratio switching is a signal divided by a quarter of the clock input signal. When the flip-flop circuits 206 and 207 both output Low, that is, when the operation starts from the reset state, the quarter-divided clock output signal also rises with respect to the first rising edge of the clock input signal. A synchronized state of outputting an edge is obtained. On the other hand, when the frequency division ratio switching signal is High, the frequency-divided clock output signal of the frequency divider 111 with frequency division ratio switching is a signal divided by half with respect to the clock input signal. If the flip-flop circuits 206 and 207 start operation from a state where both output Low, phase-synchronization that outputs the rising edge of the half-divided clock output signal with respect to the first rising edge of the clock input signal A state is obtained. A common characteristic that does not depend on the state of the division ratio switching signal, that is, the divided clock output signal with respect to the clock input signal regardless of whether the divided clock output signal is divided by a quarter or a half. The delay until is changed is determined by the delay time t _FF7 of the flip-flop circuit 207 in the final stage.

Similarly, the operation of the frequency divider 112 with frequency division ratio switching will be described with reference to FIG. When the frequency division ratio switching signal is Low, the frequency-divided clock output signal of the frequency divider 112 with frequency division ratio switching is a signal divided by 1/8 of the clock input signal. Then, if the flip-flop circuits 306, 307, and 308 all output Low, that is, if the operation starts from the reset state, the 1/8 divided clock output signal with respect to the first rising edge of the clock input signal In addition, a synchronous state in which a rising edge is output is obtained. On the other hand, when the frequency division ratio switching signal is High, the frequency-divided clock output signal of the frequency divider 112 with frequency division ratio switching is a signal divided by half with respect to the clock input signal. If the flip-flop circuits 306, 307, and 308 are all started to output Low, the half-divided clock output signal also outputs a rising edge with respect to the first rising edge of the clock input signal. A phase synchronization state is obtained. A common characteristic that does not depend on the state of the division ratio switching signal, that is, the divided clock output signal with respect to the clock input signal regardless of whether the divided clock output signal is divided by 1/8 or 1/2. The delay until is changed is determined by the delay time t _FF8 of the flip-flop circuit 308 in the final stage.

  Therefore, a description of the configuration related to the frequency dividers 111 and 112 with frequency division ratio switching in FIG. 5 is further added. The clock input signal of each of the frequency dividers 111 and 112 is inputted with the clock signal branched from the node N3, the frequency division ratio switching signal is inputted with the scan mode signal SM, and the outputted divided clock output Each of the signals is input to the CTS buffers 31 and 32 via the nodes N14 and N15. The delay time of the selector 23 is omitted as zero as applied on the timing chart relating to FIG.

  Although not shown, a circuit may be provided for supplying signals for resetting the flip-flop circuits 206, 207, 306, 307, and 308 together and simultaneously. The reset signal is also supplied to the 1/2 frequency divider 10 to reset all the clock domains at once and to the first rising edge of the clock signal supplied to the node N3. Thus, a phase synchronization state over the entire scan clock distribution system 101 is obtained in which the divided clock output signal supplied to each clock domain also outputs a rising edge.

  Next, the operation of the scan clock distribution system 101 according to the first embodiment of the present invention will be described. FIG. 10 shows a timing chart when the scan clock distribution system 101 is in the normal operation mode (SM = “Low” and TM = “Low”).

The clock signal oscillated and output by the PLL circuit 2 has a period T ₀ and is distributed to the half frequency divider 10 and the frequency dividers 111 and 112 with frequency division ratio switching. At this time, the frequency dividers 111 and 112 with frequency division ratio switching function as frequency dividers each having a frequency division ratio of 1/4 and a frequency division ratio of 1/8. Therefore, the frequency- _divided signals reaching the nodes N13, N14, and N15 have periods 2T ₀ , 4T ₀ , and 8T ₀ , respectively, and the delay times t _DV0 , t _DV3 , t _{DV4 from the} node N3 that is a branch point. Have The delay time _{t DV3, t DV4,} each equal to the delay time _{t FF8} shown in the delay time _{t FF7} and 9 shown in FIG.

    The delay times after the nodes N13, N14, N15 are the same as the delay times after the nodes N10, N11, N12 shown in FIG. The clock distribution to the scan FFs 40, 41, 42 is such that the clock arrives at a fixed delay time from the node N3, that is, an LSI design with phase synchronization.

  As a result, the relationship between the clock edge 2A and the clock edge 2B is equal to the relationship between the clock edge 10A and the clock edge 10B. Similarly, the relationship between the clock edge 2B and the clock edge 2C is equal to the relationship between the clock edge 10B and the clock edge 10C.

  FIG. 11 shows a timing chart in the scan mode (SM = “High”) and in the scan capture mode (TM = “Low”), that is, in the scan capture mode.

The only scan clock signal SCK has a cycle T ₁ and requires a delay time t _SCK from an external terminal supplied from outside the LSI to the node N 23, and further via the selector 23 to a node N 3 that is a branch point Is reached, it is distributed to the 1/2 frequency divider 10 and the frequency dividers 111 and 112 with frequency division ratio switching. At this time, the frequency division ratio switching with divider 111, 112 serves as a frequency divider having both the frequency division ratio 1/2, divided signal reaches the node N13, N14, N15 all have period 2T ₁ .

  As described above, in an LSI scan clock distribution system having a multi-clock domain, by integrating the scan clock signals supplied from the external terminals by the LSI tester device into a single book, the skew between signals generated by the LSI tester device is reduced. The aspect projected during the scan clock for every multi-domain, itself can be excluded. This eliminates the need for a lock-up latch that has to be provided in order to avoid the influence of the skew between the scan clock signals on the scan shift mode. Further, since the test input terminals and the external input terminals of the scan clock signal provided can be reduced, it can be said that this is an efficient test design technique that can minimize the test overhead.

  As described with reference to FIGS. 7 and 9, the frequency dividers 111 and 112 with frequency division ratio switching do not depend on the state of the frequency division ratio switching signal until the frequency division clock output signal changes with respect to the clock input signal. Implementation of a mode in which the delay times are equal is realized. As a result, the relationship between the delay time of the clock signal from the node N3 to the end nodes N30, N31, and N32 and the relative phase synchronization state is divided by the frequency dividers 111 and 112 with frequency division ratio switching. It does not depend on the ratio switching signal, that is, the scan mode signal SM, and can be made equal regardless of the state of the normal operation mode or the scan capture mode.

As described when explaining the timing chart of FIG. 3, the relative relationship between the delay times t _DV0 , t _DV1 , t _DV2 from the node N1 to the nodes N10, N11, N12 and the delay times t _SC0 , t _SC1. , _TSC2 has been established on the premise that the relative relationship of _tSC2 can be reflected in the LSI design so as to be equivalent. However, according to the present invention, the normal operation mode and the scan capture mode are used in the LSI design. There is no need to adjust the delay time between

If an additional description to a timing chart shown in somewhat 11 Now, first scan FF40 captures the signal appearing at the node N59 to the clock edge 11A as a base point, to launch into the combination circuit 50 and via the delay time t _FF0 . Then, combination circuit 50 sends data to the node N50, i.e., next scan FF41 through the delay time _{t CM0.} Therefore, the scan FF 41 captures data according to the clock edge 11B while securing the setup time margin t _SETUP , and thus, a series of launch and capture operations are completed. Note that the transition and propagation of data due to the clock edge next to the clock edge 11A also secures the hold time margin t _HOLD of the clock edge 11B with respect to the scan FF 41. Further, the relationship between the clock edge 11D and the clock edge 11E for the scan FF 42 is equal to the relationship between the clock edge 11A and the clock edge 11B of the previous scan FF 41.

The normal operation mode of FIG. 10 and the scan capture mode of FIG. 11 are compared with respect to the number of patterns necessary for the series of the launch operation of the scan FF 40 to the capture operation of the scan FF 41 described above. In FIG. 10, the clock edge one cycle before the clock edge 10A that needs to be phase-synchronized with the clock edge one cycle before the clock edge 10B (the clock for the capture operation) becomes the first reference point, and the clock edge 10B The clock edge after one cycle of the clock edge 10A that is in phase synchronization with the second reference point. If the period T ₀ is a pattern unit, the number of patterns of the first reference point to the second reference point is 4 patterns. On the other hand, in FIG. 11, the clock edge 11A that needs to be phase-synchronized with the clock edge one cycle before the clock edge 11B (clock for the capture operation) is the first reference point, and the relationship between the clock edge 11B and the phase synchronization. The clock edge after one cycle of the clock edge 11A is the second reference point. If the period T ₁ and pattern units, patterns the number of the first reference point to the second reference point is 2 pattern. That is, in the scan capture mode, the number of patterns to be generated can be reduced by unifying the frequency division ratios of the scan clock signals supplied between different clock domains. In the scan clock distribution system shown in FIG. 5, the frequency division ratio of the 1/2 frequency divider 10 having the minimum frequency division ratio in the normal operation mode is unified, that is, the frequency divider with frequency division ratio switching. 111 and 112 are controlled by the scan mode signal SM so that the division ratio is equal to 2 in the scan capture mode.

In FIG. 11, the time for signal change to propagate on the path between the flip-flops, that is, the delay time _tCM0 and the delay time _tCM1 are propagated within the specified time, and normal launch operation and capture operation are performed. . Therefore, further, a signal transmitted on the path between the scan FF 40 and FF 41 and on the path between the scan FF 41 and FF 42 obtained when the period T ₁ is narrowed to the limit at which these series of transition delay fault tests are determined to be normal. time changes, each is completely equal i.e. the delay time _{t CM0} and the delay time _{t CM1.}

  As described above, the phase synchronization relationship of the clock signals distributed to the scan FFs belonging to different clock domains can be completely matched between the normal operation mode and the scan capture mode. The accurate transition delay fault test can be used.

Embodiment 2. FIG.
12 shows a scan clock distribution system, and shows the configuration of the scan clock distribution laid according to the scan test method, which is an LSI test facilitating method according to the second embodiment of the present invention.

  Reference numerals 43, 45, and 46 denote scan FFs. The scan FFs 45 and 46 belong to the same clock domain, and only the scan FF 43 belongs to a different clock domain. Specifically, the former is the CTS buffer 35 and the latter is the latter. The CTS buffer 33 is synchronized by a clock signal distributed. N33 and N35 indicate nodes. In particular, the former indicates immediately before the clock input terminal of the scan FF 43, and the latter indicates immediately before the clock input terminal of the scan FFs 45 and 46. TM is a test mode signal, SI is a scan-in input signal, and SO is a scan-out output signal. The scan FFs 43, 45, and 46 are configured by D-type flip-flops to which data is input via a selector, and the selector is switched between a scan shift mode and a scan capture shift mode. Reference numerals 53, 55, 56, and 58 denote combinational circuits to be tested in the scan mode. N43, N45, and N46 indicate nodes, particularly immediately after the data output terminals of the scan FFs 43, 45, and 462. Similarly, N53 and N54 nodes are shown, particularly immediately after the data output terminal of the combinational circuit 53, and N58 immediately after the data output terminal of the combinational circuit 58.

Reference numeral 2 denotes a PLL circuit which is a clock generation source, and SM denotes a scan mode signal, both of which are the same as those shown in FIG. Reference numeral 24 denotes a selector that can be switched between the normal operation mode and the scan mode. SCK denotes a single scan clock signal supplied from outside the LSI. The clock signal oscillated by the scan clock signal SCK and the PLL circuit 2 includes nodes N24 and N4, respectively. To the selector 24 and output to the node N5. The frequency divider 111 with frequency division ratio switching has already been described with reference to FIG. Reference numeral 113 denotes a frequency divider with frequency division ratio switching. The configuration will be described with reference to FIG. 13 and the operation will be described with reference to FIGS. Incidentally node N5, the scan clock signal SCK or branched clock signal P LL circuit 2, 1 frequency divider 10 of 2 minutes, a branch point to be distributed to each of the division ratio switching with divider 111 But there is.

  FIG. 13 shows the configuration of the frequency divider 113 with frequency division ratio switching. 406, 407, and 408 are flip-flop circuits, which include a NAND circuit 402, an anti-match circuit 403, an AND circuit 404, and a match circuit 405. Based on the shift register configuration. Note that 401 is a negative circuit, and 409 is a NAND circuit, to which a division ratio switching signal is input.

First, the operation of the frequency divider 113 with frequency division ratio switching will be described with reference to FIG. Regardless of the signal of the frequency division ratio switching signal B, when the frequency division ratio switching signal A is Low, the frequency division clock output signal of the frequency divider 113 with frequency division ratio switching is 1/8 of the clock input signal. This is a divided signal. When the flip-flop circuits 406, 407, and 408 are all outputting Low, that is, when the operation is started from the reset state, the 1/8 divided clock output signal with respect to the first rising edge of the clock input signal. In addition, a synchronous state in which a rising edge is output is obtained. When the frequency division ratio switching signals A and B are both High, the frequency-divided clock output signal of the frequency divider 113 with frequency division ratio switching is a signal divided by half with respect to the clock input signal. Similarly, if the flip-flop circuits 406, 407, and 408 are all started to output Low, the half-divided clock output signal is also the rising edge with respect to the first rising edge of the clock input signal. Can be obtained. Further, in FIG. 15, when the division ratio switching signal A is High and the division ratio switching signal B is Low, the divided clock output signal of the divider 113 with the division ratio switching is 4 with respect to the clock input signal. The signal is divided by a factor of one. Similarly, if the flip-flop circuits 406, 407, and 408 are all outputting Low, that is, if the operation is started from the reset state, a quarter-frequency divided clock output is performed with respect to the first rising edge of the clock input signal. A synchronous state in which the signal also outputs a rising edge is obtained. A common characteristic that does not depend on the state of the frequency division ratio switching signal, that is, whether the frequency-divided clock output signal is 1/8, 1/2, or 1/4. In other words, the delay until the divided clock output signal changes with respect to the clock input signal is determined by the delay time _tFF8 of the flip-flop circuit 408 at the final stage.

  Therefore, a description of the configuration relating to the frequency dividers 113 and 111 with frequency division ratio switching in FIG. 12 is further added. Each of the clock input signals of the frequency dividers 113 and 111 receives the clock signal branched from the node N5, and the output frequency-divided clock output signals are respectively input to the CTS buffers 33 and 35 via the nodes N16 and N17. This is a configuration. The frequency division ratio switching signal of the frequency divider 111 is inputted with the scan mode signal SM, and the frequency division ratio switching signals A and B of the frequency divider 113 are inputted with the scan mode signal SM and the test mode signal TM, respectively. . The delay time of the selector 24 is omitted as zero as applied on the timing chart relating to FIG.

  Although not shown, the flip-flop circuits 406, 407, and 408 and the flip-flop circuits 206 and 207 that constitute the frequency divider 111 may be provided together with a circuit that supplies a signal for resetting simultaneously. . As a result, the reset signal collectively resets all clock domains, and the divided clock output signal supplied to each clock domain with respect to the first rising edge of the clock signal supplied to the node N5. In addition, the phase synchronization state over the entire scan clock distribution system 201 that outputs the rising edge is obtained.

  Next, the operation of the scan clock distribution system 201 according to the second embodiment of the present invention will be described. FIG. 16 shows a timing chart when the scan clock distribution system 101 is in the normal operation mode (SM = “Low” and TM = “Low”).

The clock signal oscillated and output by the PLL circuit 2 has a period T ₀ and is distributed to the frequency dividers 113 and 111 with frequency division ratio switching. At this time, the frequency dividers 113 and 111 with frequency division ratio switching function as frequency dividers each having a frequency division ratio of 1/8 and a frequency division ratio of 1/4. Therefore, the frequency- _divided signals reaching the nodes N16 and N17 have periods 8T ₀ and 4T ₀ , respectively, and have delay times t _DV6 and t _DV7 based on the node N5 which is a branch point. The delay time _{t DV6, t DV 7} are each equal to the delay time _{t FF7} shown in the delay time _{t FF9} and 7 shown in FIG. 14. Further, each frequency-divided signal is distributed to each synchronization circuit in the multi-clock domain via the CTS buffers 33 and 35 constituting the clock tree, and reaches the end nodes N33 and N35. At this time, delay times t _CTS3 and t _CTS4 are required _starting from each of the nodes N16 and N17.

As a synchronous operation of the specific data transfer, first scan FF43 captures the signal appearing at the node N58 to the clock edge 16A as a base point, to launch into the combination circuit 53 and via the delay time t _FF3. Then, combination circuit 53 is node N53 via the delay time _{t CM3,} i.e. and sends the data to the subsequent scan FF 45, the node via the delay time _{t CM4} N54, i.e. sends the data to the subsequent scan FF46. Therefore, the scan FF 45 captures data based on the clock edge 16B while ensuring the setup time margin t _SETUP . On the other hand, the scan FF 46 also captures data according to the clock edge 16BB while securing the setup time margin t _SETUP , and this completes a series of launch operations and capture operations.

  On the other hand, FIG. 17 shows a timing chart in the scan mode (SM = “High”) and the scan capture mode (TM = “Low”), that is, the scan capture mode, and the scan mode (SM = “High”). In the scan capture mode (TM = “High”), that is, the timing chart in the scan shift mode is shown.

First, the operation of the timing chart portion in the scan capture mode will be described. The only scan clock signal SCK has a period T _1, and is supplied from outside the LSI to the node N24, after further reaches the node N5 is a branch point via the selector 24, the frequency division ratio switching with divider 113 and 111 are distributed. At this time, the frequency dividers 113 and 111 with frequency division ratio switching function as frequency dividers having a frequency division ratio of 1/4 and 1/2, respectively, and the frequency-divided signals reaching the nodes N16 and N17 each have a period. 4T ₁ and 2T ₁

As a synchronous operation of the specific data transfer, first scan FF43 captures the signal appearing at the node N58 to the clock edge 17A as a base point, to launch into the combination circuit 53 and via the delay time t _FF3. Then, combination circuit 53 is node N53 via the delay time _{t CM3,} i.e. and sends the data to the subsequent scan FF 45, the node via the delay time _{t CM4} N54, i.e. sends the data to the subsequent scan FF46. Therefore, the scan FF 45 captures data according to the clock edge 17B while ensuring the setup time margin t _SETUP . On the other hand, the scan FF 46 also captures data according to the clock edge 17BB while ensuring the setup time margin t _SETUP .

These series of launch operations and capture operations are completely similar to the series of operations shown in FIG. 16, and the only difference is the number of patterns required. Therefore, the normal operation mode of FIG. 16 and the scan capture mode of FIG. 17 are compared with respect to the number of patterns necessary for a series of launch operation of the scan FF 43 to capture operation of the scan FF 45. In FIG. 16, if the period T ₀ is a pattern unit, the number of patterns of the clock edges 16A to 16B is 4 patterns. On the other hand, in FIG. 17, if the period _{T 1} and pattern units, patterns the number of clock edges 17A to clock edge 17B is 2 pattern. That is, regarding the relationship of the relative ratio of the division ratio of the scan clock signal supplied between different clock domains, it is the same between the normal operation mode and the scan capture mode, and the division in the scan capture mode is higher than that in the normal operation mode. It is possible to reduce the number of patterns to be generated due to the reduced circumference ratio.

Next, the operation of the timing chart portion in the scan shift mode will be described. Scan clock signal SCK has a period _{T 2,} the frequency division ratio switching with divider 113, 111 acts as a frequency divider having both the frequency division ratio 1/2, also divided signal reaches the node N16, N17 both have a period 2T _2. Therefore, each of the scan FFs 43, 45, and 46 is supplied with a clock signal having the same period and having the same cycle. FF data can be shifted. If further explanation is added, the shift operation is possible with the period 2T ₂ and the minimum number of patterns.

Other embodiments.
Furthermore, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention described above.

  According to the present invention, the phase synchronization relationship of the clock signals distributed to the scan FFs belonging to different clock domains is completely between the normal operation mode and the scan mode (including the scan capture mode and / or the scan shift mode). In other words, it is possible to perform an accurate transition delay fault test that faithfully reproduces the normal operation mode using the scan test method.

In a scan clock distribution system for an LSI having a multi-clock domain, by integrating the scan clock signals supplied from the external terminals by the LSI tester device into a single book, the skew between the signals generated by the LSI tester device is different for each multi-domain. In addition to eliminating projection during the scan clock, a node (hereinafter referred to as a “root node”) serving as a root of the clock signal in the normal operation mode supplied to the multi-domain and a scan mode (scan) capture mode or / and a scan shift mode) scan clock signal of the root node of the (to a KazuSatoshi common branch point between the node N3 in FIG. 5, the N5) in FIG. 12 and the normal operation mode and the scan mode It depends on that.

  Therefore, as another aspect of the invention, from the viewpoint of switching the clock signal to be supplied between the normal operation mode and the scan mode to the root node of the clock signal, one LSI external terminal for supplying a signal to this root node is provided. Alternatively, a mode in which the clock signal in the normal operation mode to be supplied from the outside of the LSI and the scan clock signal are properly used may be employed.

  Further, one LSI external terminal for supplying a signal to the node N2 of FIG. 5 or the node N4 of FIG. 12 while providing the selector 23 shown in FIG. 5 or the selector 24 shown in FIG. May be supplied. 5 and 12 both supply the scan clock signal SCK from the LSI external terminal. However, a device for automatically generating the scan clock signal is provided inside the LSI, and the node N23 in FIG. 5 or the node N24 in FIG. It is good also as an aspect to supply.

  In order to perfectly match the phase synchronization relationship of the clock signals distributed to the scan FFs belonging to different clock domains between the normal operation mode and the scan mode (including the scan capture mode and / or scan shift mode) The frequency divider with frequency ratio switching has the same delay value without depending on the state of the frequency division ratio switching signal.

  Although Embodiments 1 and 2 show a mode based on a shift register configuration that can be switched to a natural number and an even division ratio, odd or fractional division ratios may be used. In this case, a mode of a device that switches a plurality of frequency dividers using a selector or a multiplexer may be employed.

It is a block diagram of the conventional scan clock distribution system. It is a timing chart which shows operation | movement of the normal operation mode of the conventional scan clock distribution system. It is a timing chart which shows operation | movement when the skew between scan clock signals is zero in the scan capture mode of the conventional scan clock distribution system. It is a timing chart which shows the operation | movement in the case of zero which has the skew between scan clock signals in the scan capture mode of the conventional scan clock distribution system. It is a block diagram of the scan clock distribution system concerning Embodiment 1 of invention. It is a block diagram of the frequency divider with frequency division ratio switching concerning Embodiment 1 of invention. It is a timing chart which shows operation | movement of the frequency divider with frequency division ratio switching concerning Embodiment 1 of invention. It is a block diagram of the frequency divider with other frequency division ratio switching concerning Embodiment 1 of invention. It is a timing chart which shows operation | movement of the other frequency divider with frequency division ratio switching concerning Embodiment 1 of invention. 3 is a timing chart showing an operation in a normal operation mode of the scan clock distribution system according to the first exemplary embodiment of the invention; It is a timing chart which shows operation | movement of the scan capture mode of the scan clock distribution system concerning Embodiment 1 of invention. It is a block diagram of the scan clock distribution system concerning Embodiment 2 of invention. It is a block diagram of the frequency divider with frequency division ratio switching concerning Embodiment 2 of invention. It is a timing chart which shows operation | movement of the frequency divider with frequency division ratio switching concerning Embodiment 2 of invention. It is another timing chart which shows operation | movement of the frequency divider with frequency division ratio switching concerning Embodiment 2 of invention. It is a timing chart which shows operation | movement of the normal operation mode of the scan clock distribution system concerning Embodiment 2 of invention. It is a timing chart which shows operation | movement of the scan capture mode and scan shift mode of the scan clock distribution system concerning Embodiment 2 of invention.

Explanation of symbols

1, 101, 201 Scan clock distribution system 2 PLL circuit 10, 11, 12 Frequency divider 20, 21, 22, 23, 24 Selector 30, 31, 32, 33, 35 CTS buffer 40, 41, 42, 43, 45 , 46 scan FF
50, 51, 52, 53, 55, 56, 58, 59 Combination circuit 60, 61 Lock-up latch 70, 71 Inverters 111, 112, 113 Frequency dividers SCK, SC0, SC1, SC2 Scan clock signal SIN scan-in signal SO scan-out signal SM scan mode signal TM test signal 206, 207, 306, 307, 308.406, 407, 408 flip-flop circuit 202, 302, 402, 409 NAND circuit 203, 303, 403 anti-match circuit 304, 404, AND circuit 305, 405 Match circuit 201, 301, 401 Negative circuit

Claims (4)

A scan clock distribution system that supplies a scan clock signal in a scan mode to a root node of a clock signal supplied to a multi-clock domain in a normal operation mode,
A frequency divider that switches the frequency division ratio for dividing the scan clock signal supplied to the clock domain according to the scan mode is provided .
The relative ratio between the clock domains of the divider ratio in the normal operation mode and in the scan capture mode is the same, and the division ratio in the scan capture mode than in the normal operation mode A scan clock distribution system characterized by having a small size . 2. The scan clock distribution system according to claim 1, further comprising the frequency divider having the same delay time before and after switching the frequency division ratio. 3. The scan clock distribution system according to claim 1, wherein a frequency division ratio of the frequency divider is made equal between clock domains in a scan shift mode. A semiconductor integrated circuit device comprising a scan clock distribution system for supplying a scan clock signal to a root node of a clock signal to be supplied to a multi-clock domain in a normal operation mode,
A frequency divider that switches the frequency division ratio for dividing the scan clock signal supplied to the clock domain according to the scan mode is provided .
The relative ratio between the clock domains of the divider ratio in the normal operation mode and in the scan capture mode is the same, and the division ratio in the scan capture mode than in the normal operation mode A semiconductor integrated circuit device characterized by having a small size .

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