JP5005719B2 - Intermittent mixer circuit - Google Patents

Intermittent mixer circuit Download PDF

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JP5005719B2
JP5005719B2 JP2009066313A JP2009066313A JP5005719B2 JP 5005719 B2 JP5005719 B2 JP 5005719B2 JP 2009066313 A JP2009066313 A JP 2009066313A JP 2009066313 A JP2009066313 A JP 2009066313A JP 5005719 B2 JP5005719 B2 JP 5005719B2
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switch
signal
mixing unit
mixer circuit
intermittent
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JP2010220034A (en
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守 宇賀神
光男 中村
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Nippon Telegraph and Telephone Corp
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本発明は、無線受信機フロントエンド回路においてダウンコンバージョンミキサ回路として用いられ、間欠動作によって消費電力を低減する間欠ミキサ回路に関する。   The present invention relates to an intermittent mixer circuit that is used as a down-conversion mixer circuit in a radio receiver front-end circuit and reduces power consumption by intermittent operation.

ユビキタス情報社会の実現に向けて、センサを備えた多数の情報発信端末によるセンサネットワークの研究開発が進んでいる。これらの情報発信端末は極めて低電力で動作し、また他の無線通信システムと比較して利用する無線チャネル帯域が数ｋHz程度と小さいことが特徴である。このような狭帯域無線通信装置では、受信チャネル選択フィルタ回路を低電力で実現するために、受信機内の中間周波数（ＩＦ）を低く（10ｋHz程度）する必要がある。その場合の課題の１つにダウンコンバージョンミキサ回路における１／ｆノイズがある。１／ｆノイズは、そのノイズ強度が周波数に反比例する。このため10ｋHz程度の低い中間周波数ではダウンコンバージョンミキサ回路からの１／ｆノイズが大きくなり、受信感度を大幅に劣化させる可能性がある。   To realize a ubiquitous information society, research and development of sensor networks using a large number of information transmission terminals equipped with sensors is progressing. These information transmission terminals operate with extremely low power, and are characterized by a small radio channel bandwidth of about several kHz compared to other radio communication systems. In such a narrow band wireless communication device, in order to realize the reception channel selection filter circuit with low power, it is necessary to lower the intermediate frequency (IF) in the receiver (about 10 kHz). One of the problems in that case is 1 / f noise in the down-conversion mixer circuit. The noise intensity of 1 / f noise is inversely proportional to the frequency. For this reason, at an intermediate frequency as low as about 10 kHz, 1 / f noise from the down-conversion mixer circuit becomes large, and there is a possibility that the reception sensitivity is greatly deteriorated.

ダウンコンバージョンミキサ回路の１／ｆノイズ低減手法の１つに、図８に示すパッシブ型ミキサ回路がある（非特許文献１）。このパッシブ型ミキサ回路は、バイアス電位間に接続されるトランジスタペア（Ｑ４とＱ５，Ｑ６とＱ７）にＬＯ信号とＲＦ信号を入力してＩＦ信号を出力する構成であり、スイッチングを行うトランジスタペアに直流電流が流れないため、１／ｆノイズが発生しない。   One of the 1 / f noise reduction techniques of the down-conversion mixer circuit is a passive mixer circuit shown in FIG. 8 (Non-Patent Document 1). This passive mixer circuit is configured to input an LO signal and an RF signal to a transistor pair (Q4 and Q5, Q6 and Q7) connected between bias potentials and output an IF signal. Since no direct current flows, 1 / f noise does not occur.

図９は、従来のダブルバランスミキサ（ギルバートセルミキサ）の構成例を示す（非特許文献２）。このダブルバランスミキサは、２つの電源電位間に、ＲＦ信号を入力して電流信号に変換するＭＯＳトランジスタＱ１，Ｑ２および定電流源トランジスタＱ３からなる電流／電圧変換部１１と、ＬＯ信号を入力するＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７からなるミキシング部１２および負荷抵抗を接続し、ＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７のドレイン端子からＩＦ信号出力を取り出す構成である。   FIG. 9 shows a configuration example of a conventional double balance mixer (Gilbert cell mixer) (Non-Patent Document 2). This double balance mixer inputs a LO signal between a current / voltage conversion unit 11 composed of MOS transistors Q1, Q2 and a constant current source transistor Q3 which input an RF signal and converts it into a current signal between two power supply potentials. The mixing section 12 composed of MOS transistors Q4, Q5, Q6, and Q7 and a load resistor are connected to take out an IF signal output from the drain terminals of the MOS transistors Q4, Q5, Q6, and Q7.

The Design of CMOS Radio-Frequency Integrated Circuits (ISBN 0-521-63061-4), T. H. Lee, Cambridge University Press, (1998) pp.331-335The Design of CMOS Radio-Frequency Integrated Circuits (ISBN 0-521-63061-4), T. H. Lee, Cambridge University Press, (1998) pp.331-335 The Design of CMOS Radio-Frequency Integrated Circuits (ISBN 0-521-63061-4), T. H. Lee, Cambridge University Press, (1998) pp.322-329The Design of CMOS Radio-Frequency Integrated Circuits (ISBN 0-521-63061-4), T. H. Lee, Cambridge University Press, (1998) pp.322-329

図８に示すパッシブ型ミキサ回路は、トランジスタがアクティブ動作しないため、信号は増幅されず減衰する。このため、次段回路のノイズに強く影響され、ＮＦ特性が劣化する問題があった。   In the passive mixer circuit shown in FIG. 8, since the transistor does not perform an active operation, the signal is attenuated without being amplified. For this reason, there is a problem that the NF characteristic is deteriorated by being strongly influenced by the noise of the next stage circuit.

図９に示すダブルバランスミキサ（ギルバートセルミキサ）などのアクティブミキサ回路は、ＭＯＳトランジスタに直流電流が常時流れており、１／ｆノイズの発生が避けられない。   In an active mixer circuit such as a double balance mixer (Gilbert cell mixer) shown in FIG. 9, a direct current always flows through a MOS transistor, and the occurrence of 1 / f noise is inevitable.

本発明は、アクティブミキサ回路を間欠動作させることで信号増幅と１／ｆノイズの抑止を同時に可能とし、かつ間欠動作によるスプリアス信号の発生を大幅に低減する間欠ミキサ回路を提供することを目的とする。   It is an object of the present invention to provide an intermittent mixer circuit that enables signal amplification and 1 / f noise suppression simultaneously by intermittently operating an active mixer circuit, and that significantly reduces the generation of spurious signals due to intermittent operation. To do.

本発明の間欠ミキサ回路は、電源電位１と電源電位２との間に、ＲＦ信号を入力して電流信号に変換する電圧／電流変換部と、ＬＯ信号を入力するミキシング部とを縦積接続し、ミキシング部からＲＦ信号とＬＯ信号の周波数差に対応するＩＦ信号を出力するミキサ回路において、ミキシング部のＩＦ信号出力端子に負荷容量を接続し、電源電位１から電圧／電流変換部、ミキシング部を介して負荷容量までの間に、ミキシング部に流れる直流電流をオンオフするスイッチＳ１を接続し、ミキシング部のＩＦ信号出力端子と負荷容量の接続点にスイッチＳ２を介して電源電位２を接続し、ミキシング部のＩＦ信号出力端子と負荷容量の接続点にスイッチＳ３を介してサンプリング容量を接続し、スイッチＳ１をサンプリング周期１／fsでオンオフするとともに、スイッチＳ２をスイッチＳ１と逆相でオンオフし、スイッチＳ１がオンになってからオフになる直前に負荷容量の端子電位をサンプリング容量に保持させるようにスイッチＳ３をオンオフするスイッチ制御手段を備え、サンプリング容量の端子電位をＩＦ信号として出力する構成である。   In the intermittent mixer circuit of the present invention, a voltage / current conversion unit that inputs an RF signal and converts it into a current signal and a mixing unit that inputs an LO signal are connected in cascade between the power supply potential 1 and the power supply potential 2. In the mixer circuit that outputs the IF signal corresponding to the frequency difference between the RF signal and the LO signal from the mixing unit, a load capacitor is connected to the IF signal output terminal of the mixing unit, and the voltage / current conversion unit from the power source potential 1 is mixed. The switch S1 for turning on and off the direct current flowing through the mixing unit is connected to the load capacity via the unit, and the power supply potential 2 is connected to the connection point between the IF signal output terminal of the mixing unit and the load capacity via the switch S2. The sampling capacitor is connected to the connection point between the IF signal output terminal of the mixing unit and the load capacitor via the switch S3, and the switch S1 is turned on at the sampling period 1 / fs. Switch control means for turning on / off the switch S2 so that the terminal potential of the load capacitor is held in the sampling capacitor immediately before turning off after the switch S1 is turned on. The terminal potential of the sampling capacitor is output as an IF signal.

本発明の間欠ミキサ回路において、スイッチＳ１のオン時間ton がＬＯ信号の周期の２倍よりも長く、サンプリング周期１／fsがＲＦ信号周波数帯域の逆数で定義される時間の１／２よりも短いことを特徴とする。   In the intermittent mixer circuit of the present invention, the ON time ton of the switch S1 is longer than twice the period of the LO signal, and the sampling period 1 / fs is shorter than 1/2 of the time defined by the reciprocal of the RF signal frequency band. It is characterized by that.

本発明の間欠ミキサ回路において、スイッチＳ１は、電圧／電流変換部の電源端子と電源電位１との間、または電圧／電流変換部とミキシング部との間、またはミキシング部のＩＦ信号出力端子と負荷容量の接続点との間に接続し、ミキシング部に流れる直流電流をオンオフする構成である。   In the intermittent mixer circuit of the present invention, the switch S1 is provided between the power supply terminal of the voltage / current conversion unit and the power supply potential 1, or between the voltage / current conversion unit and the mixing unit, or the IF signal output terminal of the mixing unit. It is connected to the connection point of the load capacity, and the DC current flowing through the mixing unit is turned on / off.

本発明の間欠ミキサ回路において、スイッチＳ１は、電圧／電流変換部の定電流源またはＲＦ信号入力部のバイアス電位を切り替え、ミキシング部に流れる直流電流をオンオフする構成である。   In the intermittent mixer circuit of the present invention, the switch S1 is configured to switch the bias potential of the constant current source of the voltage / current conversion unit or the RF signal input unit to turn on and off the direct current flowing through the mixing unit.

本発明の間欠ミキサ回路において、スイッチＳ１は、ミキシング部のＬＯ信号入力部のバイアス電位を切り替え、ミキシング部に流れる直流電流をオンオフする構成である。   In the intermittent mixer circuit of the present invention, the switch S1 is configured to switch the bias potential of the LO signal input section of the mixing section and turn on / off the direct current flowing through the mixing section.

本発明の間欠ミキサ回路は、負荷容量が接続されたミキサ回路を間欠動作させ、ＩＦ信号をサンプリング周波数fsでサンプリングすることによりミキサ回路の消費電力を低減するとともに、ミキシング部のオン時間ton に対応する周波数１／ton より低周波数の１／ｆノイズを抑圧することができる。   The intermittent mixer circuit of the present invention reduces the power consumption of the mixer circuit by intermittently operating the mixer circuit to which the load capacitor is connected and sampling the IF signal at the sampling frequency fs, and supports the on time ton of the mixing unit. 1 / f noise having a frequency lower than the frequency 1 / ton can be suppressed.

本発明の間欠ミキサ回路の実施例構成を示す図である。It is a figure which shows the Example structure of the intermittent mixer circuit of this invention. スイッチＳ１，Ｓ２，Ｓ３を制御するスイッチ制御信号の一例を示す図である。It is a figure which shows an example of the switch control signal which controls switch S1, S2, S3. 本発明の間欠ミキサ回路の第１の回路構成例を示す図である。It is a figure which shows the 1st circuit structural example of the intermittent mixer circuit of this invention. 本発明の間欠ミキサ回路の第２の回路構成例を示す図である。It is a figure which shows the 2nd circuit structural example of the intermittent mixer circuit of this invention. 本発明の間欠ミキサ回路の第３の回路構成例を示す図である。It is a figure which shows the 3rd circuit structural example of the intermittent mixer circuit of this invention. 本発明の間欠ミキサ回路の第４の回路構成例を示す図である。It is a figure which shows the 4th circuit structural example of the intermittent mixer circuit of this invention. 高精度回路シミュレータによるＩＦ信号の例を示す図である。It is a figure which shows the example of IF signal by a high precision circuit simulator. パッシブ型ミキサ回路の構成例を示す図である。It is a figure which shows the structural example of a passive type mixer circuit. 従来のダブルバランスミキサ（ギルバートセルミキサ）の構成例を示す図である。It is a figure which shows the structural example of the conventional double balance mixer (Gilbert cell mixer).

図１は、本発明の間欠ミキサ回路の実施例構成を示す。
図において、ＲＦ信号（周波数：ｆRF）を入力して電流信号に変換する電圧／電流変換部１１と、ＬＯ信号（周波数：ｆLO）を入力するミキシング部１２は、図９に示す従来のダブルバランスミキサ（ギルバートセルミキサ）と同様に、２つの電源電位１と電源電位２との間に縦積み接続される。ここで、本実施例の間欠ミキサ回路は、電圧／電流変換部１１と電源電位１との間にスイッチＳ１を挿入し、ミキシング部１２と電源電位２との間にスイッチＳ２を挿入し、ミキシング部１２の出力に負荷容量１３を接続するとともに、スイッチＳ３を介してサンプリング容量１４を接続し、サンプリング容量１４の端子電位をＩＦ信号出力（周波数：ｆIF）とする構成である。スイッチＳ１，Ｓ２，Ｓ３は、スイッチ制御部１５によりサンプリング周波数fsのスイッチ制御信号でオンオフ制御される。 FIG. 1 shows an embodiment of the intermittent mixer circuit according to the present invention.
In FIG. 9, a voltage / current conversion unit 11 that inputs an RF signal (frequency: f RF ) and converts it into a current signal, and a mixing unit 12 that inputs an LO signal (frequency: f LO ) are shown in FIG. Similar to a double balance mixer (Gilbert cell mixer), two power supply potentials 1 and 2 are connected in cascade. Here, in the intermittent mixer circuit of this embodiment, the switch S1 is inserted between the voltage / current conversion unit 11 and the power supply potential 1, and the switch S2 is inserted between the mixing unit 12 and the power supply potential 2, thereby mixing. The load capacitor 13 is connected to the output of the unit 12, and the sampling capacitor 14 is connected via the switch S3, and the terminal potential of the sampling capacitor 14 is used as an IF signal output (frequency: f IF ). The switches S1, S2, and S3 are ON / OFF controlled by the switch control unit 15 with a switch control signal having a sampling frequency fs.

図２は、スイッチＳ１，Ｓ２，Ｓ３を制御するスイッチ制御信号の一例を示す。
スイッチＳ１とスイッチＳ２は、逆相のスイッチ制御信号によりオンオフする。すなわち、スイッチＳ１のオン時間（ton ）はスイッチＳ２がオフになり、スイッチＳ１のオフ期間（１／fs−ton ）はスイッチＳ２がオンになる。ここで、スイッチＳ１がオン、スイッチＳ２がオフの間に、ミキシング部１２から出力されるＩＦ信号の電荷が負荷容量１３に蓄積される。また、ミキシング部１２の出力端Ａの電位（負荷容量１３の端子電位）は、スイッチＳ２がオフの間はＩＦ信号が積分され、スイッチＳ２がオンになると電源電位２と等しくなりリセットされる。スイッチＳ３は、スイッチＳ２がオンになる直前の出力端Ａの電位をサンプリング容量１４に保持するようにオンになり、ＩＦ信号出力とする。 FIG. 2 shows an example of a switch control signal for controlling the switches S1, S2, and S3.
The switches S1 and S2 are turned on and off by a reverse phase switch control signal. That is, the switch S2 is turned off during the on time (ton) of the switch S1, and the switch S2 is turned on during the off period (1 / fs-ton) of the switch S1. Here, the charge of the IF signal output from the mixing unit 12 is accumulated in the load capacitor 13 while the switch S1 is on and the switch S2 is off. Further, the potential of the output terminal A of the mixing unit 12 (the terminal potential of the load capacitor 13) is integrated while the IF signal is integrated while the switch S2 is off, and is equal to the power supply potential 2 and reset when the switch S2 is on. The switch S3 is turned on so that the potential of the output terminal A immediately before the switch S2 is turned on is held in the sampling capacitor 14, and is output as an IF signal.

このようなスイッチ操作により、ミキシング部１２に流れる直流電流はスイッチＳ１のオフ期間で遮断され、オン時間ton に対応する周波数１／ton より低周波数の１／ｆノイズは発生しない。   By such switch operation, the direct current flowing through the mixing unit 12 is cut off during the OFF period of the switch S1, and 1 / f noise having a frequency lower than the frequency 1 / ton corresponding to the ON time ton is not generated.

ここで、スイッチＳ１は、ＲＦ信号を電流信号に変換する電圧／電流変換部１１と電源電位１との間の電流切断を行うが、その目的はミキシング部１２に流れる直流電流を周期的に切断することである。このため、スイッチＳ１の設置位置は、電圧／電流変換部１１と電源電位１との間に限らず、電圧／電流変換部１１とミキシング部１２の間、ミキシング部１２の出力端Ａ、電圧／電流変換部１１の内部、ミキシング部１２の内部のいずれにあってもよい。   Here, the switch S1 performs current disconnection between the voltage / current conversion unit 11 that converts the RF signal into a current signal and the power supply potential 1, and its purpose is to periodically disconnect the direct current flowing through the mixing unit 12. It is to be. For this reason, the installation position of the switch S1 is not limited to between the voltage / current conversion unit 11 and the power supply potential 1, but between the voltage / current conversion unit 11 and the mixing unit 12, the output terminal A of the mixing unit 12, and the voltage / current It may be either inside the current conversion unit 11 or inside the mixing unit 12.

図３は、本発明の間欠ミキサ回路の第１の回路構成例を示す。
ここでは、図９に示す従来のダブルバランスミキサ（ギルバートセルミキサ）を用いた回路構成例を示す。すなわち、電圧／電流変換部１１はＭＯＳトランジスタＱ１，Ｑ２および定電流源のＭＯＳトランジスタＱ３に対応し、ミキシング部１２はＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７に対応する。定電流源トランジスタＱ３と電源電位１（ＶSS）との間にスイッチＳ１を挿入し、ＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７と電源電位２（ＶDD）との間にスイッチＳ２、負荷容量１３、さらにスイッチＳ３を介してサンプリング容量１４を接続し、サンプリング容量１４の端子電位をＩＦ信号出力とする。 FIG. 3 shows a first circuit configuration example of the intermittent mixer circuit of the present invention.
Here, a circuit configuration example using the conventional double balance mixer (Gilbert cell mixer) shown in FIG. 9 is shown. That is, the voltage / current conversion unit 11 corresponds to the MOS transistors Q1, Q2 and the constant current source MOS transistor Q3, and the mixing unit 12 corresponds to the MOS transistors Q4, Q5, Q6, Q7. A switch S1 is inserted between the constant current source transistor Q3 and the power supply potential 1 (VSS), a switch S2, a load capacitor 13 between the MOS transistors Q4, Q5, Q6, Q7 and the power supply potential 2 (VDD), and further The sampling capacitor 14 is connected via the switch S3, and the terminal potential of the sampling capacitor 14 is used as an IF signal output.

なお、スイッチＳ１は、上記のようにミキシング部１２に直流電流が流れる経路上のどこにおいてもよい。   Note that the switch S1 may be located anywhere on the path through which the direct current flows through the mixing unit 12 as described above.

図４に示す第２の回路構成例は、電圧／電流変換部１１の内部にあって定電流源のバイアス切り替えによりＭＯＳトランジスタＱ３をオンオフする構成である。ゲート端子とバイアス端子との間にスイッチＳ１を接続し、ゲート端子とソース端子との間に、スイッチＳ１と反転論理でオンオフする反転スイッチＳ１を接続する。スイッチＳ１をオフ、スイッチＳ１をオンにすることにより、ミキシング部１２に流れる直流電流が切断される。 The second circuit configuration example shown in FIG. 4 is a configuration in which the MOS transistor Q3 is turned on and off by switching the bias of the constant current source inside the voltage / current conversion unit 11. The switch S1 is connected between the gate terminal and the bias terminal, and the switch S1 and the inverting switch S1 that is turned on / off by inverting logic are connected between the gate terminal and the source terminal. When the switch S1 is turned off and the switch S1 is turned on, the direct current flowing through the mixing unit 12 is cut off.

図５に示す第３の回路構成例は、電圧／電流変換部１１の内部にあってＲＦ信号入力部のバイアス切り替えによりＭＯＳトランジスタＱ１，Ｑ２をオンオフする構成である。ＭＯＳトランジスタＱ１，Ｑ２の各ゲート端子に抵抗を接続し、さらにスイッチＳ１を介してＲＦバイアス端子を接続するか、スイッチＳ１と反転論理でオンオフする反転スイッチＳ１を介して電源電位１（ＶSS）を接続する。スイッチＳ１をオフ、スイッチＳ１をオンにすることにより、ミキシング部１２に流れる直流電流が切断される。 The third circuit configuration example shown in FIG. 5 is a configuration in which the MOS transistors Q1 and Q2 are turned on and off by switching the bias of the RF signal input unit inside the voltage / current conversion unit 11. A resistor is connected to each gate terminal of the MOS transistors Q1 and Q2, and further an RF bias terminal is connected via the switch S1 , or a power supply potential 1 (VSS) is supplied via the switch S1 and the inverting switch S1 which is turned on / off by inverting logic. Connecting. When the switch S1 is turned off and the switch S1 is turned on, the direct current flowing through the mixing unit 12 is cut off.

図６に示す第４の回路構成例は、ミキシング変換部１１の内部にあってＬＯ信号入力部のバイアス切り替えによりＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７をオンオフする構成である。ＭＯＳトランジスタＱ４，Ｑ５，Ｑ６，Ｑ７の各ゲート端子に抵抗を接続し、さらにスイッチＳ１を介してＬＯバイアス端子を接続するか、スイッチＳ１と反転論理でオンオフする反転スイッチＳ１を介して電源電位１（ＶSS）を接続する。スイッチＳ１をオフ、スイッチＳ１をオンにすることにより、ミキシング部１２に流れる直流電流が切断される。 The fourth circuit configuration example shown in FIG. 6 is a configuration in which the MOS transistors Q4, Q5, Q6, and Q7 are turned on and off by switching the bias of the LO signal input unit inside the mixing conversion unit 11. A resistor is connected to each gate terminal of the MOS transistors Q4, Q5, Q6, and Q7, and a LO bias terminal is connected via the switch S1 , or a power supply potential 1 is supplied via the inverting switch S1 that is turned on and off with the switch S1 and inverting logic. Connect (VSS). When the switch S1 is turned off and the switch S1 is turned on, the direct current flowing through the mixing unit 12 is cut off.

図７は、高精度回路シミュレータ（ＨＳＰＩＣＥ）による本実施例のＩＦ信号の例を示す。図７(a) は、図３に示す本発明の間欠ミキサ回路の第１の回路構成例におけるＩＦ信号出力を示す。図７(b) は、図９に示す従来の抵抗負荷のダブルバランスミキサ（ギルバートセルミキサ）のＩＦ信号出力を示す。ＬＯ＋およびＬＯ−にｆLO＝ 290ＭHzのＬＯ差動信号を入力し、ＲＦ＋およびＲＦ−にｆRF＝289.99ＭHzのＲＦ差動信号を入力する。ＩＦ＋およびＩＦ−にはｆIF＝10ｋHzのＩＦ差動信号が出力される。図２に示す本発明の間欠ミキサ回路のスイッチＳ１，Ｓ２，Ｓ３を制御するスイッチ制御信号は、fs＝３ＭHz（１／fs＝ 333ｎ秒）、ｔon＝33ｎ秒、ｔon／ａ＝２ｎ秒とする。 FIG. 7 shows an example of the IF signal of this embodiment by a high precision circuit simulator (HSPICE). FIG. 7A shows the IF signal output in the first circuit configuration example of the intermittent mixer circuit of the present invention shown in FIG. FIG. 7B shows the IF signal output of the conventional resistive load double balance mixer (Gilbert cell mixer) shown in FIG. An LO differential signal of f LO = 290 MHz is input to LO + and LO−, and an RF differential signal of f RF = 289.99 MHz is input to RF + and RF−. An IF differential signal of f IF = 10 kHz is output to IF + and IF−. The switch control signals for controlling the switches S1, S2, and S3 of the intermittent mixer circuit of the present invention shown in FIG. 2 are fs = 3 MHz (1 / fs = 333 nsec), ton = 33 nsec, and ton / a = 2n sec. .

本発明の間欠ミキサ回路のＩＦ信号出力には、スイッチＳ１のオン時間ton のＩＦ信号の積分値が１／fsの時間ごとに出現する。また、１／fs周期のノイズが出現しているが、ＩＦ信号よりも周波数が十分に高いため、後段の負荷容量１３のフィルタ回路で除去することができる。   In the IF signal output of the intermittent mixer circuit of the present invention, the integral value of the IF signal during the on time ton of the switch S1 appears every 1 / fs. Further, although noise having a 1 / fs cycle appears, the frequency is sufficiently higher than that of the IF signal, and therefore it can be removed by the filter circuit of the load capacitor 13 at the subsequent stage.

以上示した４種類の周波数ｆRF，ｆLO，ｆIF，fsと、スイッチＳ１のオン時間ton の関係は次の通りである。ＩＦ周波数ｆIFはＲＦ周波数ｆRFに比べて小さく、ｆIF＝｜ｆRF−ｆLO｜、ｆRF≒ｆLOである。また、ton ＜１／fsであり、負荷容量１３に流れ込むＲＦ信号およびＬＯ信号の漏れを平均化して除去するためton ＞２／ｆLOとする。また、ＩＦ信号出力に残っている不要妨害波を後段のフィルタ回路で除去するため、不要妨害波の最大周波数をfuとすると、fs＞２fuである。ここで、fuは無線システム帯域（受信フロントエンド回路のＲＦフィルタ帯域）に等しく、例えばＲＦフィルタ帯域は 100ｋHzであり、fs／２＞（ＲＦフィルタ帯域）である。すなわち、１／fs＜１／２（ＲＦフィルタ帯域）とする。 The relationship between the four types of frequencies f RF , f LO , f IF , fs shown above and the on-time ton of the switch S1 is as follows. The IF frequency f IF is smaller than the RF frequency f RF , and f IF = | f RF −f LO | and f RF ≈f LO . Further, <a 1 / fs, ton for removal by averaging the leakage of RF and LO signals flowing in the load capacitor 13> ton and 2 / f LO. Further, since the unnecessary interference wave remaining in the IF signal output is removed by a subsequent filter circuit, fs> 2fu where fu is the maximum frequency of the unnecessary interference wave. Here, fu is equal to the radio system band (RF filter band of the reception front end circuit), for example, the RF filter band is 100 kHz, and fs / 2> (RF filter band). That is, 1 / fs <1/2 (RF filter band).

本発明の間欠ミキサ回路は、消費電力を低減するとともにミキシング部のオン時間ton に対応する周波数１／ton より低周波数の１／ｆノイズを抑圧することができ、低消費電力でかつ高感度な無線受信機に利用することができる。   The intermittent mixer circuit of the present invention can reduce power consumption and suppress 1 / f noise having a frequency lower than the frequency 1 / ton corresponding to the on-time ton of the mixing unit, and can achieve low power consumption and high sensitivity. It can be used for wireless receivers.

１１ 電圧／電流変換部
１２ ミキシング部
１３ 負荷容量
１４ サンプリング容量
１５ スイッチ制御部
Ｓ１，Ｓ２，Ｓ３ スイッチ 11 Voltage / Current Conversion Unit 12 Mixing Unit 13 Load Capacity 14 Sampling Capacity 15 Switch Control Unit S1, S2, S3 Switch

Claims (5)

電源電位１と電源電位２との間に、ＲＦ信号を入力して電流信号に変換する電圧／電流変換部と、ＬＯ信号を入力するミキシング部とを縦積接続し、ミキシング部からＲＦ信号とＬＯ信号の周波数差に対応するＩＦ信号を出力するミキサ回路において、
前記ミキシング部のＩＦ信号出力端子に負荷容量を接続し、
前記電源電位１から前記電圧／電流変換部、前記ミキシング部を介して前記負荷容量までの間に、前記ミキシング部に流れる直流電流をオンオフするスイッチＳ１を接続し、
前記ミキシング部のＩＦ信号出力端子と前記負荷容量の接続点にスイッチＳ２を介して前記電源電位２を接続し、
前記ミキシング部のＩＦ信号出力端子と前記負荷容量の接続点にスイッチＳ３を介してサンプリング容量を接続し、
前記スイッチＳ１を１／fsの周期でオンオフするとともに、前記スイッチＳ２を前記スイッチＳ１と逆相でオンオフし、前記スイッチＳ１がオンになってからオフになる直前に前記負荷容量の端子電位を前記サンプリング容量に保持させるように前記スイッチＳ３をオンオフするスイッチ制御手段を備え、
前記サンプリング容量の端子電位を前記ＩＦ信号として出力する構成である
ことを特徴とする間欠ミキサ回路。 Between the power supply potential 1 and the power supply potential 2, a voltage / current conversion unit that inputs an RF signal and converts it into a current signal and a mixing unit that inputs an LO signal are connected in cascade, and the RF signal is transmitted from the mixing unit to the RF signal. In the mixer circuit that outputs the IF signal corresponding to the frequency difference of the LO signal,
Connect a load capacitor to the IF signal output terminal of the mixing unit,
A switch S1 for turning on and off a direct current flowing through the mixing unit is connected between the power supply potential 1 and the load capacity via the voltage / current conversion unit and the mixing unit.
The power supply potential 2 is connected to a connection point between the IF signal output terminal of the mixing unit and the load capacitor via a switch S2,
A sampling capacitor is connected via a switch S3 to a connection point between the IF signal output terminal of the mixing unit and the load capacitor,
The switch S1 is turned on / off at a period of 1 / fs, the switch S2 is turned on / off in a phase opposite to that of the switch S1, and the terminal potential of the load capacitor is set to be just before turning off after the switch S1 is turned on. A switch control means for turning on and off the switch S3 so as to hold the sampling capacity;
An intermittent mixer circuit characterized in that the terminal potential of the sampling capacitor is output as the IF signal. 請求項１に記載の間欠ミキサ回路において、
前記スイッチＳ１のオン時間ton が前記ＬＯ信号の周期の２倍よりも長く、前記１／fsが前記ＲＦ信号周波数帯域の逆数で定義される時間の１／２よりも短い
ことを特徴とする間欠ミキサ回路。 The intermittent mixer circuit according to claim 1,
The on-time ton of the switch S1 is longer than twice the period of the LO signal, and the 1 / fs is shorter than 1/2 of the time defined by the reciprocal of the RF signal frequency band. Mixer circuit. 請求項１に記載の間欠ミキサ回路において、
前記スイッチＳ１は、前記電圧／電流変換部の電源端子と前記電源電位１との間、または前記電圧／電流変換部と前記ミキシング部との間、または前記ミキシング部のＩＦ信号出力端子と前記負荷容量の接続点との間に接続し、前記ミキシング部に流れる直流電流をオンオフする構成である
ことを特徴とする間欠ミキサ回路。 The intermittent mixer circuit according to claim 1,
The switch S1 is connected between the power supply terminal of the voltage / current conversion unit and the power supply potential 1, or between the voltage / current conversion unit and the mixing unit, or between the IF signal output terminal of the mixing unit and the load. An intermittent mixer circuit that is connected to a connection point of a capacitor to turn on and off a direct current flowing through the mixing unit. 請求項１に記載の間欠ミキサ回路において、
前記スイッチＳ１は、前記電圧／電流変換部の定電流源またはＲＦ信号入力部のバイアス電位を切り替え、前記ミキシング部に流れる直流電流をオンオフする構成である
ことを特徴とする間欠ミキサ回路。 The intermittent mixer circuit according to claim 1,
The intermittent switch circuit is characterized in that the switch S1 is configured to switch a bias potential of a constant current source or an RF signal input unit of the voltage / current conversion unit, and to turn on / off a direct current flowing through the mixing unit. 請求項１に記載の間欠ミキサ回路において、
前記スイッチＳ１は、前記ミキシング部のＬＯ信号入力部のバイアス電位を切り替え、前記ミキシング部に流れる直流電流をオンオフする構成である
ことを特徴とする間欠ミキサ回路。 The intermittent mixer circuit according to claim 1,
The intermittent switch circuit is characterized in that the switch S1 is configured to switch a bias potential of an LO signal input unit of the mixing unit and to turn on / off a direct current flowing through the mixing unit.
JP2009066313A 2009-03-18 2009-03-18 Intermittent mixer circuit Expired - Fee Related JP5005719B2 (en)

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