JP5000265B2 - Clock generation circuit - Google Patents

Description

  The present invention relates to a clock generation circuit and a method for generating a clock signal, and more particularly to a duty cycle correction circuit, a clock generation circuit, and a clock signal generation method.

  A semiconductor device including a clock generation circuit includes a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit. A conventional PLL has a voltage controlled oscillator (VCO) that generates a relatively high frequency clock signal, a duty cycle correction unit (DCC) including at least one pair of amplification units and a charge pump pair corresponding thereto. : Duty cycle Correction Circuit). On the other hand, a conventional DLL includes a voltage controlled delay line (VCDL), and a duty cycle correction unit including at least a pair of amplification units and a charge pump pair corresponding thereto.

  Referring to FIG. 1, the conventional PLL 100 includes a phase detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140, a duty cycle correction unit 150, and a frequency divider 160.

  The phase detector 110 generates a control signal in response to the phase difference between the external clock signal INS and the feedback clock signal FEEDS, and transmits the generated control signal to the charge pump 120. The control signal includes a logic high signal and a logic low signal (not shown). When the phase of the external clock signal INS precedes the feedback clock signal FEEDS, the phase detector 110 is activated and generates an activated logic high signal. On the other hand, when the phase of the feedback clock signal FEEDS precedes the external clock signal INS, the phase detector 110 generates an activated logic low signal. The charge pump 120 and the loop filter 130 increase the level of the control signal VC in response to the activated logic high signal, and decrease the level of the control voltage VD in response to the activated logic low signal. The control signal VC is input to the voltage controlled oscillator 140.

  The voltage controlled oscillator 140 generates clock signals CLK and CLKB transmitted to the duty cycle correction unit 150. The phase difference between the clock signals CLK and CLKB is about 180 °. The duty cycle correction unit removes a duty cycle error present in each of the clock signals CLK and CLKB, and generates corrected clock signals CCLKB and CCLK that maintain a normal duty cycle (50%: 50%). The phase difference between the correction clock signals CCLK and CCLKB is about 180 °.

  The frequency divider 160 receives one of the correction clock signals CCLK and CCLKB (illustrated as being input with the CCLK signal in FIG. 1) and has the same frequency as the external clock signal INS. The circulated feedback clock signal FEEDS is output. In order to obtain correction clock signals CCLK and CCLKB having a higher frequency than the external clock signal INS, the frequency divider 160 is provided in the PLL 100. On the other hand, if the PLL 100 does not include the frequency divider 160, the frequencies of the correction clock signals CCLK and CCLKB have the same value as the frequency of the external clock signal INS.

  Referring to FIG. 2, the conventional DLL 200 includes a voltage controlled delay line 240 instead of the voltage controlled oscillator 140 of the PLL of FIG. 1. A phase detector 210, a charge pump 220, a loop filter 230, and a duty cycle correction unit 250 are provided.

  The delay line 240 receives clock signals CLK and CLKB obtained by delaying the external clock signal INS for a predetermined time in response to outputs of the charge pump 220 and the loop filter 230 (the loop filter is generally composed of a low pass filter). generate. Then, the duty cycle correction unit 250 removes a duty cycle error present in each of the clock signals CLK and CLKB, and generates corrected clock signals CCLK and CCLKB having a normal duty cycle.

  Referring to FIG. 3, the conventional duty cycle correction units 150 and 250 will be described in more detail. The duty cycle correction units 150 and 250 receive different differential clock signals CLK, CLKB or single-ended signals having a phase difference of about 180 °. This will be described in more detail with reference to FIGS. In the case of different clock signals, the duty cycle errors of the clock signals CLK and CLKB are corrected in response to the control signals VC and VCB generated from the charge pump 320 of the duty cycle correction unit. The charge pump 320 adjusts the voltage values of the control signals VC and VCB generated in response to the correction clock signals CCLK and CCLKB. The amplifying unit 310 maintains the correction clock signals CCLK and CCLKB at a normal duty cycle (50%: 50%), and the duty of the clock signals CLK and CLKB input according to the voltage values of the control signal VC and the inverted control signal VCB. Adjust the cycle.

  Referring to FIG. 12A, if the intermediate clock signals CLK and CLKB have no duty cycle error, the correction clock signals CCLK and CCLKB also have no duty cycle error. Therefore, the average voltage level of the control signal VC is kept constant in the mode clock cycle.

  Referring to FIG. 13A, if the clock signals CLK, CLKB have a duty cycle error, the corrected clock signals CCLK, CCLKB also have a duty cycle error. Accordingly, the charge pump 320 of the duty cycle correction units 150 and 250 operates to adjust the voltage level of the control signal VC in order to control the amplification unit 310 to correct the duty cycle error of the clock signals CLK and CLKB. To do. As shown in the figure, the average voltage value of the control voltage in one clock period varies from one section to another until the corrected clock signals CCLK and CCLKB are corrected to have a normal duty cycle by the operation of the duty cycle correction unit.

  Referring to FIG. 4, the voltage controlled oscillator 410 outputs two pairs of clock signals CLK1 / CLKB1 and CLK2 / CLKB2. In this case, as shown in block 420a and block 420b, the duty cycle correction unit 400 has a one-to-one correspondence with the two amplification units 425a and 425b in order to correct the duty cycle error of two different pairs of clock signals. Two charge pumps 430a and 430b.

  Referring to FIG. 5, the voltage controlled oscillator 510 outputs four single-ended signals CLK1, CLK2, CLK3, and CLK4. In this case, as shown in blocks 520a, 520b, 520c, and 520d, the duty cycle correction unit 500 has four amplifying units corresponding one to one in order to correct the duty cycle error of each of the four single-ended signals. Four charge pumps 530a, 530b, 530c, and 530d disposed in 525a, 525b, 525c, and 525d, respectively, are provided. The duty cycle error of the clock signals CLK1, CLK2, CLK3, CLK4 is generated from the charge pumps 530a, 530b, 530c, 530d that adjust the voltage value of the control signal in response to the correction signals CCLK1, CCLK2, CCLK3, CCLK4. Correction is performed in response to the signals VC1, VC2, VC3, and VC4. Therefore, the amplifiers 525a, 525b, 525c, and 525d adjust the duty cycle of the CLK1, CLK2, CLK3, and CLK4 signals according to the respective VC1, VC2, VC3, and VC4.

  As FIG. 4 illustrates, while FIG. 5 illustrates the voltage controlled oscillator 510 and the duty cycle correction unit 500 in a PLL, those skilled in the art will be able to implement a DLL that uses a voltage controlled delay line instead of a voltage controlled oscillator. A similar arrangement between the voltage controlled delay line and the duty cycle corrector will be understood.

  As described above with respect to the conventional clock generation circuit, the charge pump for duty cycle correction is aligned in association with the amplifying unit to which the clock signal is transmitted to generate the correction clock signal. The requirement for a plurality of charge pumps for duty cycle correction of a conventional semiconductor device has the problem that high power consumption and a large chip area are required.

  It is an object of the present invention to provide an improved clock generation circuit that is more compact and has reduced power consumption.

  One aspect of the present invention provides at least one or more advantages in the following description with respect to the above problems or disadvantages. Therefore, the present invention has advantages in low power consumption and reduction in chip size in a semiconductor device using a clock generator.

  The present invention provides a clock generator comprising a plurality of amplifiers for generating a correction clock signal and a shared charge pump for adjusting the voltage level of the control signal VC and providing the control signal VC in response to the correction control signal. A circuit and a method for generating a clock signal are provided.

  According to an embodiment of the present invention, the duty cycle correction unit can be used in a clock generation circuit. A duty cycle correction circuit according to an embodiment of the present invention transmits a pair of first differential clock signals, a first amplifier that outputs a pair of first correction clock signals, and a pair of second differential clock signals. A second amplifying unit for outputting a pair of second correction clock signals; a second amplifier for transmitting the first and second correction clock signal pairs; and a second control signal for outputting a second control signal based on the first and second correction clock signal pairs. A charge pump is provided. The first and second amplifying units adjust the duty cycles of the first and second differential clock signal pairs different from each other.

  According to another embodiment of the present invention, a method for generating a clock signal includes generating a first and a second differential clock signal pair different from each other, and generating a first correction clock signal pair in a first amplifying unit. A step of inputting one differential clock signal pair; a step of inputting a second differential clock signal pair to a second amplifying unit to generate a second pair of corrected clock signals; and a reference of the first and second correction signal pairs In order to generate the second voltage control signal, the second and second correction clock signal pairs are input to the second charge pump, and the duty cycles of the first and second differential clock signal pairs different from each other are adjusted. Therefore, the method includes a step of inputting a second voltage control signal to at least one of the first and second amplification units.

  The clock generation circuit according to the present invention can correct the duty cycle error between generated clock signals while reducing the power consumption and the circuit area.

  For a full understanding of the present invention and its operational advantages and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating the preferred embodiments of the invention and the contents described in the drawings. I must. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals attached to the drawings indicate the same members.

  Referring to FIG. 6, the semiconductor device according to an embodiment of the present invention includes a clock generation unit 610 and a duty cycle correction unit 620. In the semiconductor device 600 employing the PLL, the clock generator 610 is driven by a voltage controlled oscillator. In a semiconductor device employing a DLL according to another embodiment, the clock generator 610 is driven by a voltage controlled delay line.

  As shown in FIG. 6, the duty cycle correction unit 620 according to an embodiment of the present invention uses a shared charge pump 630 to correct the duty cycle errors of the respective differential clock signals CLK1 / CLKB1, CLK2 / CLKB2. (Instead of the independent charge pump of the conventional duty cycle correction unit shown in FIG. 4). Therefore, it is possible to reduce not only the chip area but also the power consumption caused by the charge pump of the duty cycle correction unit as compared with the prior art. The charge pump shared by the duty cycle correction unit controls the voltage values of the control signal VC and the inverted control voltage VCB in response to the average value of the duty cycle of the CCLK1 / CCLKB1 and CCLK2 / CCLKB2 signals. The values of the control voltage and the inverted control voltage VC / VCB output to the amplifying unit 625a by the shared charge pump 630 are different even if they are equal to the values of the control voltage and the inverted control voltage VC / VCB output to the amplifying unit 625b. Value may be used.

  Referring to FIG. 7, in one embodiment of the present invention, the shared charge pump 630 includes an output unit 710, an input driver 720, and a driving current source ISD. The output unit 710 includes a first current source IS1 and a second current source IS2 connected between the power supply voltage VCC and the output node, and a capacitor C connected between the output node NO and the inverted output node NOB. Prepare. Here, the capacitor C acts as a low-pass filter. The input driver 720 is connected in parallel between the output node NO and the control node NC, and includes a plurality of input transistors ITR1 and ITR2 that receive the correction clock signals CCLK1 and CCLK2, respectively, and an inverting output node NOB and the control node NC. And a plurality of inverting input transistors ITRB1 and ITRB2 that are connected in parallel and receive the inverted signals CCLKB1 and CCLKB2 of the correction clock signal, respectively. Drive current source ISD is connected between control node NC and ground voltage VSS.

  Referring to FIG. 9, in the semiconductor device according to another embodiment of the present invention, the shared charge pump 930 includes an output unit 910 and an input driver 920. The input driver 920 in FIG. 9 different from the charge pump shown in FIG. 7 includes two drive current sources ISD1 and ISD2. The first driving current source ISD1 is connected between the first control node NC1 and the ground voltage VSS, and the second driving current source ISD2 is connected between the second control node NC2 and the ground voltage VSS.

  Referring to FIG. 8, in the semiconductor device according to the embodiment of the present invention, the amplifying unit 625a (or the amplifying unit 625b) includes a load unit 810 and a control unit 820. Here, the clock signal and the inverted clock signal CLK1 / CLKB1 are applied to the gate terminals of the second amplification transistor and the first amplification transistor ATR2, ATR1, respectively. The second amplification transistor and the first amplification transistors ATR2 and ATR1 are connected to the node NCA1. On the other hand, the control voltage and the inversion control voltages VC and VCB output from the shared charge pump are applied to the gate terminals of the fourth and third amplification transistors ATR4 and ATR3, respectively. The first correction clock signal and the first inverted correction clock signal CCLK1 and CCLKB1 are output from the inverted amplification output node NOAB and the amplification output node NOA, respectively.

  Referring to FIGS. 12B and 13B, a method for generating a control signal according to the above-described embodiment of the present invention will be described.

  Referring to FIG. 12B, when the clock signals CLK1, CLKB1, and CLK2, CLKB2 do not generate a duty cycle error, the correction clock signals CCLK1, CCLKB1, CCLK2, and CCLKB2 also do not generate a duty cycle error.

  In section A of FIG. 12B, the first correction clock signal CCLK1 is associated with the output node NO, and the first correction clock signal CCLKB1 is associated with the inverted output node NOB. Therefore, the voltage drop at the output node NO has the same value as the voltage drop at the inverting output node NOB. Therefore, the level of the control voltage VC is maintained at a constant constant.

  In the B section of FIG. 12B, the two correction clock signals CCLK1 and CCLK2 associated with the output node NO have a logic high level. Therefore, when the first input transistor ITR1 is activated and turned on, an additional voltage drop occurs at the output node NO. On the other hand, since the inverting input transistors ITRB1 and ITRB2 connected to the inverting output node NOB are turned off, the voltage of the inverting output node NOB increases. Therefore, the level of the control signal VC decreases as shown.

  In section C of FIG. 12B, both the second corrected clock signal CCLK2 associated with the output node NO and the inverted second corrected clock signal CCLKB2 associated with the inverted output node NOB have a logic high level. Therefore, the voltage drop at the output node NO is the same as the voltage drop at the inverting output node NOB. Therefore, the control signal VC is kept constant.

  In section D of FIG. 12B, only the inverted correction clock signals CCLKB1 and CCLKB2 associated with the inverted output node NOB have a logic high level. Accordingly, the second inverting input transistor ITRB2 that is additionally activated and turned on causes an additional voltage drop at the inverting output node NOB. On the other hand, since all the input transistors ITR1, ITR2 connected to the output node NO are turned off, the voltage level of the output node NO decreases. Therefore, the control signal VC increases as shown.

  As shown in FIG. 12B, since there is no duty cycle error in the clock signals CLK1, CLK2, the average voltage value of the control signal VC is kept the same during one cycle of the correction clock signals CCLK1, CCLK2, CCLKB1, CCLKB2. As shown in FIG. 12B, the ripple of the control signal VC of the present invention according to one embodiment is also reduced compared to the control signal VC generated from the conventional duty cycle correction unit shown in FIG. 12A.

  As shown in FIG. 13B, when the first and second clock signals CLK1 / CLKB1, CLK2 / CLKB2 have a duty cycle error, the first and second correction clock signals CCLK1 / CCLKB1, CCLK2 / CCLKB2 also have a duty cycle error. .

  In section A of FIG. 13B, both the first correction clock signal CCLK1 associated with the output node NO and the second inversion correction clock signal CCLKB2 associated with the inverted output node NO have a logic high level. Therefore, the voltage drop at the output node NO is the same as the voltage drop at the inverting output node NOB. Therefore, the control voltage VC is kept constant.

  In the B section of FIG. 13B, the first and second correction clock signals CCLK1 and CCLK2 associated with the output node NO have a logic high level. Therefore, since the second input transistor ITR2 is additionally activated and turned on, an additional voltage drop occurs at the output node NO. On the other hand, since all the transistors ITRB1 and ITRB2 connected to the inverted output node NOB are turned off, the voltage of the inverted output node NOB increases. Therefore, the voltage level of the control voltage VC decreases as shown.

  In section C of FIG. 13B, the second corrected clock signal CCLK2 associated with the output node NO and the first inverted clock signal CCLKB1 associated with the inverted output node NOB have a logic high level. Therefore, the voltage drop at the output node NO is the same as the voltage drop at the inverted output node NOB. Therefore, the control voltage VC is kept constant.

  In section C of FIG. 13B, the first and second inverted clock signals CCLKB1 and CCLKB2 associated with the inverted output node NOB have a logic high level. Accordingly, since the second inverting input transistor ITRB2 is additionally activated and turned on, an additional voltage drop occurs at the inverting output node NOB. On the other hand, all the transistors connected to the output node NO are turned off. Therefore, the control voltage VC level increases as shown. In one embodiment of the present invention, the time during which the control voltage VC increases in the D section is long, while the time during which the control voltage VC decreases in the B section is short.

  As shown in FIG. 13B, since there is a duty cycle error in the correction clock signal, the average value of the control voltage VC is not constant during one cycle of the clock signal. That is, as shown in FIG. 13B, the average control voltage level from one clock period to the next increases gradually until the duty cycle error present in the correction clock signal is removed.

  In order to set the correction clock signal to a high level until the high level interval of the correction clock signal becomes longer than the low level interval of the correction clock signal CCLK while correcting the duty cycle error according to an embodiment of the present invention, the control signal VC The voltage level of increases sequentially.

  Referring to FIG. 10, the semiconductor device 1000 according to another embodiment of the present invention includes a clock generator 1010. In the invention of FIG. 10, the shown clock generation unit 1010 may be employed in a PLL. In one example of use, the clock generator 1010 included in the voltage controlled oscillator is used for a PLL. In another use example, the clock generation unit 1010 included in the voltage control delay line is used for a DLL.

  As shown in FIG. 10, the duty correction circuit 1020 according to another embodiment of the present invention is a shared charge pump 1030 for correcting the duty cycle error of each single-ended clock signal CLK1, CLK2, CLK3, CLK4. (Instead of each independent charge pump in the conventional duty cycle correction unit of FIG. 5). Therefore, compared to the conventional arrangement, the charge pump of the duty cycle correction unit according to another embodiment of the present invention can reduce the area of the semiconductor chip and reduce power consumption. The charge pump 1030 shared by the duty cycle correction unit adjusts the value of the control voltage VC in response to the average duty cycle value of the correction clock signals CCLK1, CCLK2, CCLK3, and CCLK4. The control voltage VC is output to the amplification units 1025a, 1035b, 1025c, and 1025d by the shared charge pump 1030.

  Referring to FIG. 11A, the amplifiers 1025a (1025b, 1025c, 1025d) according to the embodiment of the present invention are applied with the intermediate clock signal CLK1 and output the first corrected clock signal CCLK1. Is provided. The transistors SATR1 and SATR4 are applied with the control voltage VC output by the shared charge pump.

  Referring to FIG. 11B, a shared charge pump 1030 according to an embodiment of the present invention includes an output 110 and an input driver including four pairs of transistors PTR1 / NTR1, PTR2 / NTR2, PTR3 / NTR3, and PTR4 / NTR4. Is provided. The four pairs of transistors PTR1 / NTR1, PTR2 / NTR2, PTR3 / NTR3, and PTR4 / NTR4 include a first node N1 to which the first current source IS1 is connected, and a second node N2 to which the second current source IS2 is connected. It is connected between. The transistor pairs PTR1 / NTR1, PTR2 / NTR2, PTR3 / NTR3, and PTR4 / NTR4 are configured to receive correction clock signals CCLK1, CCLK2, CCLK3, and CCLK4, and output a shared output signal at the output node NOS. . The output unit 110 includes an amplifier 1115. The amplifier 1115 receives the reference voltage VREF and a signal output from the input driver through the output node NOS. Then, the control signal VC is output.

  During operation, the duty cycle error of the clock signal CLK1 is adjusted in response to the voltage value of the control voltage VC to output a corrected clock signal CCLK1 that maintains a normal duty cycle (50%: 50%). Is done. For example, if the high level interval of the first clock signal CLK1 is longer than the low level interval of the first clock signal CLK1, the control voltage VC becomes a relatively high level (through the timing diagram of the charge pump 1030 shown in FIG. 11B). You will understand). Therefore, the drive capacity of the transistor SATR4 is much higher than the drive capacity of the transistor SATR1. Therefore, the high level interval of the correction clock signal CCLK1 is shorter than the previous interval, and the low level interval of the correction clock signal CCLK1 is longer than the previous interval.

  Referring to FIG. 14, a PLL according to another embodiment of the present invention is provided. The PLL includes a duty cycle correction unit 1450 including amplification units 1455a (625a in FIG. 6) and 1455b (625b in FIG. 6) and a shared second charge pump 1460 shown in FIGS. In the invention shown in FIG. 14, the PLL 1400 includes a phase detector 1410, a first charge pump 1420, a loop filter 1430, a voltage controlled oscillator 1440, a duty cycle correction unit 1450, and a frequency divider 1470. The voltage controlled oscillator 1440 outputs two pairs of clock signals CLK1 / CLKB1 and CLK2 / CLKB2 that are different from each other to the duty cycle correction unit 1450.

  In another embodiment of the present invention, the voltage controlled oscillator 1450 outputs a plurality of single-ended signals that drive the duty cycle correction unit 1450. In a PLL 1400 according to another embodiment, the external clock signal INS is synchronized to a correction clock signal such as CCLK2.

  Referring to FIG. 15, a DLL 1500 according to another embodiment of the present invention is provided. The DLL 1500 includes a duty cycle correction unit 1550 including amplification units 1555a and 1555b and a shared second charge pump 1560 (630 in FIG. 6) shown in FIGS. 15 includes a phase detector 1510, a first charge pump 1520, a loop filter 1530, a delay line 1540, and a duty cycle correction unit 1550. The voltage control delay line 1540 outputs two pairs of different clock signals CLK1 / CLKB1, CLK2 / CLKB2 to the duty cycle correction unit 1550. The DLL 1500 includes a voltage delay line 1540 that delays the external clock signal INS by a certain time and outputs a plurality of clock signals having a certain constant phase difference (90 ° phase difference).

  In other embodiments of the present invention, the duty cycle correction unit 1550 may be configured to output a plurality of single-ended clock signals, in which case the duty cycle correction unit 1550 may be configured accordingly. Operates (see FIGS. 10, 11A, and 11B). The DLL 1500 according to another embodiment of the present invention synchronizes the external clock signal INS with a correction clock signal such as CCLK2.

  Referring to FIG. 16, a memory device 1600 according to another embodiment of the present invention is provided. The memory device 1600 includes an input / output unit 1610, a memory cell array 1620, an address decoder 1630, a command decoder 1640, and a clock generation unit 1650. The clock generator 1650 constitutes a PLL (shown in FIG. 14) or DLL (shown in FIG. 15) including a duty cycle correction unit having a shared charge pump.

  As described above, the best embodiment has been disclosed in the drawings and the specification. Certain terminology has been used herein for the purpose of describing the invention only and is intended to limit the scope of the invention as defined by the meaning and claims. It was not used for. Accordingly, those skilled in the art will appreciate that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the claims.

  The present invention is suitably used in the technical field related to semiconductor devices.

It is a block diagram which shows the conventional PLL. It is a block diagram which shows the conventional DLL. FIG. 3 is a block diagram illustrating a duty cycle correction unit used in the PLL of FIG. 1 or the DLL of FIG. 2. 6 is a diagram illustrating a conventional internal connection relationship between different clock signals and a duty correction circuit. 6 is a diagram illustrating an internal connection relationship between a conventional duty cycle correction unit and a single-ended signal. 1 is a diagram illustrating a clock generation circuit according to an embodiment of the present invention. It is drawing which shows one Embodiment of the charge pump shown in FIG. It is drawing which shows one Embodiment of the amplification part shown in FIG. It is drawing which shows other embodiment of the charge pump shown in FIG. FIG. 6 is a block diagram illustrating a clock generation circuit according to another embodiment of the present invention. It is drawing which shows the amplification part shown in FIG. It is drawing which shows the electric charge pump shown in FIG. FIG. 6 is a timing diagram illustrating a normal duty cycle of a correction clock signal in a conventional clock generation circuit. FIG. 6 is a timing diagram illustrating a normal duty cycle of a correction clock signal in a clock generation circuit according to an embodiment of the present invention. FIG. 10 is a timing diagram illustrating an abnormal duty cycle of a correction clock signal in a conventional clock generation circuit. FIG. 5 is a timing diagram illustrating an abnormal duty cycle of a correction clock signal in a clock generation circuit according to an embodiment of the present invention. 3 is a diagram illustrating a PLL according to another embodiment of the present invention. 4 is a diagram illustrating a DLL according to another exemplary embodiment of the present invention. 6 is a diagram illustrating a representative execution device of a memory device according to still another embodiment of the present invention.

Explanation of symbols

600 Semiconductor Device 610 Clock Generation Unit 620 Duty Cycle Correction Unit 625a, 625b Amplification Unit 630 Charge Pump 710 Output Unit 720 Input Driver 810 Load Unit 820 Control Unit ATR1, ATR2, ATR3, ATR4 Amplification Transistor
C capacitor CLK1 / CLKB1, CLK2 / CLKB2 differential clock signal CCLK1, CCLK2 correction clock signal CCLKB1, CCLKB2 inverted correction clock signal IS1 first current source IS2 second current source ISD1, ISD2 drive current source ITR1, ITR2 input transistor ITRB1, ITRB2 Inverting input transistor NC control node NCA1 node NO output node NOA amplified output node NOAB inverted amplified output node NOB inverted output node VC control signal VCB inverted control voltage VCC power supply voltage VSS ground voltage

Claims (30)

In the duty cycle correction circuit used in the clock generation circuit,
A first amplifier for receiving a pair of first intermediate differential clock signals and outputting a pair of first internal clock signals;
A second amplifier for receiving a pair of second intermediate differential clock signals and outputting a pair of second internal clock signals;
The pair of first internal clock signals and the pair of second internal clock signals are received, and a second control signal is received based on the received pair of first internal clock signals and the pair of second internal clock signals. A second charge pump for outputting,
The first amplifying unit adjusts a duty cycle of the pair of first intermediate differential clock signals based on the second control signal and outputs the first intermediate clock signal to the pair of first internal clock signals.
The second amplifying unit adjusts a duty cycle of the pair of second intermediate differential clock signals based on the second control signal and outputs the adjusted pair of second internal clock signals to the pair of second internal clock signals. Correction circuit. The duty cycle correction circuit according to claim 1, wherein the correction of the duty cycle of each of the first and second internal clock signal pairs is performed based on a second control signal. The second control signal includes first and second voltage control signals,
The second charge pump is
An output unit including a first output node that outputs the first voltage control signal and a second output node that outputs the second voltage control signal;
An input driver that receives the first and second internal clock signal pairs and outputs the first and second voltage control signals at the first and second output nodes based on the internal clock signal ;
The duty cycle correction circuit according to claim 1, further comprising a capacitive device provided in association with the first and second output nodes. The duty cycle correction circuit according to claim 3, wherein the capacitive device maintains a voltage difference between the first voltage control signal and the second voltage control signal constant. The duty cycle correction circuit according to claim 4, wherein the capacitive device includes a capacitor connected between the first output node and the second output node. The input driver is
A first transistor pair composed of first and second input transistors to which the first internal clock signal and the second internal clock signal are applied, respectively, and which outputs the first voltage control signal at the first output node;
A second transistor pair composed of first and second inverting input transistors to which the first inverted internal clock signal and the second inverted internal clock signal are applied, respectively, and which outputs the second voltage control signal at the second output node; The duty cycle correction circuit according to claim 3, further comprising: The second charge pump is
A first current source coupled to the first output node;
The duty cycle correction circuit according to claim 3, characterized in that it comprises a second current source connected to the second output node. The duty cycle correction circuit according to claim 3, wherein the second charge pump further includes a first drive current source coupled to the input driver. The input driver is
A first transistor pair comprising a first and a second input transistor to which the first internal clock signal and the second internal clock signal are applied, respectively, and which outputs the first voltage control signal at the first output node at one end; ,
The second and second inverted input transistors are applied with the first inverted internal clock signal and the second inverted internal clock signal , respectively, and output the second voltage control signal at the second output node as one end. A transistor pair,
The duty cycle according to claim 8, wherein the first driving current source is connected to a control node which is the other end of the first and second transistor pairs driven by the first driving current source. Cycle correction circuit. The duty cycle correction circuit according to claim 8, wherein the second charge pump further includes a second drive current source coupled to an input driver. The input driver is
A first input transistor that receives the first internal clock signal through a gate terminal;
A second input transistor to which the second internal clock signal is input via a gate terminal;
A first inverting input transistor to which the first inverted internal clock signal is input via a gate terminal;
A second inverting input transistor that receives the second inverted internal clock signal via a gate terminal;
The first and second input transistors output a first voltage control signal at the first output node, which is one end,
The first and second inverting input transistors output a second voltage control signal at the second output node as one end,
The first driving current source is connected to a third node which is the other end of the first input transistor and the first inverting input transistor,
The duty cycle correction circuit according to claim 10, wherein the second drive current source is connected to a fourth node which is the other end of the second input transistor and the second inverting input transistor. The second control signal is:
Comprising first and second voltage control signals;
At least one of the first and second amplification units is:
A first amplification transistor that receives the first inverted intermediate differential clock signal via a gate terminal;
A second amplification transistor that receives the first intermediate differential clock signal through a gate terminal;
A third amplifying transistor that receives the second voltage control signal via a gate terminal;
A fourth amplification transistor that receives the first voltage control signal through a gate terminal;
The first and third amplification transistors output the first internal clock signal at a first output node that is one end,
2. The duty cycle correction circuit according to claim 1, wherein the second and fourth amplification transistors output the first inverted internal clock signal at a second output node that is one end. 3. The amplification unit is
A first drive current source connected to the other ends of the first and second amplification transistors and driving the first and second amplification transistors;
The duty cycle correction according to claim 12, further comprising: a second drive current source connected to the other end of the third and fourth amplification transistors and driving the third and fourth amplification transistors. circuit. A semiconductor circuit comprising the duty cycle correction circuit according to claim 1,
A duty cycle correction circuit, further comprising a clock generator for generating a first and second intermediate differential clock signal pair. In a phase-locked loop comprising the duty cycle correction circuit according to claim 1,
A phase detector that receives an external clock signal and any one of the internal clock signals and outputs a first control signal;
A first charge pump and a loop filter that receive the first control signal and output a control voltage based on the first control signal;
A phase-locked loop comprising: a voltage-controlled oscillator that receives the control voltage and outputs a first and second intermediate differential clock signal pair. In a delay locked loop comprising the duty cycle correction circuit of claim 1,
A phase detector that receives an external clock signal and any one of the internal clock signals and outputs a first control signal;
A first charge pump and a loop filter that receive the first control signal and output a first control voltage based on the first control signal;
A delay line that receives the first control voltage and outputs a first and second intermediate differential clock signal pair. The external clock signal is
The phase-locked loop according to claim 15, wherein the phase-locked loop is a signal synchronized with any one of the first and second internal clock signals . The external clock signal is
The delay locked loop according to claim 16, wherein the delay locked loop is a signal synchronized with any one of the first and second internal clock signals . A memory device comprising the duty cycle correction circuit according to claim 1.
A memory cell array;
An input / output unit for inputting / outputting data signals to / from the memory cell array;
A clock generator comprising the duty cycle correction circuit,
The memory device, wherein the clock generator receives an external clock signal and outputs the first and second internal clock signal pairs to the input / output unit. The memory device includes:
An address decoder connected to the memory cell array and receiving an address signal;
The memory device according to claim 19, further comprising a command decoder connected to the input / output unit and receiving a command signal. In the duty cycle correction circuit used in the clock generation circuit,
A first amplifier for receiving a first intermediate single-ended clock signal and outputting a first internal clock signal;
A second amplifier for receiving a second intermediate single-ended clock signal and outputting a second internal clock signal;
A second charge pump for receiving the first internal clock signal and the second internal clock signal and outputting a first voltage control signal based on the received first internal clock signal and the second internal clock signal ; With
The first amplifying unit adjusts a duty cycle of the pair of first intermediate single-ended clock signals based on the second control signal, and outputs the adjusted pair to the first internal clock signals.
The second amplifying unit adjusts a duty cycle of the pair of second intermediate single-ended clock signals based on the second control signal, and outputs the adjusted signal to the pair of second internal clock signals. Correction circuit. The second charge pump is
An input driver, characterized in that the input of the first and second internal clock signal, and outputs a first voltage value at the first output node based on the first and second internal clock signal,
The duty cycle correction circuit according to claim 21, further comprising: an output unit that receives the first voltage and the reference voltage at the first output node and outputs a first voltage control signal. The input driver is
A first input transistor pair that receives first and second internal clock signals and outputs a first voltage value at the first output node;
23. The duty cycle correction circuit according to claim 22, further comprising: a second input transistor pair that receives first and second inverted internal clock signals and outputs a second voltage value at the first output node. The second charge pump is
A first current source coupled to the second output node;
A second current source coupled to the third output node;
The first input transistor and the first inverting input transistor are connected to the second output node,
23. The duty cycle correction circuit of claim 22, wherein the second input transistor and the second inverting input transistor are connected to the third output node. At least one of the first and second amplifying units is:
First and fourth transistors to which a first voltage control signal is input;
The duty cycle correction circuit according to claim 21, further comprising: a second transistor and a third transistor that receive the first single-ended signal in common and output an internal clock signal . In the duty cycle correction circuit,
26. The duty cycle correction circuit of claim 25, wherein the internal clock signal is standardized as a result of adjusting the duty cycle of the single-ended signal in response to the first voltage control signal. The duty cycle correction circuit includes:
A third amplifier for receiving a third single-ended signal and outputting a third internal clock signal ;
A fourth amplifier for receiving the fourth single-ended signal and outputting the fourth internal clock signal ;
The charge pump receives the first to fourth internal clock signals ,
The first voltage control signal is based on the first to fourth internal clock signals ,
The duty cycle correction circuit according to claim 21, wherein the first to fourth amplifying units adjust a duty cycle of the first to fourth single-ended signals in response to the first voltage control signal. . The duty cycle correction circuit according to claim 27, wherein the first to fourth internal clock signals are based on the first voltage control signal. In a method for generating a clock signal,
Generating a first and second intermediate differential clock signal pair;
Inputting the first intermediate differential clock signal pair to a first amplifying unit to generate a pair of first internal clock signals;
Inputting the second intermediate differential clock signal pair to a second amplifying unit to generate a pair of second internal clock signals;
To generate a second voltage control signal based on the first and second internal clock signal to the steps of inputting the first and second internal clock signal to the second charge pump,
The duty cycle of the first intermediate differential clock signal pair is adjusted based on the second voltage control signal and output to the pair of first internal clock signals, or the duty cycle of the second intermediate differential clock signal pair Is adjusted based on the second voltage control signal and output to the pair of second internal clock signals, the second voltage control signal is supplied to at least one of the first and second amplification units. A method of generating a clock signal, comprising: a step of inputting each. 30. The clock signal generation method of claim 29, further comprising: correcting a duty cycle of the first and second internal clock signals with reference to the second voltage control signal. How it occurs.

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