JP4997401B2 - Display device - Google Patents

Description

  The present invention relates to a technique for writing transmitted image data in a memory, reading the image data from the memory, and displaying the same on a screen.

  The video data, that is, the moving image can be replaced by using still images that are continuous at high speed. The camera forms an object using a lens, converts the intensity of light into an electrical signal, and uses this two-dimensional still image (hereinafter referred to as “image data”) as one-dimensional information on the time axis. Send as.

  That is, the image data is converted into one-dimensional information by sequentially scanning the plane of the light receiving surface from the upper left to the upper right and from the upper to the lower. That is, the image data is finely divided in the horizontal direction, and the divided right end is connected to the left end of the division unit immediately below to convert the data into a one-dimensional signal flow like one string.

  After receiving this one-dimensional signal, the liquid crystal display (hereinafter referred to as “liquid crystal display device”) separates the screens one by one with the left and right sides of the screen as a separator, and reconstructs one piece of image data in the original order. Do. In realizing the reconstruction of the image data, a technique for temporarily writing the received image data into the memory and reading the image data from the memory and displaying it on the screen is used in the liquid crystal display device (see Patent Document 1). ).

  Regarding the direction in which image data is written to the memory and the direction in which the image data is read from the memory, generally, a method of performing the same direction is used. FIG. 12 is an explanatory diagram showing an operation when the writing direction and the reading direction are the same. FIG. 4A shows the writing direction to the memory, and after writing from the left side of the top row to the right side from the start point located at the upper left to the end point located at the lower right, Write from the left side to the right side of the next lower row, and repeat the same operation until the lowest row. FIG. 6B shows the reading direction, and image data is read in the same direction as the writing direction shown in FIG.

If the image data already written in the memory is the initial image shown in FIG. 13A and the image data to be rewritten next is the rewritten image shown in FIG. The obtained image is the same image as the rewritten image shown in FIG. That is, even when the writing start time and the reading start time are the same, the writing speed is usually faster than the reading speed, and the writing direction and the reading direction are the same, so writing and reading are exclusive. Will be done.
JP-A-8-320682

  However, when the writing direction and the reading direction are different, the problem described below occurs.

  FIG. 15 is an explanatory diagram illustrating a first operation when the writing direction and the reading direction are different. FIG. 4A shows the writing direction to the memory. After writing from the right side of the bottom row to the left side from the start point located at the lower right to the end point located at the upper left, the next Is written from the right side to the left side, and the same operation is repeated up to the top row. FIG. 5B shows the reading direction, and image data is read in the same direction as the reading direction described with reference to FIG.

  When writing and reading are performed in the direction shown in FIG. 15, there is always one pixel where writing and reading compete as shown in FIG. 16A. Therefore, as shown in FIG. In the competitive area, there was a problem that noise (flickering) occurred.

  FIG. 17 is an explanatory diagram illustrating a second operation when the writing direction and the reading direction are different. FIG. 4A shows the writing direction to the memory, and after writing from the upper left side to the lower side between the start point located at the upper left and the end point located at the lower right, Writing from the upper side to the lower side of the next right column, the same operation is repeated up to the rightmost column. FIG. 5B shows the reading direction, and image data is read in the same direction as the reading direction described with reference to FIG.

  When writing and reading are performed in the direction shown in FIG. 17, there are always a plurality of pixels in which writing and reading compete as shown in FIG. 18A. As shown in FIG. Since there are areas where writing occurs before writing and areas where writing occurs after reading, when the initial image and the rewritten image of FIG. 13 are used, the images before and after rewriting are mixed as shown in FIG. Then, since the screen is switched in an oblique state, there is a problem in that it gives a sense of discomfort to the user who recognizes that the screen is generally scrolled in the vertical direction or the horizontal direction.

  The present invention has been made in view of the above, and even when the reading direction and the writing direction are different, the first problem is to prevent the occurrence of noise (flicker), and the user feels uncomfortable. It is a second problem not to give.

  The display device according to the first aspect of the present invention is based on storage means capable of storing image data, timing means for outputting a read signal instructing reading of the image data at a predetermined interval, and the output read signal. An input / output control means for reading out the image data stored in the storage means, and a D / A conversion means for supplying a voltage corresponding to the image data to the display means when the read image data is received. When the image data transmitted from the processing device is received, the input / output control unit writes the image data in the storage unit and also starts black from the start to the end of the writing. Alternatively, a display signal for displaying a white image is transmitted to the D / A converter, and the D / A converter receives the display signal when the display signal is received. The voltage response and supplying to said display means.

  In the present invention, when the input / output control means of the display device receives the image data transmitted from the processing device, the received image data is written in the storage means and the writing is started until it is finished. A display signal for displaying a black or white image is transmitted to the D / A conversion means, and a voltage corresponding to the display signal is supplied to the display means by the D / A conversion means, so that the image data is written. During this time, a black or white image is forcibly displayed, and a clear image free from noise (flicker) can be output to the display means.

  According to a second aspect of the present invention, there is provided a display device for updating stored image data on the basis of image data and signals transmitted from a processing device. Timing means for outputting a read signal instructing reading of image data at an interval equivalent to a synchronization signal transmitted from the apparatus at a predetermined interval; and when the output read signal is received, the read signal is stored in the storage means From the processing device, after finishing reading the image data stored up to the end address in the writing area specified by the start address and the end address transmitted from the processing device. Input / output control means for receiving transmitted image data and writing the received image data in the writing area It is characterized in.

  In the present invention, when the input / output control means of the display device receives the read signal output from the timing means, it starts reading the image data stored in the storage means and is transmitted from the processing device. After reading the image data stored up to the end address in the writing area specified by the start address and end address, the image data transmitted from the processing device is received, and the received image data is written to the writing area. Therefore, it is possible to prevent the occurrence of contention between reading and writing in the writing area. Furthermore, since the screen is not switched in an oblique state, an image that does not give the user a sense of incongruity can be provided.

  A mobile terminal according to a third aspect of the present invention is a mobile terminal comprising: a processing device; and a display device that updates stored image data based on image data and signals transmitted from the processing device. The processing apparatus includes a first transmission unit that transmits a synchronization signal at a predetermined interval, a second transmission unit that transmits a writing area specified by a start address and an end address, and an image after transmitting the synchronization signal. Third display means for transmitting data, wherein the display device reads the image data at intervals equivalent to the storage means capable of storing image data and the synchronization signal transmitted by the first transmission means. And a timing means for outputting a read signal for instructing, and when the output read signal is received, reading of the image data stored in the storage means is started, and the second transmission is started. After reading out the image data stored up to the end address designated in the writing area transmitted by the means, the image data transmitted by the third transmitting means is received, and the received image data is And an input / output control means for writing in the writing area.

  An image data update method according to a fourth aspect of the present invention is an image data processed by a processing device and a display device that updates stored image data based on image data and signals transmitted from the processing device. In the updating method, after the processing device transmits a synchronization signal at a predetermined interval, a second step of transmitting a write area specified by a start address and an end address, and after transmitting the synchronization signal A third step of transmitting the image data, and a fourth step in which the display device can store the image data in the storage means, and at an interval equivalent to the synchronization signal transmitted in the first step. A fifth step of outputting a read signal instructing reading of image data, and when the output read signal is received, are stored in the storage means After reading out the image data, after reading out the image data stored up to the end address specified in the writing area transmitted in the second step, the image data transmitted in the third step is read out. Receiving, and writing the received image data into the writing area.

  According to a fifth aspect of the present invention, there is provided a display device for updating stored image data on the basis of image data and control commands transmitted from a processing device. A timing control command for extending the vertical front porch period in the synchronization period to such an extent that writing of image data can be completed is received from the processing device, and the vertical front porch period extended based on the timing control command is received. Timing means for outputting a read signal instructing reading of image data at an interval equivalent to the vertical synchronization period, and receiving the output read signal and within the extended vertical front porch period by the processing device And input / output control means for writing the transmitted image data into the storage means. To.

  In the present invention, since the input / output control means of the display device writes the image data transmitted by the processing device to the storage means within the extended front porch period, there is no conflict between the reading and writing of the image data. Occurrence can be prevented. Furthermore, since the screen is not switched in an oblique state, an image that does not give the user a sense of incongruity can be provided.

  A mobile terminal according to a sixth aspect of the present invention is a mobile terminal comprising: a processing device; and a display device that updates stored image data based on image data and a control command transmitted from the processing device. The processing apparatus includes a first transmission unit that transmits a timing control command for extending a vertical front porch period in the vertical synchronization period to an extent at which writing of image data can be completed, and a second transmission unit that transmits image data. The display device receives the timing control command transmitted by the first transmission unit, and is extended based on the timing control command. Timing to output a read signal instructing reading of image data at an interval equivalent to a vertical synchronization period having a vertical front porch period And an input / output control unit that receives the output read signal and writes the image data transmitted by the second transmission unit to the storage unit within the extended vertical front porch period. It is characterized by.

  An image data updating method according to a seventh aspect of the present invention is an image processed by a processing device and a display device that updates stored image data based on image data and a control command transmitted from the processing device. In the data update method, a first step of transmitting a timing control command for extending a vertical front porch period in a vertical synchronization period to an extent capable of completing writing of image data by the processing device, and transmitting image data And a second step of receiving the timing control command transmitted by the first step and extending based on the timing control command. The image data is read out at the same interval as the vertical synchronization period having the vertical vertical porch period. A fourth step of outputting a read signal, and a fifth step of receiving the output read signal and writing the image data transmitted by the second step in the storage means within the extended vertical front porch period. And a step.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a case where a reading direction and a writing direction differ, generation | occurrence | production of a noise can be prevented and the display apparatus or portable terminal which does not give a discomfort to a user can be provided.

  Hereinafter, the present embodiment will be described with reference to the drawings.

[First Embodiment]
First, the configuration of the liquid crystal display device 1 in the first embodiment will be described.

  FIG. 1 is a configuration diagram showing a configuration of a liquid crystal display device 1 according to the present embodiment. The liquid crystal display device 1 includes an interface circuit 10, a command control circuit 11, a timing circuit 12, an input / output control circuit 13, a RAM 14, a latch circuit 15, a D / A converter 16, an amplifier circuit 17, a signal line switch circuit 18, and a scanning line drive. The circuit 19 and the display unit 20 are provided.

  Of these circuits constituting the liquid crystal display device 1, the interface circuit 10, command control circuit 11, timing circuit 12, input / output control circuit 13, RAM 14, latch circuit 15, D / A converter 16, and amplifier circuit 17 are included. Are formed inside a single driver IC. In addition, a CPU 2 as a processing device is disposed outside the liquid crystal display device 1.

  Next, functions of each circuit constituting the liquid crystal display device 1 will be described.

  The interface circuit 10 is electrically connected to the CPU 2 and receives a CPU signal transmitted from the CPU 2. The CPU signal is a general name including a plurality of signals, and includes, for example, a command signal, a synchronization signal (Vsync signal), a write signal, and image data. After receiving the CPU signal, the interface circuit 10 transmits a command signal among the CPU signals to the command control circuit 11. If a synchronization signal is included, the synchronization signal is also transmitted to the command control circuit 11. When the CPU signal includes a write signal and image data, both the write signal and the image data are transmitted to the input / output control circuit 13.

  The command signal is a plurality of control signals for operating each circuit constituting the liquid crystal display device 1 in accordance with a plurality of functions, and in this embodiment, the image data writing area and writing to the RAM 14 are described. This will be described as a RAM control signal for setting the direction.

  When receiving a timing signal from the interface circuit 10, the command control circuit 11 transmits the signal to the timing circuit 12. When receiving a control signal, the command control circuit 11 sends the signal to the input / output control circuit 13. Send to. That is, when a synchronization signal is received, it is transmitted to the timing circuit 12, and when it is a RAM control signal, it is transmitted to the input / output control circuit 13.

  The timing circuit 12 transmits the timing signal created by the timing circuit 12 to the latch circuit 15 and the scanning line driving circuit 19 at a predetermined interval. Further, a read signal instructing reading of image data from the RAM 14 is transmitted to the input / output control circuit 13 at a predetermined interval. Further, when receiving a timing signal (synchronization signal) from the command control circuit 11, the timing circuit 12 transmits a timing signal and a read signal at intervals equivalent to the synchronization signal.

  The timing signal is a signal for measuring the timing for transferring the image data read from the RAM 14 to the D / A converter 16 and the timing for displaying the read image data on the display unit 20.

  The input / output control circuit 13 receives a control signal (RAM control signal) transmitted from the command control circuit 11, a write signal transmitted from the interface circuit 10, and image data. When the RAM control signal is received, the writing area of the RAM 14 is set so that the image data is written in the writing area specified by the start address and the end address in the RAM control signal, and the write signal and the image data are transmitted. Then, based on the writing direction designated by the RAM control signal, the image data is written into the set writing area. Further, the input / output control circuit 13 receives the read signal transmitted from the timing circuit 12, and outputs the image data written in the RAM 14 from the left side of the uppermost row at an interval equal to the interval at which the read signal is transmitted. After reading in the right direction, reading from the left side to the right side of the next lower row is performed in the same manner, and the operation of reading to the lowest row and transmitting to the latch circuit 15 is repeated.

  The RAM 14 is a memory having a function of storing image data.

  The latch circuit 15 temporarily stores the image data transmitted from the RAM 14 and transfers the image data to the D / A converter 16 based on the timing signal transmitted from the timing circuit 12.

  The D / A converter 16 converts the image data transferred by the latch circuit 15 into an analog signal and transmits it to the amplifier circuit 17.

  The amplifier circuit 17 amplifies the analog image data converted by the D / A converter 16 and transmits it to the signal line switch circuit 18.

Signal line switching circuit 18 supplies the image data amplified by the amplifier circuit 17 to a plurality of signal lines S _m.

The scanning line driving circuit 19 supplies a driving signal for driving the switch elements connected to the plurality of scanning lines _Gn based on the timing signal transmitted from the timing circuit 12.

The display unit 20 includes m rows (m is a natural number excluding zero) of signal lines S _{1 to} S _m and n rows (n is a natural number excluding zero) of scanning lines G _{1 to} G _n intersecting each other, the driving of the connected switching element to the scanning line G _n, the image data supplied to the signal line S _m is output. Further, the section divided by the scanning lines G _{1 to} G _n and the signal lines S _{1 to} S _m functions as a display area 200 for displaying image data.

  The CPU 2 functions as a processing device that transmits a CPU signal. Although this embodiment will be described as a CPU (Central Processing Unit), the present invention is not limited to this, and an MPU (Micro Processing Unit) can also be used.

  FIG. 2 is a circuit configuration diagram showing an example of the circuit configuration of the input / output control circuit 13 and the RAM 14. The input / output control circuit 13 includes a column decoder 131, a row decoder 132, an AND circuit, and the like. The RAM 14 also includes a plurality of word lines WL and a plurality of data lines D that intersect each other. One section surrounded by the word line WL and the data line D is called a memory cell and functions as a storage area for storing image data. The RAM 14 in the present embodiment is composed of, for example, memory cells of 240 rows × 320 columns (hereinafter referred to as “(240, 320)”) as shown in FIG. Of course, the number of memory cells is not limited to this, and can be changed according to the size of the display unit 20 having a display standard such as VGA or S-VGA.

FIG. 3 is a circuit configuration diagram showing an example of the circuit configuration of the memory cell. Memory cell is connected to one electrode connected to the control electrode to the word line WL switch element SS 1 which is connected to the data lines D _1, by connecting the control electrode to the word line WL to one of the electrodes to the data lines D ₂ switching element SS 2 to _the inverter IV 1 connected to the other electrode of the input electrode connected to the other electrode of the switch element SS ₁ output electrode switching element SS _2, the other electrode of the output electrode switching element SS ₁ an input electrode connected is configured to include an inverter IV 2 connected to the other electrode of the switching element SS _2, the output driver OUT which is connected to the input electrode to the input electrode of the inverter IV ₂ to. Note that the inverter IV ₁ and the inverter IV ₂ function as a memory element in the memory cell.

Here, the image data writing operation will be briefly described with reference to FIGS. The input / output control circuit 13 is connected to one of the input terminals of the AND circuit connected to each column of the column decoder 131 corresponding to the write area designated by the RAM control signal transmitted from the command control circuit 11. Prepare to input the signal. After that, when the write signal and the image data are transmitted from the interface circuit 10, the H signal is supplied to the other input terminal of the AND circuit. Therefore, the AND circuit is connected to the data line D connected to the output terminal. H signal is output. The output H signals is supplied to the data lines D ₁ through the inverter IV _a, it is further supplied to the data line D ₂ through the inverter IV _b.

On the other hand, similarly for the row decoder 132, the input / output control circuit 13 connects the word line WL connected to each row of the row decoder 132 corresponding to the write area specified by the RAM control signal transmitted from the command control circuit 11. Prepare to supply drive signals. Then, from the interface circuit 10 when the write signal is transmitted, and supplies a drive signal to the prepared word line WL, and turned on by the drive signal control electrodes of the switching elements SS ₁ and a switch element SS ₂ from off by being controlled, the data lines D ₁ and the data line D ₂ are electrically connected to each of the inverters IV ₁ and the inverter IV _2, writing of image data to the memory element is performed.

  On the other hand, at the time of reading, by supplying a drive signal to the lead wire based on the read signal transmitted from the timing circuit 12 at a predetermined interval, the output driver OUT becomes conductive, and image data is read from the RAM 14. Can do.

FIG. 4 is a circuit configuration diagram showing a circuit configuration of the display area 200. In the display area 200, the switch element SW one electrode is connected to the control electrode to the scanning line G _n to the signal line S _m is connected, the storage capacitor 201 and the display electrode connected to the other electrode of the switch SW 202 is disposed, and a liquid crystal 204 is sandwiched between the display electrode 202 and the counter electrode 203.

Here, liquid crystal display driving will be briefly described with reference to FIGS. 1 and 4. A driving method for displaying image data is performed by line-sequential driving in which image data simultaneously supplied to the signal lines S _{1 to} S _m is sampled with timing signals sequentially supplied to the scanning lines G _{1 to} G _n. .

When a certain time (T _{1 to} T _n ) is assigned to each scanning line G _n , when an address signal based on the timing signal from the timing circuit 12 is applied to the scanning line G ₁ at a certain selection time T ₁ , All the switch elements SW _{11 to} SW _1m arranged on the scanning line G ₁ are turned on, and the switch is turned on. As a result, the image data given to the signal lines S _{1 to} S _m is transmitted to the display electrode 202 via the switch elements SW _{11 to} SW _1m and supplied to the storage capacitor 201. As a result, a voltage difference is generated between the display electrode 202 and the counter electrode 203, and the alignment of liquid crystal molecules in the liquid crystal 204 is controlled. As a result, the brightness (luminance) of incident light from a backlight (not shown) is adjusted, and color display according to image data is enabled via a color filter (not shown).

In the next selection time _{T 2,} all the switch elements _SW 11 _{to SW 1 m} in the scan lines _{G 1} is turned off, the pixel that has been selected by the scanning lines _{G 1} is electrically disconnected from the signal line _S 1 to S _m It is. At this time, the image displayed by the selection time T ₁ is held by the storage capacitor 201 until the address signal is then supplied to the scanning line G _1. Then, all the switch elements _SW 51 _{to SW 5 m} disposed on the scanning line _{G 5} is turned on, the image data is transmitted to the display electrode 202, it is supplied to the storage capacitor 201. Thereafter, the same operation is repeated to display one frame.

  Subsequently, image data reading and writing operations in the liquid crystal display device 1 of the present embodiment will be described. First, the reading operation of the image data stored in the RAM 14 will be described.

  The timing circuit 12 transmits a read signal to the input / output control circuit 13 at a predetermined interval (S101).

  The input / output control circuit 13 receives the read signal transmitted from the timing circuit 12, and reads the image data from the RAM 14 at the received timing (S102).

  In the present embodiment, the readout area read based on the read signal is (1, 1) to (240, 320) shown in FIG. 5A, and the readout direction is located at the upper left of the readout area. Read from the left side of the top row to the right side from the start point to the end point located at the bottom right, then read from the left side of the next lower row to the right side, and repeat the same operation to the bottom row Will be described below.

  The latch circuit 15 receives the image data read in (S102), and transfers the image data to the D / A converter 16 based on the timing signal transmitted from the latch circuit 15 (S103).

  The D / A converter 16 converts the image data transferred by the latch circuit 15 into an analog signal, and transmits it to the display unit 20 via the amplifier circuit 17 and the signal line switch circuit 18 (S104). Since the liquid crystal display driving for displaying the image data on the display unit 20 is the same as the operation described above, the redundant description is omitted here.

  Next, the write operation will be described.

  First, the CPU 2 transmits a CPU signal including a command decode signal to the interface circuit (S201).

  Next, the interface circuit 10 receives the CPU signal transmitted from the CPU 2 and transmits a command decode signal included in the CPU signal to the command control circuit 11 (S202).

  The command control circuit 11 receives the command decode signal transmitted from the interface circuit 10, and since this command decode signal includes a RAM control signal, it transmits the RAM control signal to the input / output control circuit 13 ( S203).

  The input / output control circuit 13 receives the RAM control signal transmitted from the command control circuit 11, and writes data in each column of the column decoder 131 and each row of the row decoder 132 corresponding to the write area designated by the RAM control signal. Prepare to perform (S204).

  Here, the start address of the write area of the RAM 14 designated by the RAM control signal is (1, 1) shown in FIG. 5B, and the end address is (240, 320). On the other hand, the writing direction is from the start point located at the lower right of the writing area to the end point located at the upper left. The following description will be made on the assumption that writing is performed in the left direction and the same operation is repeated up to the top row.

  The CPU 2 transmits both the write signal and the image data to the interface circuit 10 (S205).

  The interface circuit 10 receives the write signal and image data transmitted from the CPU 2 and transmits them to the input / output control circuit 13 (S206).

  The input / output control circuit 13 receives the write signal and image data transmitted from the interface circuit 10. Then, the input / output control circuit 13 writes image data in the writing area of the RAM 14 prepared in (S204) along the writing direction specified by the RAM control signal (S207).

  The input / output control circuit 13 writes the image data in (S207) and transmits a display signal for displaying a black or white image from the start to the end of the writing to the D / A converter 16 (S208). .

D / A converter 16 supplies the output control circuit 13 after receiving a display signal, a voltage enough to all the liquid crystal molecules of the liquid crystal 204 rises to all of the signal lines _{S m} (S209).

  For example, by using a normally white liquid crystal panel in the display unit 20, a black image is forcibly output while image data is being written in the RAM 14. Conversely, white display can be performed by arranging a normally black liquid crystal panel. After completing the writing, the input / output control circuit 13 ends the transmission of the display signal.

  FIG. 6 is a comparison diagram showing an image displayed on the display unit 20 while writing image data to the RAM 14 and an image displayed on the display unit 20 after the writing is completed. Since the input / output control circuit 13 forcibly displays the black screen shown in FIG. 5A during the writing of the image data, an image without noise (flicker) is displayed as shown in FIG. be able to.

  According to the present embodiment, when the input / output control circuit 13 receives the image data transmitted from the CPU 2, the received image data is written in the RAM 14, and the black image is displayed from the start to the end of the writing. Is transmitted to the D / A converter 16, and the D / A converter 16 supplies a voltage corresponding to the display signal to the display unit 20. Therefore, while image data is being written, A black image is forcibly displayed and a clear image free from noise (flicker) can be output to the display unit 20.

[Second Embodiment]
The configuration of the liquid crystal display device 1 and the function of each circuit in the second embodiment are the same as those described in the first embodiment with reference to FIGS.

  Next, the operation of the liquid crystal display device 1 in the present embodiment will be described. First, a read operation will be described.

  The CPU 2 transmits a synchronization signal to the interface circuit 10 (S301).

  The interface circuit 10 receives the synchronization signal transmitted from the CPU 2 and transmits it to the command control circuit 11 (S302).

  The command control circuit 11 receives the synchronization signal transmitted from the interface circuit 10 and transmits it to the timing circuit 12 (S303).

  The timing circuit 12 receives the synchronization signal transmitted from the command control circuit 11, and transmits a read signal to the input / output control circuit 13 at intervals synchronized with the synchronization signal (S304).

  The input / output control circuit 13 receives the read signal transmitted from the timing circuit 12, and reads the image data from the RAM 14 at the received timing (S305).

  In the present embodiment, the readout area and readout direction read based on the read signal are the same as the readout area and readout direction described with reference to FIG. 5A in the first embodiment, and will be described below. To do.

  The latch circuit 15 receives the image data read in (S305), and transfers the image data to the D / A converter 16 based on the timing signal transmitted from the latch circuit 15 (S306).

  The D / A converter 16 converts the image data transferred by the latch circuit 15 from analog to analog, and transmits it to the display unit 20 via the amplifier circuit 17 and the signal line switch circuit 18 (S307). Since the liquid crystal display driving for displaying the image data on the display unit 20 is the same as the operation described in the first embodiment, a duplicate description is omitted here.

  Next, the write operation will be described.

  First, the CPU 2 transmits a CPU signal including a command decode signal to the interface circuit (S401).

  Next, the interface circuit 10 receives the CPU signal transmitted from the CPU 2, and transmits a command decode signal included in the CPU signal to the command control circuit 11 (S402).

  The command control circuit 11 receives the command decode signal transmitted from the interface circuit 10, and since this command decode signal includes a RAM control signal, it transmits the RAM control signal to the input / output control circuit 13 ( S403).

  The input / output control circuit 13 receives the RAM control signal transmitted from the command control circuit 11, and writes data in each column of the column decoder 131 and each row of the row decoder 132 corresponding to the write area designated by the RAM control signal. Prepare to perform (S404).

  Here, it is assumed that the writing area of the RAM 14 designated by the RAM control signal is the first memory block 113a shown in FIG. 7, that is, the top line to the L line. That is, the start address is (1, 1) shown in the figure, and the end address is (79, 320). Also, the writing direction is from the start point located at the upper left of the writing area to the end point located at the lower right, after writing from the upper left side to the lower side and then the upper side of the next right column. The following description will be made on the assumption that the same operation is repeated up to the rightmost column.

  The CPU 2 transmits the synchronization signal in (S301) and, after a predetermined time has elapsed, transmits both the write signal and the image data to the interface circuit (S405). This predetermined time will be described later.

  The interface circuit 10 receives the write signal and image data transmitted from the CPU 2 and transmits them to the input / output control circuit 13 (S406).

  The input / output control circuit 13 receives the write signal and image data transmitted from the interface circuit 10. Then, the input / output control circuit 13 writes the image data in the writing direction of the RAM 14 prepared in (S404) along the writing direction specified by the RAM control signal (S407).

  Here, the predetermined time described in (S405) will be described. The predetermined time is specified in the writing area in (S404) after the CPU 2 transmits the synchronization signal in (S301), that is, the input / output control circuit 13 starts reading the image data in (S305). This is the time when reading of the image data stored up to the end address (79, 320) ends.

  Since the synchronization signal transmitted from the CPU 2 to the interface circuit 10 of the liquid crystal display device 1 in (S301) and the read signal transmitted from the timing circuit 12 to the input / output control circuit 13 in (S304) are synchronized, the CPU 2 The input / output control circuit 13 grasps the timing at which image data starts to be read. Here, the predetermined time can be calculated by grasping in advance the time per line for reading the image data from the RAM 14.

  Thereafter, the operations described in (S301) to (S307) and (S401) to (S407) are repeated. However, the writing area of the RAM 14 designated by the RAM control signal in (S404) is sequentially shifted with respect to each frame. That is, when the write area for the N frame is the first memory block 113a shown in FIG. 7, the write area for the N + 1 frame is the second memory block 113b, that is, the L + 1 line to the M line, and the write area for the N + 2 frame is the third. It is assumed that the memory block 113c, that is, the M + 1 line is the lowest line.

  FIG. 8 is a diagram illustrating a screen displayed in N frames to N + 2 frames. FIG. 4A shows image data displayed after writing to the first memory block 113a, and FIG. 4B shows image data displayed after writing to the second memory block 113b. FIG. 6C shows image data displayed after further writing to the third memory block 113c. As shown in the figure, since the images are not switched in an oblique state, it is possible to provide the user with an uncomfortable image.

  Also, as shown in FIG. 9, the write area is divided into 1/5 areas, the fourth memory block 113d from the L + 1 line to the M line in the case of N frames, and the I + 1 line to the L in the case of N + 1 frames. 5a memory block 113e1 up to the line and 5b memory block 113e2 from the M + 1 line to the J line, in the case of N + 2 frame, the 6a memory block 113f1 from the highest line to the I line and the J + 1 line to the lowest line By setting to write using the 6b memory block 113f2, it is also possible to provide an image having a wipe effect that spreads up and down from the center as shown in FIG.

  In the present embodiment, the writing area is described as 1/3 or 1/5, but 1 / N (N is a natural number of 2 or more) may be used.

  According to the present embodiment, when the input / output control circuit 13 receives the read signal transmitted from the timing circuit 12, the input / output control circuit 13 starts reading the image data stored in the RAM 14 and starts transmitting from the CPU 2. After reading the image data stored up to the end address in the writing area specified by the address and the end address, the image data transmitted from the CPU 2 is received and the received image data is written in the writing area. Thus, the occurrence of contention between reading and writing in the writing area can be prevented. Furthermore, since the screen is not switched in an oblique state, an image that does not give the user a sense of incongruity can be provided.

[Third Embodiment]
The configuration of the liquid crystal display device 1 and the function of each circuit in the third embodiment are the same as those described in the first embodiment with reference to FIGS. Note that, unlike the second embodiment, the CPU 2 does not transmit a synchronization signal.

  Next, the operation of the liquid crystal display device 1 in the present embodiment will be described. First, a read operation will be described.

  The timing circuit 12 transmits a read signal to the input / output control circuit 13 at a predetermined interval (S501).

  The input / output control circuit 13 receives the read signal transmitted from the timing circuit 12, and reads the image data from the RAM 14 at the received timing (S502).

  In the present embodiment, the readout area and readout direction read based on the read signal are the same as the readout area and readout direction described with reference to FIG. 5A in the first embodiment, and will be described below. To do.

  The latch circuit 15 receives the image data read in (S502), and transfers the image data to the D / A converter 16 based on the timing signal transmitted from the latch circuit 15 (S503).

  The D / A converter 16 converts the image data transferred by the latch circuit 15 into an analog signal, and transmits the analog data to the display unit 20 via the amplifier circuit 17 and the signal line switch circuit 18 (S504). Since the liquid crystal display driving for displaying the image data on the display unit 20 is the same as the operation described above, the redundant description is omitted here.

  The liquid crystal display device 1 can display image data on a screen by repeatedly performing the above-described operations (S501) to (S504) for each frame.

  Next, the write operation will be described.

  First, the CPU 2 transmits a timing control command to the interface circuit 10 (S601).

  Here, the timing control command is a timing signal and is a command for extending the vertical front porch (hereinafter referred to as “FP”) period in the vertical synchronization period of the read signal generated by the timing circuit. . This extension period will be described later.

  Next, the interface circuit 10 receives the timing control command transmitted from the CPU 2 and transmits it to the command control circuit 11 (S602).

  The command control circuit 11 receives the timing control command transmitted from the interface circuit 10, and transmits the timing control command to the timing circuit 12 because it is a timing system signal (S603).

  The timing circuit 12 receives the timing control command transmitted from the command control circuit 11, and extends the FP period in the vertical synchronization period of the read signal generated by the timing circuit 12 based on the period specified by the timing control command. (S604).

  The CPU 2 transmits a CPU signal including a command decode signal to the interface circuit (S605).

  The interface circuit 10 receives the CPU signal transmitted from the CPU 2 and transmits a command decode signal included in the CPU signal to the command control circuit 11 (S606).

  The command control circuit 11 receives the command decode signal transmitted from the interface circuit 10, and since this command decode signal includes a RAM control signal, it transmits the RAM control signal to the input / output control circuit 13 ( S607).

  The input / output control circuit 13 receives the RAM control signal transmitted from the command control circuit 11, and writes data in each column of the column decoder 131 and each row of the row decoder 132 corresponding to the write area designated by the RAM control signal. Prepare to perform (S608).

  Here, the start address and the write direction of the write area of the RAM 14 specified by the RAM control signal are the same as the write area and the write direction described in the first embodiment with reference to FIG. To do.

  The CPU 2 transmits a timing control command in (S601) and, after a predetermined time has elapsed, transmits a write signal and image data to the interface circuit (S609). This predetermined time will also be described later.

  The interface circuit 10 receives the write signal and image data transmitted from the CPU 2 and transmits them to the input / output control circuit 13 (S610).

  The input / output control circuit 13 receives the write signal and image data transmitted from the interface circuit 10. Then, the input / output control circuit 13 writes the image data in the writing direction of the RAM 14 prepared in (S608) along the writing direction specified by the RAM control signal (S611).

  Here, the extension period described in (S601) and the predetermined time described in (S609) will be described. FIG. 11 is an explanatory diagram showing transmission of image data within an extended FP period.

  The upper stage shown in the figure shows the timing at which image data is read from the RAM 14 described in (S502) based on the read signal transmitted at a predetermined interval from the timing circuit 12 described in (S501). The predetermined interval here is a vertical synchronization period shown in the figure, and is composed of a back porch (hereinafter referred to as “BP”) period, an image display period, and an FP period. The image display period is a period in which one frame of image data is read from the RAM 14 and displayed on the display unit 20. By repeating the operation of transmitting the read signal to the input / output control circuit 13 at intervals of the vertical synchronization period, a plurality of frames are output to the display unit 20.

  Here, for example, the BP period has three lines from the first line to the third line, the image display period has 128 lines from the fourth line to the 131st line, and the FP period from the 132nd line to the lowest line (133 The following description will be given as two lines up to the first line).

  The lower part of the figure shows the timing at which the timing control command and the image data are transmitted from the CPU 2 to the liquid crystal display device 1. Unlike the second embodiment, since the CPU 2 and the liquid crystal display device 1 are not synchronized, the CPU 2 does not grasp the timing at which the read signal is transmitted from the timing circuit 12. Therefore, the front porch (hereinafter referred to as “FP”) period included in the read signal output from the timing circuit 12 is extended, and the writing of the image data is completed within the extended period, thereby reading out the image data. Avoid conflicts with writing. The FP period to be extended is the FP period of the vertical synchronization period next to the vertical synchronization period in which the timing control command is received.

  Here, in a certain vertical synchronization period, a timing control command is transmitted immediately after the start of BP (hereinafter referred to as “T1”) and immediately before the end of FP (hereinafter referred to as “T2”). The case where it was done is demonstrated.

  In the case of T1, the CPU 2 performs the write operation after a period of 264 lines in total including the vertical synchronization period (133 lines), the BP period (3 lines) and the image display period (128 lines) in the next vertical synchronization period has elapsed. It is necessary to transmit a signal and image data. The FP period is a period (α) necessary for writing image data into the RAM 14.

  In the case of T2, the CPU 2 needs to transmit a write signal and image data after a total of 131 lines of the BP period (3 lines) and the image display period (128 lines) in the next vertical synchronization period have elapsed. There is. The FP period in this case is a period (α) necessary for writing the image data into the RAM 14 as in the case of T1.

  As described above, since the CPU 2 does not grasp the timing at which the read signal is transmitted from the timing circuit 12, the write signal can be reliably avoided in order to avoid contention between reading and writing of the image data from the RAM 14. And the transmission timing of image data need to be longer. That is, the predetermined time described in (S609) is the period of 264 lines described in the case of T1.

  When the predetermined time is a period of 264 lines, the FP period required in T2 is a period (133 lines) obtained by excluding the BP period (3 lines) and the image display period (128 lines) from the period of 264 lines. And a period (α) necessary for writing the image data into the RAM 14. In either case of T1 and T2, in order to write image data within the FP period, it is necessary to make the FP period longer. That is, the extension period described in (S601) is the (period of 133 lines + α period) described in the case of T2.

  Accordingly, the time per line for writing image data to the RAM 14 is grasped in advance, and the FP period is extended to a period longer than (period of 133 lines + α period), for example, 254 lines. Can be avoided reliably.

  According to the present embodiment, the input / output control circuit 13 writes the image data transmitted by the CPU 2 in the RAM 14 within the extended front porch period, thereby preventing the occurrence of contention between reading and writing of the image data. can do. Furthermore, since the screen is not switched in an oblique state, an image that does not give the user a sense of incongruity can be provided.

  Finally, the liquid crystal display device 1 and the processing device 2 described in the first to third embodiments are used in a mobile terminal such as a mobile phone or a PDA (Personal Digital Assistant), a PC (Personal Computer), or the like. It is possible to apply. Further, the liquid crystal display device 1 is not limited to the liquid crystal, and can be applied to a display device using an organic EL or the like.

It is a block diagram which shows the structure of the liquid crystal display device 1 in a 1st form. It is a circuit block diagram which shows an example of the circuit structure of an input / output control circuit and RAM. It is a circuit block diagram which shows an example of the circuit structure of a memory cell. It is a circuit block diagram which shows the circuit structure of a display area. It is explanatory drawing which shows the reading direction and writing direction of the image data in a 1st form. It is a comparison figure which shows the image displayed on the display part while writing image data in RAM, and the image displayed on the display part after finishing writing. It is explanatory drawing which shows the writing area | region and writing direction of the image data in a 2nd form. It is the figure which showed the screen displayed in N frame-N + 2 frame. It is explanatory drawing which shows the writing area | region and writing direction of the image data in a 2nd form. It is the figure which showed the screen displayed in N frame-N + 2 frame. It is explanatory drawing which shows transmission of the image data in the extended FP period. It is explanatory drawing which shows operation | movement when the writing direction and the reading direction are the same. It is a figure which shows the initial screen of the image data already written in memory, and the rewriting screen of the image data to be rewritten. It is a figure which shows the read-out screen after reading. It is explanatory drawing which shows the 1st operation | movement in case a writing direction and a reading direction differ. It is explanatory drawing explaining the case where writing and reading compete. It is explanatory drawing which shows the 2nd operation | movement when a writing direction and a reading direction differ. It is explanatory drawing explaining the case where writing and reading compete.

Explanation of symbols

D, D1, D2 ... data lines G ₁ ~G n _... scan line IV _a, IV b _... inverter OUT ... output driver S ₁ to S m _... signal line _{SS 1,} SS 2, SW ... switching elements T1, T2 ... Selection time WL ... Word line 1 ... Liquid crystal display device 2 ... Processing device 2 ... CPU
DESCRIPTION OF SYMBOLS 10 ... Interface circuit 11 ... Command control circuit 12 ... Timing circuit 13 ... Input / output control circuit 13 ... Input / output circuit 13 ... RAM input / output control circuit 14 ... RAM
DESCRIPTION OF SYMBOLS 15 ... Latch circuit 16 ... Converter 17 ... Amplifier circuit 18 ... Signal line switch circuit 19 ... Scan line drive circuit 20 ... Display part 113a ... 1st memory block 113b ... 2nd memory block 113c ... 3rd memory block 113d ... 4th memory Block 113e1 ... 5a memory block 113e2 ... 5b memory block 113f1 ... 6a memory block 113f2 ... 6b memory block 131 ... Column decoder 132 ... Row decoder 200 ... Display area 201 ... Storage capacitor 202 ... Display electrode 203 ... Counter electrode 204 …liquid crystal

Claims (1)

Storage means capable of storing image data;
Timing means for outputting a read signal instructing reading of image data at a predetermined interval;
Input / output control means for reading out image data stored in the storage means based on the output read signal;
In a display device having D / A conversion means for supplying a voltage corresponding to the image data to the display means when the read image data is received,
When the input / output control unit receives the image data transmitted from the processing device, the input / output control unit writes the image data in the storage unit and displays a black or white image from the start to the end of the writing. A signal is transmitted to the D / A conversion means;
When the D / A conversion unit receives the display signal, the D / A conversion unit supplies a voltage corresponding to the display signal to the display unit.

Images