JP4992859B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a wiring structure of a programmable semiconductor device, a logic integrated circuit device having the wiring structure, an arithmetic circuit device, a memory device, and a programming circuit thereof.

  A conventional semiconductor integrated circuit includes an element such as a transistor formed on a semiconductor substrate and a wiring structure formed on an upper layer of the semiconductor substrate to connect the element. The wiring has a pattern determined at the design stage of the integrated circuit, and it is impossible to change the connection between the transistors after manufacturing the semiconductor integrated circuit.

  A programmable semiconductor integrated circuit such as an FPGA (Field Programmable Gate Array) can solve the above problems. The programmable semiconductor integrated circuit stores the operation of the logic circuit and the arithmetic circuit and the connection between the logic circuit and the arithmetic circuit in a memory, thereby making it possible to change the logic operation and the wiring connection. Here, an SRAM (Static Random Access Memory) cell, an antifuse, a floating gate MOS transistor, or the like is used as a memory element for storing configuration information.

  A DRAM (Dynamic Random Access Memory) cell, a ferroelectric capacitor, or the like can also be used.

US Pat. No. 6,487,106

  In the conventional semiconductor integrated circuit, when a defect is found after manufacturing or when the design is changed, it is necessary to redesign the wiring pattern and then perform manufacturing again.

  In addition, when there is a design change, enormous costs are required for redesigning the wiring pattern and manufacturing the mask. Along with the increase in scale of integrated circuits, the probability of occurrence of defects after manufacturing is increasing, and the cost of masks is rapidly increasing with miniaturization. For this reason, there is a need for a technique that can cope with correction of defects after manufacturing and change of specifications without remaking the mask.

In addition, a programmable semiconductor integrated circuit such as an FPGA can change the circuit configuration by changing the memory content, but the memory element is formed in the same layer as the transistor on the semiconductor substrate. Therefore, there is a problem of occupying a very large area. For this reason, a programmable integrated circuit has a large chip area and an increased manufacturing cost.
Further, in an FPGA in which such a memory element occupies a large area, the area of the wiring switch for changing the connection between the logic circuit and the arithmetic circuit becomes large, so that the ratio of the logic circuit and the arithmetic circuit in the chip area is low. There is a problem even if it becomes. For this reason, in an ordinary FPGA, one logic circuit or arithmetic circuit is provided with as many functions as possible, and by increasing the granularity of the logic circuit or arithmetic circuit, the proportion of the logic circuit or arithmetic circuit in the chip area is increased. ing. However, such a coarse-grained logic circuit or arithmetic circuit has a problem that the use efficiency is low because it is wasted depending on the assigned function.

  In the future, there will be a problem that the power consumption increases due to the leakage current of the memory element storing circuit configuration information, and the stored contents are destroyed due to a soft error caused by cosmic rays.

  In addition, the switch circuit includes a memory circuit and a pass transistor, or an element in which these are integrated, but the on-resistance of the element is as large as several hundred ohms to several kilohms, and there is a problem in that the signal delay increases. is there.

  On the other hand, there is an FPGA using a fuse or an antifuse as a programmable element. These elements such as antifuses can have an on-resistance as small as several hundred Ω, but once programmed to an on or off state, they cannot be restored to their original state. Therefore, it is impossible to cope with correction of a circuit after manufacture and a change in function which the present invention intends to solve.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of changing the wiring connection configuration after manufacturing, enabling correction of defects and changing specifications in the semiconductor integrated circuit, memory device, etc. after manufacturing, and reducing costs. There is to do.

  Another object of the present invention is to provide a reconfigurable semiconductor device that reduces the chip area.

  It is another object of the present invention to provide a reconfigurable semiconductor device that uses a logic circuit or arithmetic circuit with a fine granularity and has high use efficiency of the logic circuit or arithmetic circuit.

  Furthermore, another object of the present invention is to provide a reconfigurable semiconductor device that reduces signal delay.

  A semiconductor device according to one aspect of the present invention that achieves the above object includes a first electrode, a second electrode, and a metal ion that is interposed between the first electrode and the second electrode. The second electrode is made of a material having a lower ionization tendency than the first electrode, and the first electrode and the second electrode are formed by a redox reaction of the metal ion. A two-terminal switch element in which the conductivity between the electrodes changes, the first and second transistors having different polarities connected to the first electrode, and the different polarities connected to the second electrode A switch circuit including the third and fourth transistors.

  The present invention includes a substrate on which an element is formed and a wiring structure provided in an upper layer of the substrate, and the first and second end portions separated from each other in the wiring structure. A wiring element including a variable conductivity type member is provided, and a switching element having the first end and the second end of the wiring as two terminals is provided in the wiring structure.

  In the present invention, the wiring including the variable conductivity type member is a connection hole. In the present invention, the variable conductivity type member is an electrolyte material, a chalcogenide material, or the like, and the two terminals of the switch element are variably set to a short circuit, an open state, or an intermediate state between the short circuit and the open state.

  A semiconductor device according to another aspect of the present invention includes a substrate on which an element is formed, and a wiring structure provided on an upper layer of the substrate. One wiring layer having a wiring including a variable conductivity type member between two end portions, and further, the first end portion covering the variable conductivity type member in a wiring layer different from the wiring layer And a wiring that partially overlaps the second end, and the first end and the second end of the wiring of the one wiring layer are in the first and second ends in the wiring structure. A three-terminal switching element that forms a terminal and the wiring of the other wiring layer that partially overlaps the first end portion and the second end portion forms the control terminal. To do.

  A semiconductor device according to another aspect of the present invention changes conductivity between two wirings by depositing or dissolving a conductive substance from an electrolyte material disposed between the two wirings. A non-volatile switch element is provided. According to the present invention, a programmable logic circuit or arithmetic circuit can be configured by configuring a reconfigurable logic circuit or arithmetic circuit using these switch elements, or by using these switch elements for connecting transistors. A semiconductor device such as a circuit or a memory circuit is formed.

  A semiconductor device according to another aspect of the present invention includes a first electrode, a second electrode adjacent to the first electrode, and a third electrode facing the first electrode and the second electrode. An ion conductor that conducts metal ions interposed between the first electrode, the second electrode, and the third electrode, the first electrode and the second electrode At least one of the electrodes is a material having a lower ionization tendency than the third electrode, and a three-terminal switch element in which the conductivity between the first electrode and the second electrode is changed by an oxidation-reduction reaction of the metal ion. And first and second transistors having different polarities connected to the first electrode, and third and fourth transistors having different polarities connected to the second electrode, Different polarities connected to the third electrode And a fifth and sixth transistors.

  According to the present invention, since it is possible to change the connection of wiring in a semiconductor integrated circuit after manufacture, it is possible to correct defects and change specifications in the semiconductor integrated circuit after manufacture. It enables development and production of semiconductor integrated circuits.

  Also, both the memory element or memory circuit for storing configuration information and the pass transistor for connecting the wirings, which are used in the conventional programmable integrated circuit, are replaced with the wiring structure of the present invention. It is possible.

  According to the present invention, the switch elements can be stacked in multiple layers in the wiring layer, and the density of the switch elements per unit area can be increased.

  Further, according to the present invention, unlike the switch element formed on the substrate, the switch element has no leakage current flowing through the substrate, so that power consumption can be reduced.

  In addition, since this switch element has a smaller on-resistance than a pass transistor, the load driving capability can be increased and the circuit can be operated at high speed. As described above, the wiring structure of the present invention provides superior characteristics in terms of occupied area, power consumption, operation speed, and the like, as compared with a conventional combination of a memory element and a pass transistor. According to the present invention, it is possible to provide a reconfigurable semiconductor device having improved characteristics such as area, delay, leakage current, and soft error resistance.

  The best mode for carrying out the invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a diagram showing a first embodiment of a wiring structure according to the present invention. FIG. 1A is a diagram for explaining a three-dimensional structure of a programmable switch circuit according to the present invention. Referring to FIG. 1A, an embodiment of a wiring structure according to the present invention includes a semiconductor substrate 100, a first wiring layer 101, a second wiring layer 102, and a via-shaped switch element 103.

  Elements such as transistors are formed on the semiconductor substrate 100. The first wiring layer 101 and the second wiring layer 102 each have a planar wiring, and the wiring is made of a conductive material such as copper or aluminum. The via 103 having a switching function is a vertical wiring for connecting one wiring in the first wiring layer 101 and one wiring in the second wiring layer 102.

  An electrolyte material containing metal ions is disposed in the via 103 or in a portion where the via 103 and the wiring of the first wiring layer 101 or the wiring of the second wiring layer 102 are in contact with each other. The conductivity is changed by the method of precipitation.

  For example, as shown in FIG. 1B, copper sulfide (Cu 2 S) is disposed as an electrolyte material 104 in the via 103, and a copper electrode is formed at a portion where the electrolyte material and the first wiring layer 101 are connected. (Referred to as “first electrode”) 105 is disposed, and an electrode made of a material that is difficult to oxidize such as titanium or platinum (referred to as “second electrode”) is connected to the portion where the electrolyte material and the second wiring layer are connected. ) 106 is disposed.

  In FIG. 1B, when a positive voltage is applied to the first electrode 105 and a negative voltage is applied to the second electrode 106, the second electrode basically follows the same principle as metal plating. Electrons (e−) are supplied from 106 to the electrolyte material 104, copper ions (Cu2 +) in the copper sulfide are reduced in the vicinity of the second electrode 106 (Cu2 + 2 + 2e− → Cu), and in the vicinity of the second electrode 106, Copper (Cu) is deposited. Further, by applying a voltage, copper deposited from the second electrode 106 grows toward the first electrode 105 and comes into contact with the first electrode 105. At this time, since the first electrode 105 and the second electrode 106 are connected by the deposited copper, the resistance between both terminals can be reduced. In this state, the specific resistance value between both terminals (on-resistance) can be 50Ω or less, and the resistance value is reduced to 1/10 to 100 minutes compared to the connection using the pass transistor. Can be reduced to about 1.

  From this state, when a negative voltage is applied to the first electrode 105 and a positive voltage is applied to the second electrode 106, the copper deposited between the first electrode 105 and the second electrode 106 is removed. Oxidized (Cu → Cu2 + 2e−) and dissolved again in the electrolyte material 104 as copper ions (Cu2 +), and the connection between the first electrode 105 and the second electrode 106 is broken. The electrical resistance (off-resistance) between the first electrode 105 and the second electrode 106 in this state depends on the thickness of the electrolyte material 104 and the area of the via 103, but is 1 MΩ or more in the prototype device. High resistance. With such an operation principle, the wiring of the first wiring layer 101 and the wiring of the second wiring layer 102 can be short-circuited or opened, and can be used as a switch element. Moreover, the short circuit and the open state can be reprogrammed repeatedly 1000 times or more. Furthermore, it has been confirmed that this short-circuited or opened state is maintained for 1000 hours or more at room temperature. Of course, the via structure according to the present invention may be applied to a stacked via.

  FIG. 2 is a diagram showing another embodiment of the wiring structure of the present invention. Referring to FIG. 2, the wiring structure of the present invention includes a semiconductor substrate 100, a first wiring layer 111, and a second wiring layer 112.

  The semiconductor substrate 100 has elements such as transistors. The first wiring layer 111 and the second wiring layer 112 each have a planar wiring, and the wiring is made of a conductive material such as copper or aluminum. The two wirings of the first wiring layer 111 are close to each other through a minute gap 117 to form a source electrode 114 and a drain electrode 115. An electrolyte material 113 is laminated inside and around the gap 117, and the wiring of the second wiring layer 112 is disposed thereon to constitute the gate electrode 116. The space | gap 117 is good also as the range of 10 nm-1 micrometer as an example.

  In the electrolyte material 113, the conductivity is changed by applying a suitable voltage or current to the gate 116 to deposit a conductive material from the electrolyte material.

  For example, a case where the source electrode 114 and the drain electrode 115 are made of a material that is not easily oxidized such as titanium or platinum, the gate electrode 116 is made of copper, and the member 113 disposed therebetween is made of copper sulfide (Cu 2 S) will be described. To do.

  When a positive voltage is applied to the gate electrode 116 and a negative voltage is applied to the source electrode 114 and the drain electrode 115, electrons are supplied to the copper sulfide in the vicinity of the source electrode 114 and the drain electrode 115 according to the same principle as metal plating. Copper ions Cu 2+ in the copper are reduced, and copper 119 is deposited in the vicinity of the source electrode 114 and the drain electrode 115 as shown in FIG. When a voltage is further applied, this copper precipitate 119 gradually grows, and eventually copper precipitates grown from the source electrode 114 and copper precipitates grown from the drain electrode 115 as shown in FIG. Things come into contact and they are electrically connected.

  Conversely, when a positive voltage is applied to the source electrode 114 and the drain electrode 115 and a negative voltage is applied to the gate electrode 116, the copper 119 deposited near the source electrode 114 and the drain electrode 115 is oxidized, and again in the electrolyte material. And the connection between the source electrode 114 and the drain electrode 115 is broken.

  Thereby, the source 114 and the drain 115 can be short-circuited or opened. In this way, the three-terminal switch element 118 capable of adjusting the conductivity between the source 114 and the drain 115 by the voltage or current applied to the gate 116 is formed in the wiring layer on the upper layer of the substrate.

  When the switch element shown in FIG. 1 or 2 uses an oxidation-reduction reaction of an electrolyte material, at least one terminal and platinum, aluminum, gold, silver, copper, It includes any one of titanium, tungsten, vanadium, niobium, tantalum, chromium, molybdenum, nitrides of these metals, or silicides of these metals. Another at least one terminal includes copper, silver, chromium, tantalum, tungsten, or the like as the second electrode material, and the sulfide of the second electrode material between the first electrode and the second electrode. For example, an electrolyte material containing metal ions or a metal ion ionized and melted from the second electrode has a structure in which an electrolyte material that can move freely is arranged. With this electrode structure, the amount of metal precipitates between the terminals changes due to the oxidation-reduction reaction of metal ions in the electrolyte material by applying a voltage or flowing current between the terminals, and the terminals are short-circuited by the metal precipitates. Alternatively, the electrical conductivity between the terminals can be changed by opening.

  FIG. 3 is a diagram schematically illustrating a cross-sectional configuration of a semiconductor integrated circuit using the switch element. Referring to FIG. 3, an embodiment of a semiconductor integrated circuit according to the present invention includes a semiconductor substrate 100, a plurality of logic circuits 121, 122, 123 formed on the semiconductor substrate 100, a first wiring layer 101, a second wiring layer. The wiring layer 102, the normal via 126, and the vias 103a and 103b having the switching function described in the above embodiment are provided.

  A plurality of logic circuits are formed on the semiconductor substrate 100, and the plurality of logic circuits are connected by wiring of the first wiring layer 101, the second wiring layer 102, or other wiring layers. Wirings in different wiring layers are connected by vias 126 or 103.

  In this embodiment, some vias are vias 103 with variable conductivity as shown in FIG. 1, and the remaining vias are vias 126 of normal conductive material. In the semiconductor integrated circuit having such a configuration, the operation of the circuit can be changed by controlling the state of the via whose conductivity is changed.

  For example, in the case where outputs are obtained from the logic circuits 121 and 123 and a signal is input to the logic circuit 122, when the conductivity of the via 103a is set high and the conductivity of the via 103b is set low, the logic circuit 122 operates depending on the output result of the logic circuit 121. On the other hand, when the conductivity of the via 103 a is low and the conductivity of the via 103 b is set high, the logic circuit 122 operates depending on the output result of the logic circuit 123. In this manner, the operation of the logic circuit 122 can be changed by changing the settings of the vias 103a and 103b that can change the conductivity.

  FIG. 4 is a diagram in which the vias 103a and 103b in which the conductivity of the circuit of FIG. 3 is changed are replaced with three-terminal devices 118a and 118b. Referring to FIG. 4, an embodiment of a semiconductor integrated circuit according to the present invention includes a semiconductor substrate 100, a plurality of logic circuits 131, 132, 133 formed on the semiconductor substrate 100, a first wiring layer 111, a second wiring layer. The wiring layer 112, the gate terminals 116a and 116b formed in the second wiring layer, and the three terminals that can change the conductivity of the two terminals of the first wiring layer by the voltage of the gate terminal as shown in FIG. In the devices 118a and 118b, the three-terminal device 118 is provided with a material 113 that serves to change the conductivity between the terminals.

  In the circuit shown in FIG. 4, the conductivity between the channels of the three-terminal devices 118a and 118b can be changed by applying an appropriate voltage or current to the gates 116a and 116b. For example, when the conductivity of the three-terminal device 118a is set high and the conductivity of the three-terminal device 118b is set low, the logic circuit 132 is connected to the logic circuit 131, and conversely, the conductivity of the three-terminal device 118a is lowered. By setting the conductivity of 118b high, the logic circuit 132 is connected to the logic circuit 133. In this way, the operation of the logic circuit 132 can be changed by appropriately setting the conductivity of the three-terminal devices 118a and 118b.

  Hereinafter, various examples in which the switch element according to the present invention described in the above embodiment is applied to a programmable logic circuit, a memory device, and the like will be described with reference to the drawings.

  FIG. 5 is a diagram showing a configuration of an embodiment of a programmable logic circuit using the switch element of the present invention.

  Referring to FIG. 5, the semiconductor integrated circuit of this embodiment includes a plurality of input terminals 150, a selector circuit 151, a plurality of switch elements 152, a sense circuit 153, and an output terminal 154. Here, the switch 152 element is formed in the wiring layer like the via 103 shown in FIGS. 1 and 3 or the switch element 118 shown in FIGS. 2 and 4, and the conductivity between the two terminals is changed. Is.

  The selector circuit 151 includes three rows connected in series between the output of the switch element 152 and the input of the sense circuit 153, corresponding to the eight switch elements 152, and an inverter for each of the three inputs 150. Pass transistors 153-2 having the inverted signal of 153-1 and the normal signal input to the gate are arranged in an array. When the three input signals 150 are “000”, the output of the switch element 152 in the first column is selected and transmitted to the sense circuit 153, and when the three input signals 150 are “001”, the second The output of the switch element 152 in the column is selected and transmitted to the sense circuit 153. Similarly, when the three input signals 150 are “111”, the output of the switch element 152 in the eighth column is selected. This is transmitted to the sense circuit 153. The output of the selector circuit 151 is input to the inverter 153-1 of the sense circuit 153, and a p-channel MOS transistor 153-2 is connected between the input of the inverter 153-1 and the power source.

  In the circuit shown in FIG. 5, the selector 151 selects one switch corresponding to the input logic from the switch elements 152 according to the logic combination of the input 150, and the selected switch element 152 has a high conductivity. , Connected to a constant potential 155 and open if low.

  The sense circuit 153 discriminates these states and outputs “1” or “0”. For example, the switch element 152 defines a high conductivity state as “0” and a low conductivity state as “1”, and the conductivity is programmed in advance. A logical function is set. When programming the switch element 152, the switch element to be programmed is selected by the selector, and an appropriate voltage is applied from the sense circuit, whereby a voltage is applied between the two terminals of the selected switch element, and the conductive element The rate is changed. Further, when the switch element 152 is the three-terminal device 118, the conductivity is changed by applying an appropriate voltage to the gate terminal 116.

  FIG. 6 is a diagram showing a configuration of an embodiment of a programmable selector circuit using the switch element according to the present invention. Referring to FIG. 6, the selector circuit of this embodiment includes a plurality of input / output terminals 160, a plurality of switch elements 161, and one input / output terminal 162. The switch element 161 is formed in the wiring layer as indicated by 103 in FIG. 1 or 118 in FIG. 2, and the conductivity between the two terminals can be changed.

  In the circuit shown in FIG. 6, by increasing the conductivity of one switch element among the plurality of switch elements 161 and decreasing the conductivity of the remaining switch elements, any one of the plurality of input / output terminals 160 can be selected. Can be connected to the input / output terminal 162. Thereby, for example, a selector that selects and outputs one input from a plurality of inputs, or a signal can be output to an arbitrary signal line from the plurality of signal lines. When it is desired to increase the conductivity between any one of the input / output terminals 160 of the selector circuit and the input / output terminal 162, the arbitrarily selected terminal of the input / output terminals 160 has a certain constant value. And another voltage is applied to the other terminals of the input / output terminal 160. At this time, the input / output terminal 162 is open or biased to a constant voltage via a transistor or a resistance element.

  FIG. 7 is a diagram showing the configuration of another embodiment of the present invention. In this embodiment, a control gate is added to the selector shown in FIG. Referring to FIG. 7, the selector circuit of this embodiment includes a plurality of input / output terminals 160, a plurality of switch elements 161, a plurality of transistors 171, a control input 172, and one input / output terminal 162. .

  In the circuit of FIG. 7, the signal supplied from the control input 172 can turn off the transistor 171 so that no voltage or current is applied to the switch element 161. Thus, only the transistor 171 connected to the switch element 161 to be programmed is turned on and the other transistors 171 are turned off, so that the switch element 161 can be selectively programmed. The transistor 171 may be disposed between the switch element 161 and the input terminal 160. Further, the control input 172 connected to the gate terminal of the transistor 171 may be common to all the transistors, or a separate control input may be connected to each transistor.

  FIG. 8 is a diagram showing the configuration of another embodiment of the present invention. In this embodiment, a bias circuit is added to the selector circuit of FIG. 6 or FIG. Referring to FIG. 8, the selector circuit of this embodiment includes a plurality of input / output terminals 160, a plurality of switch elements 161, a circuit 180 composed of transistors, resistor elements, or a combination thereof, a constant voltage source 181, and one input / output. A terminal 162 is provided.

  The circuit of FIG. 8 is a circuit that applies an appropriate voltage between two terminals of the switch element 161 when programming the switch element 161. For example, the switch element 161 is turned on when a positive voltage is applied to the input / output terminal 160 side and a negative voltage is applied to the input / output terminal 162 side (referred to as “forward bias”), and the voltage is reversed. When applied (referred to as “reverse bias”), it shall be off. Here, a voltage of 1 volt is applied to one of the input / output terminals 160, 0 volt is applied to the other terminals of the input / output terminal 160, the input / output terminal 162 is opened, and the constant voltage source 181 is Assume that it is 0 volts. In this case, the input / output terminal 162 is grounded to 0 volt through a resistance element or transistor 180, and one volt (referred to as “A”) of the switch element 161 is applied with 1 volt from the input terminal 160. Therefore, a forward bias is applied to the switch element A and the switch element A is turned on. Then, a voltage of 1 volt is transmitted from the input / output terminal 160 to the input / output terminal 162 via the switch element A, and the potential of the input / output terminal 162 is increased. Then, since a reverse bias is applied to the switch elements other than A, the switch elements other than A are turned off. In this way, by adding a circuit in which the voltage of the input / output terminal 162 becomes an appropriate voltage, the conductivity of any one switch element can be increased. A programming method in which a resistance element or transistor 180 is added to the input / output terminal 160 side and a bias voltage is applied to the input / output terminal 160 is also possible.

  FIG. 9 is a diagram showing the configuration of another embodiment of the present invention. In this embodiment, a control gate is added to the selector circuit of FIG. Referring to FIG. 9, the selector circuit of this embodiment includes a plurality of input / output terminals 160, a plurality of switch elements 161, a circuit 180 composed of transistors, resistor elements, or a combination thereof, a transistor 190, a constant voltage source 181, and a control. An input 191 and one input / output terminal 162 are provided.

  In the circuit shown in FIG. 9, the transistor 190 can be turned off by the control input 191. Accordingly, the circuit 180 functions so that an appropriate voltage is applied to the input / output terminal 162 during programming of the switch element 161, and conversely, when the switch 180 operates as a selector, the transistor 190 is turned off. It is possible not to affect the operation of the selector.

  FIG. 10 is a diagram showing one application example of the selector circuit of this embodiment shown in FIGS. 6 to 9 as another embodiment of the present invention. Referring to FIG. 10, the semiconductor integrated circuit of this embodiment includes a plurality of input terminals 200, the selector circuit 201, the logic circuit 202, the output terminal 203, and the global wiring 204. The wiring 204 is a wiring having a length of about several tens of microns to several millimeters used for connection with other logic circuits.

  In the circuit shown in FIG. 10, one of the input terminals 200 is connected to the input terminal of the logic circuit 202 by the selector 201. The operation of the output 203 of the logic circuit varies depending on which input terminal the selector 201 selects. Thus, the connection to the wiring 204 connected to another logic circuit and the logic circuit 202 can be changed.

  FIG. 11 is a diagram showing one application example of the selector circuit of the present invention shown in FIGS. 6 to 9 as another embodiment of the present invention. Referring to FIG. 11, the semiconductor integrated circuit of this embodiment includes the selector circuit 211, the logic circuit 202, the plurality of output terminals 213, and the global wiring 204 connected to other logic circuits. The wiring 204 is a wiring having a length of about several tens of microns to several millimeters used for connection with other logic circuits. In the circuit illustrated in FIG. 11, the selector 211 can propagate the output of the logic circuit 202 to one or more wirings arbitrarily selected in the wiring 204.

  FIG. 12 is a diagram showing a configuration of an embodiment of a programmable logic circuit (semiconductor integrated circuit) to which the switch element of the present invention is applied. Referring to FIG. 12, this embodiment includes a plurality of input terminals 220, a plurality of switch elements 221, a logic gate 222, and an output terminal 223. Here, if the number of input terminals 220 is M and the total number of input terminals of the logic gate 222 is N, one switch element 221 is arranged at each intersection of the vertical and horizontal wirings, and the total number of switch elements 221 is M. × N.

  The switch element 221 is formed in the wiring layer like the via 103 in FIG. 1 or the switch element 118 in FIG. 2, and the conductivity between the two terminals can be changed.

  The circuit shown in FIG. 12 includes an input and an output by a logic circuit (logic gate) 222 in which simple gates such as NANDs and inverters are regularly arranged and a switch element 221 that changes connection of input and output signals. The logic function between can be changed.

  An example of the configuration is shown in FIGS. FIG. 13 shows an example of a semiconductor integrated circuit to which a logic function can be programmed, to which the wiring structure of the present invention is applied. Referring to FIG. 13, the semiconductor integrated circuit of this embodiment includes a switch matrix 400, NAND gates 401 to 404, inverters 405 to 408, a switch matrix 409, and a switch matrix 410. At the intersections of the wirings of the switch matrices 400, 409, and 410, the switch elements having the structure shown in FIG. 1 or FIG. 2 are provided.

  Of these intersections, a portion where the vertical wiring and the horizontal wiring are connected by the switch element is indicated by a black dot 411. In addition, among the intersections, those without the black dot 411 indicate that the switch elements that connect the vertical wiring and the horizontal wiring are not connected in an open state.

  FIG. 13A shows an example in which a half adder is configured using this semiconductor integrated circuit. By appropriately programming the switch matrices 400, 409, and 410, the connection of the logic gates 401 to 408 can be changed, and a circuit equivalent to the half adder shown in FIG. 13B can be configured.

  FIG. 13C shows an example in which a set-reset flip-flop with an enable input is configured using this semiconductor integrated circuit. By appropriately programming the switch matrices 400, 409, and 410, the connection of the logic gates 401 to 408 can be changed, and a circuit equivalent to the flip-flop (set reset with enable input) shown in FIG. .

FIG. 14 is a diagram for explaining an example of a method for changing the connection of the switch matrices 400, 409, and 410 of the semiconductor integrated circuit shown in FIG. Referring to FIG. 14, the switch matrix includes a horizontal wiring 424, a vertical wiring 422, a switch element 420, and a transistor 426 for setting the horizontal wiring 424 to a constant potential. Here, the switch element 420 is a switch element formed in the wiring layer shown in FIG. 1 or 2, and is arranged by the number of intersections of the vertical wiring and the horizontal wiring. For example, when there are m vertical wirings 422 and n horizontal wirings 424, m × n switches are arranged. Assume that the initial states of these switch elements are all off. Further, of the two terminals of the switch element, a positive voltage is applied to a terminal connected to the vertical wiring 422 and a negative voltage is applied to a terminal connected to the horizontal wiring 424. Assume that the switch transitions to the ON state when the potential difference between is greater than the threshold value V _TH .

In the circuit shown in FIG. 14, when the target switch element 420a is changed from the OFF state to the ON state, a voltage higher than the threshold value V _TH (here, 2V _TH) is applied to the vertical wiring 422a connected to the switch element 420a. ) Is applied. Further, the horizontal wiring 424a connected to the switch element 420a is grounded by turning on the transistor 426a. Then, since the voltage 2V _TH higher than the threshold value V _{TH of the} switch element is applied between both terminals of the target switch element 420a, the switch transits to the ON state. At this time, a voltage lower than the threshold value V _TH (here, V _TH ) is applied to the vertical wiring 422 not connected to the target switch element 420a, and the horizontal wiring 424 not connected to the switch element 420a. The transistor 426 is in an OFF state, and the voltage V _TH of the vertical wiring 422 is propagated. Therefore, since 2V _TH and V _TH are applied to both terminals of the elements connected to the vertical wiring 422a and the horizontal wiring 424, respectively, the voltage between the terminals becomes V _TH , but this voltage is the threshold voltage. _Does not exceed V _TH , so the switch state does not change. Further, since V _TH and 0 volt are applied to both terminals of the element connected to the vertical wiring 422 and the horizontal wiring 424a, the voltage between the terminals becomes V _TH, and this voltage also has a threshold voltage V _{Since TH} does not exceed, the state of the switch does not change. Since _VTH is applied to both terminals of the elements connected to the vertical wiring 422 and the horizontal wiring 424, the voltage between the terminals is zero, and the state of the switch does not change. In this way, only the state of the arbitrarily selected switch element 420a can be shifted to the on state.

  FIG. 15 is a diagram showing an example of a method for changing the connection of the switch matrices 400, 409, and 410 of the semiconductor integrated circuit shown in FIG. Referring to FIG. 15, the switch matrix includes a horizontal wiring 501, a vertical wiring 500, a switch element 504, a transistor 505 inserted in series between the vertical wiring 500 and the switch element 504, and a gate of the transistor 505. A control line 502 for controlling the terminals is provided. Here, the switch elements 504 are the switch elements 103 and 118 formed in the wiring layer shown in FIG. 1 or FIG. 2, and are arranged by the number of intersections of the vertical wiring and the horizontal wiring. For example, when there are m vertical wirings 500 and n horizontal wirings 501, m × n switches are arranged. Of these two terminals of the switch element, when a positive voltage is applied to the terminal connected to the vertical wiring 500 and a negative voltage is applied to the terminal connected to the horizontal wiring 501, the switch is turned on. When a voltage is applied in the reverse direction, the state transitions to the off state.

  In the circuit shown in FIG. 15, when the target switching element 504a is turned on and the vertical wiring 500a and the horizontal wiring 501a are connected, a voltage of about 1 volt is applied to the vertical wiring 500a connected to the switching element 504a. Is applied. The vertical wiring 500 that is not connected to the switch element 504a is grounded. Further, a voltage is applied to the control terminal 502a so that the transistor 505a is turned on at the gate of the transistor 505a connected to the switch element 504a. Other control terminals 502 are grounded. Then, the voltage applied between the vertical wiring 500a and the adjacent vertical wiring 500 is resistance-divided by the switch element 504a serving as the target and the switch element 504b other than the target, and the forward bias is applied to the switch element 504a. A reverse bias is applied to the element 504b. At this time, the switch element 504a to which the forward bias is applied transitions to the on state, and the switch element 504b to which the reverse bias is applied transitions to the off state. After all of the switch elements 504b to which the reverse bias is applied have transitioned to the OFF state, the forward wiring can be further applied to the switch element 504a by grounding the horizontal wiring 501a.

  In this manner, the switch element 504a is turned on and the switch element 504b is turned off, so that the arbitrarily selected wiring 500a and the wiring 501a are connected. At this time, since the control signal 502 is grounded, the transistor 505 is in an off state, no voltage is applied between both terminals of the switch element 504, and the impedance of the switch element 504 does not change. For this reason, the switch element connected to the other wiring 501 in the horizontal direction is not affected.

  FIG. 16 is a diagram for explaining a method of changing the connection of the switch matrices 400, 409, and 410 of the semiconductor integrated circuit shown in FIG. Referring to FIG. 16, the switch matrix includes a horizontal wiring 511, a vertical wiring 510, a switch element 513, and a control line 512 for controlling the gate terminal of the switch element 513. Here, the switch element 513 is the switch element 118 formed in the wiring layer shown in FIG. 2, and is arranged by the number of intersections of the vertical wiring and the horizontal wiring. For example, when there are m vertical wirings 510 and n horizontal wirings 511, m × n switches are arranged.

  Among these three terminals of the switch element 513, a positive voltage is applied to the gate terminal connected to the control line 512, and the terminal connected to the vertical wiring 510 or the side connected to the horizontal wiring 511 is connected. When a negative voltage is applied to at least one of the terminals, the switch element 513 transitions to an on state, and when a voltage is applied in the reverse direction, it transitions to an off state.

  In the circuit shown in FIG. 16, when the switch element 513a as a target is turned on and the vertical wiring 510a and the horizontal wiring 511a are connected, the vertical wiring 510a connected to the switch element 513a is grounded. A voltage of about 1 volt is applied to the vertical wiring 510 that is not connected to the switch element 513a. Further, a voltage of about 1 volt is applied to the control terminal 512a connected to the switch element 513a. Other control terminals 512 are opened. Then, a positive voltage is applied to the control gate of the switch element 513a, and the terminal connected to the vertical wiring 510a is grounded, so that the switch element 513a is turned on. The switch element 513b does not change its state because a voltage of about 1 volt is applied to both the control gate and the vertical wiring. Since the switch element 513 connected to the control terminal 512 is open at the control terminal, electrons are not exchanged at the control terminal, so that the state of the switch element does not change. In this manner, when the switch element 513a is turned on, the arbitrarily selected wiring 510a and the wiring 511a are connected.

  FIGS. 17A and 17B show an embodiment of the three-dimensional structure of the switch matrices 400, 409, and 410 of the semiconductor integrated circuit shown in FIG. Referring to FIGS. 17A and 17B, this switch matrix includes a semiconductor substrate 100, wirings 431 formed on the semiconductor substrate 100, and switch elements 432 that connect (short-circuit) or open the wirings. . The switch elements 432 are two-dimensionally or three-dimensionally arranged in the wiring layer, and a switch matrix 433 is formed on a different plane from the semiconductor substrate 100. Logic gates 401 to 408 in FIG. 13 are formed on the semiconductor substrate 100. Note that in FIG. 17A, the switch element 432 is provided in the vertical direction between the wirings 431 of different wiring layers, and in FIG. 17B, the switch element 432 is provided between the vertical and horizontal wirings (same wiring layer). It has been.

  On the other hand, FIG. 18 is a diagram showing an example of a three-dimensional structure of a switch matrix that constitutes a comparative example of the present invention (a configuration not employing the configuration of the present invention). Referring to FIG. 18, the switch matrix 433 according to the comparative example includes a semiconductor substrate 100, wiring 431, a memory element 442 formed on the semiconductor substrate 100, and a pass transistor 443 formed on the semiconductor substrate. The switch matrix according to the comparative example requires not only a wiring layer but also a memory circuit and a pass transistor on a semiconductor substrate, and is formed at a location different from the logic gate 430, so that the area becomes very large. In addition, since the on-resistance of the pass transistor is large, there is a problem that a signal propagation delay is increased. Furthermore, in the future, it is expected that problems such as an increase in leakage current of a circuit formed on the semiconductor substrate and destruction of configuration information stored in the memory element due to a soft error will occur. For this reason, the switch matrix according to the present invention shown in FIG. 17 is more advantageous than the conventional one in terms of area, delay, leakage current, soft error resistance, and the like.

  FIG. 19 is a diagram showing an embodiment of a switch box to which the wiring structure of the present invention is applied. Referring to FIG. 19, the switch box of this embodiment includes a plurality of input / output terminals 230 and a plurality of switch elements 231 that connect two terminals of the input / output terminals 230. The switch element 231 is formed in the wiring layer as indicated by 103 in FIG. 1 or 118 in FIG. 2, and the conductivity between the two terminals can be changed.

  The circuit shown in FIG. 19 connects an arbitrary input / output terminal and another arbitrary input / output terminal by turning on an arbitrary switch element. In addition, by turning on a plurality of switch elements, it is possible to output a signal input from a certain terminal to a plurality of wiring nodes.

The switch element 231 may be arranged for all combinations of two terminals selected from the input / output terminals 230, or may be arranged for a part thereof. FIG. 19 shows an example in which four input / output terminals 230 are provided, and switches are arranged for all combinations of two terminals selected from these. When such switch elements are arranged for all combinations of two terminals among the N input / output terminals, _{two N} C switch elements are required.

  FIG. 20 is a diagram showing an embodiment of a programmable semiconductor integrated circuit to which the wiring structure of the present invention is applied. Referring to FIG. 20, the semiconductor integrated circuit of the present embodiment includes a plurality of logic blocks 240 and a switch box 241 for connecting the plurality of logic blocks 240 to each other.

  The logic block 240 has a structure in which a logic function between an input and an output can be arbitrarily programmed by the look-up table of FIG. 5 or the combination of the programmable switch and logic gate of FIG. The switch 241 is made up of the selector in FIG. 6 and the switch box in FIG. 19, and can connect an arbitrary input / output terminal to another arbitrary input / output terminal. Accordingly, a semiconductor integrated circuit that realizes a desired function can be realized by arbitrarily connecting logic blocks programmed with an arbitrary logic function.

  FIGS. 21A and 21B are diagrams showing a configuration of an embodiment of a memory cell to which the wiring structure according to the present invention is applied, in which FIG. 21A shows a cross-sectional configuration and FIG. 21B shows a circuit configuration. Yes. Referring to FIGS. 21A and 21B, the memory cell of this embodiment includes a semiconductor substrate 100, a transistor 251, a first wiring layer 101, a second wiring layer 102, and a conductive layer formed on the semiconductor substrate 100. A via 103 (two-terminal switching element) whose rate is changed, a bit line 255, a word line 256, and a plate line 257 are provided.

  As described with reference to FIG. 1, the via 103 (two-terminal switch element) whose conductivity is changed includes an electrolyte material such as a metal sulfide. The electrical conductivity between the terminals can be changed by depositing or dissolving a metal substance in the vicinity of the terminals. A terminal on one side of the via 103 whose conductivity is changed is connected to a source terminal or a drain terminal of the transistor 251. Further, of the source terminal or the drain terminal of the transistor 251, the terminal that is not connected to the via 103 is connected to the bit line 255 or the plate line 257. Further, the line of the bit line 255 or the plate line 257 that is not connected to the transistor 251 is connected to the terminal of the via 103 that is not connected to the transistor 251. The gate terminal of the transistor 251 is connected to the word line 256.

  In a semiconductor integrated circuit having a plurality of memory cells having such a structure, the conductivity of the via of each memory cell is programmed in advance, and the voltage of the word line 256 of one memory cell is manipulated, whereby the transistor 251 Is turned on, and the programmed information can be read by detecting the conductivity between the bit line 255 and the plate line 257 in this state.

  Further, at the time of programming, the transistor 251 is turned on by manipulating the voltage of the word line 256 of a certain memory cell, and an appropriate voltage is applied between the bit line 255 and the plate line 257 in this state. , The conductivity of the via 103 can be changed. Thus, a memory circuit for storing information can be realized by applying the wiring structure of the present invention.

  22A and 22B are diagrams showing the configuration of another embodiment of the memory cell to which the wiring structure of the present invention is applied. FIG. 22A shows a cross-sectional configuration, and FIG. 22B shows a circuit configuration. Show. 22A and 22B, the memory cell of this embodiment includes a semiconductor substrate 100, a transistor 251 formed on the semiconductor substrate 100, a first wiring layer 111, a second wiring layer 112, and a metal. An electrolyte material 113 containing sulfide and the like, a gate terminal 116 for controlling the amount of metal precipitates in the electrolyte material 113, a bit line 255, a word line 256, and a plate line 257 are provided.

  As shown in FIG. 2, the electrolyte material 113 and the gate 116 have a function of short-circuiting or opening the two wirings of the first wiring layer 111. The electrolyte material 113 contains a metal sulfide or the like, and the electrical conductivity between the terminals can be changed by depositing or dissolving a metal substance near the terminals by a voltage applied between the terminals or a flowing current. One terminal in contact with the electrolyte material 113 is connected to the source terminal or the drain terminal of the transistor 251. Further, of the source terminal or the drain terminal of the transistor 251, the terminal that is not connected to the terminal in contact with the electrolyte material 113 is connected to the bit line 255 or the plate line 257. Further, the line of the bit line 255 or the plate line 257 that is not connected to the transistor 251 is connected to the terminal that is not connected to the transistor 251 among the terminals in contact with the electrolyte material 113. The gate terminal of the transistor 251 is connected to the word line 256.

  In a semiconductor integrated circuit having a plurality of memory cells having such a structure, the conductivity of the electrolyte material 113 of each memory cell is programmed in advance, and the voltage of the word line 256 of one memory cell is manipulated, The programmed information can be read by turning on the transistor 251 and detecting the conductivity between the bit line 255 and the plate line 257 in this state.

  At the time of programming, the conductivity of the electrolyte material 113 can be changed by applying an appropriate voltage or passing a current between the bit line 255, the plate line 257, and the gate terminal 116. Thus, a memory circuit for storing information can be realized by applying the wiring structure of the present invention.

  FIG. 23 is a diagram showing a configuration of an embodiment of a memory cell array using the memory cell of the present invention. Referring to FIG. 23, this memory cell array includes a bit line 255, a word line 256, a switch element 258, an access transistor 251, and a plate line 257. The switch element 258 and the access transistor 251 constitute the memory cell shown in FIG. 21 or FIG. 22, and are arranged by the number of intersections between the bit line and the word line. For example, when there are m bit lines 255 and n word lines 256, m × n switches are arranged in a matrix.

  In the circuit shown in FIG. 23, rewriting of information in the memory cell is realized by changing the impedance of the switch element of the target memory cell. In this embodiment, a voltage of about 1 to 2 volts is applied to the word line 256a. Then, the access transistor 251a is turned on, and the voltage of the bit line 255 and the voltage of the plate line 257 are applied between the two terminals of the switch element 258a. At this time, when a forward bias is applied to the switch element, the impedance of the switch element 258a decreases, and when a reverse bias is applied, the impedance increases. Since other word line 256b is grounded, access transistor 251b is off, no voltage is applied between the two terminals of switch element 258b, and the impedance does not change.

  In this way, only the impedance of the memory cells connected to the arbitrarily selected word line can be changed.

  When reading the information written in the memory cell, a voltage of about 1 to 2 volts is applied to the word line 256a connected to the memory cell to be read to turn on the access transistor 251a, and the plate The line 257 is set to the ground potential, and the bit line 255 is precharged to a voltage of about 1 to 2 volts. At this time, if the impedance of the switch element 258a is high, a voltage of about 1 to 2 volts appears as the voltage of the bit line 255, and conversely, if the impedance of the switch element 258a is low, 0% is applied to the bit line 255. A voltage near volt appears.

  Thus, by detecting the voltage appearing on the bit line, the information written in the memory cell of the selected word can be read. Further, since the access transistor 251b of the memory cell that is not selected is in the OFF state, the state of the switch element 258b does not affect this read operation.

  In the memory cell array shown in FIG. 23, unlike the switch matrix described above, a plurality of memory cells connected to a certain bit line 255 are all connected to a common plate line 257. That is, the conductivity between the paired bit line 255 and the plate line 257 can be changed, but any two wirings cannot be connected.

  FIG. 24 is a diagram showing a configuration of an embodiment of a write circuit or a read circuit of a memory cell to which the wiring structure of the present invention is applied. Referring to FIG. 24, the memory cell write circuit or read circuit of this embodiment includes a current source 270, a memory cell 271 containing a switch element 258, a reference voltage 273, a voltage comparator 274, and an output terminal 275. .

  In the circuit shown in FIG. 24, a current is supplied to the memory cell 271 by the current source 270. At this time, the voltage appearing in the memory cell 271 changes depending on the conductivity of the switch element 258 in the memory cell 271. The voltage comparator 274 compares the voltage appearing in the memory cell 271 with the reference voltage 273 and determines whether the voltage appearing in the memory cell 271 is higher or lower than the reference voltage 273. For example, when it is desired to increase the conductivity of the switch element 258 to a desired conductivity, when the current of the switch element 258 is gradually increased by flowing current from the current source 270 into the memory cell 271, the voltage appearing in the memory cell 271 is increased. Gradually decreases. When the voltage appearing at the memory cell 271 becomes smaller than the reference voltage 273, the value of the output terminal 275 of the voltage comparator 274 changes, so that it is determined that the conductivity of the memory cell 271 has increased to a desired value. it can.

  Conversely, when it is desired to reduce the conductivity of the memory cell 271, the voltage appearing in the memory cell 271 gradually increases. Therefore, by detecting the timing at which this voltage becomes higher than the reference voltage 273, the desired conductivity can be obtained. Can be determined. Thus, by using the circuit of the present invention, it is possible to determine whether the conductivity of the memory cell is programmed to a desired value.

  FIG. 25 is a diagram showing an embodiment of a configuration in which a reference voltage is generated in a replica memory cell in the write circuit or read circuit of the memory cell of FIG. Referring to FIG. 25, the memory cell write or read circuit of this embodiment includes two current sources 270, a memory cell 271 having a switch element 258, and a replica having an element 285 having a certain conductivity such as a resistance element or a transistor. A memory cell 284, a voltage comparator 274, and an output terminal 275 are provided. Replica memory cell 284 has a configuration in which switching element 258 of memory cell 271 is replaced with element 285 having a constant conductivity.

  In the circuit shown in FIG. 25, the same current is supplied to both the memory cell 271 having the switch element 258 and the replica memory cell 284 having a fixed conductivity, and the voltage comparator 274 compares the magnitude relation of the voltages appearing in both. Thus, it can be determined which of the conductivity of the memory cell 271 and the conductivity of the replica memory cell 284 is higher. For example, by setting the conductivity of the replica memory cell 284 to a target conductivity when the memory cell 271 is programmed, it is possible to determine whether or not the conductivity of the memory cell 271 has reached the target conductivity. . Such a programming circuit can determine whether the conductivity of the memory cell has been programmed to a desired value. Further, by providing a plurality of replica memory cells 284 having different conductivities, it becomes possible to compare the conductivities of a plurality of replica memory cells having different conductivities and the memory cells 271, and the difference in conductivities can be compared with analog information. It is possible to distinguish analog information and multi-value information by assigning them to multi-value information. The impedance of the resistance element 285 included in the replica memory cell 284 is preferably set larger than the on-resistance of the switch element 258 and smaller than the off-resistance.

  FIG. 26 is a diagram showing the configuration of another embodiment of the write circuit or read circuit of the memory cell to which the wiring structure of the present invention is applied. Referring to FIG. 26, the memory cell write or read circuit of the present invention includes a voltage source 290, a memory cell 271 having a switch element 258, a reference current 292, a current comparator 293, and an output terminal 294.

  In the circuit shown in FIG. 26, a current flows depending on the conductivity of the switch element 258 by applying a voltage from the voltage source 290 to the memory cell 271. By comparing whether the current is larger or smaller than the reference current 292 with the current comparator 293, it is possible to determine whether the conductivity of the switch element is higher or lower than the desired conductivity.

  FIG. 27 is a diagram showing an example in which a reference current is generated in the replica memory cell in the memory cell write or read circuit of FIG. Referring to FIG. 27, a memory cell write or read circuit according to the present invention includes two voltage sources 290, a memory cell 271 having a switch element 258, and a replica memory having an element 285 having a certain conductivity such as a resistance element or a transistor. A cell 284, a current comparator 293, and an output terminal 294 are provided.

  In the circuit shown in FIG. 27, the same voltage is applied to the memory cell 271 and the replica memory cell 284, and the magnitude relationship between the currents flowing through both is compared, whereby the conductivity of the memory cell 271 is greater than the conductivity of the replica memory cell 284. Is also determined as being high or low. By disposing an element having a target conductivity in the replica memory cell 284, it can be determined whether or not the memory cell 271 has reached the target conductivity. Furthermore, by making the conductivity of the memory cell 271 correspond to analog information or multi-value information, preparing a plurality of replica memory cells having different conductivity, and comparing the conductivity of the replica memory cell and the memory cell 271, The conductivity of the memory cell is handled in an analog manner, and analog information and multi-value information can be discriminated.

  FIG. 28 is a diagram showing an example of a detailed circuit configuration of the write circuit and the memory cell array of the memory shown in FIG. Referring to FIG. 28, the memory write circuit is an asynchronous circuit that inputs a data input 450 to a data terminal D, inputs a write pulse 451 to a clock terminal, and outputs a normal output (Q) 466 and an inverted output (/ Q) 452. A D-type flip-flop 471 with a reset input, a signal obtained by inverting the data input 450 by the inverter 478, is input to the data terminal D, and a write pulse 451 is input to the clock terminal, and a normal output (Q) 453 and an inverted output (/ Q) A D-type flip-flop 472 with an asynchronous reset input for outputting 467, a source connected to a power source, a pMOS switch (transistor) 454 for inputting the inverted output 452 of the D-type flip-flop 471 to the gate, and a source grounded, An nMOS switch in which the normal output 453 of the D-type flip-flop 472 is input to the gate. And Ji 455, and a pMOS current mirror circuit 456 which is connected to the drain of the pMOS switch 454, the nMOS current mirror 457 connected to the drain of nMOS switch 455.

  The memory cell array 461 includes a bit line 255, a reference line 459, a plate line 257, and a plurality of memory cells 271. The memory cell 271 includes an access transistor 251 and a switch element 258. The gate of the access transistor 251 is connected to the word line, one of the source and the drain is connected to the bit line, and the other of the source and the drain is the switch element 258. The other end of the switch element 258 is connected to the plate line 257.

  The memory write circuit has two replica memory cells (see FIG. 25), the first replica memory cell 284a has a dummy access transistor 474 and a reference resistance element 285a, and the second replica memory cell 284b has A dummy access transistor 477 and a reference resistor 285b are provided. In the dummy access transistor 474 of the first replica memory cell 284a and the dummy access transistor 477 of the second replica memory cell 284b, one of the source and the drain is commonly connected to the reference line 459, and a data input 450 is connected to the gate. The signals obtained by inverting the data input 450 by the inverter 479 are respectively input. One of the first and second terminals of the switch element 285a of the first replica memory cell 284a and the switch element 285b of the second replica memory cell 284b is connected in common to the plate line 257, and the first and second terminals The other terminal is connected to the other of the sources and drains of the dummy access transistors 474 and 477. An nMOS switch 468 is inserted between the plate line 257 and the ground, and the normal output 466 of the D-type flip-flop 471 is input to the gate of the nMOS switch 468. When it is on, the plate line 257 is set to the ground potential. A pMOS switch 469 is inserted between the plate line 257 and the power supply VDD, and the inverted output 467 of the D-type flip-flop 472 is input to the gate of the pMOS switch 469, and when it is on, the plate line 257 is set to the power supply potential. The reference line 459 is connected to the drain of one transistor (a transistor in which the source and the drain are connected) of the transistor pair of the pMOS current mirror circuit 456 and the nMOS current mirror circuit 457. The bit line 255 is connected to the drain of the other transistor of the transistor pair of the pMOS current mirror circuit 456 and the nMOS current mirror circuit 457. The current flowing through the bit line 255 to which the selected memory cell 271 is connected and the current (mirror current) flowing through the reference line 459 to which the selected replica memory cell 284 is connected are set equal. The voltage comparison circuit 274 compares the voltages of the bit line 255 and the reference line 459, and the output is connected to the reset terminals R of the D-type flip-flops 471 and 472.

  The switch element 258 is the switch element formed in the wiring layer shown in FIG. 1 or FIG. The dummy access transistors 474 and 477 are elements having the same characteristics as the access transistor 251 of the memory cell 271. The reference resistance elements 285a and 285b are elements having a target resistance value when setting the resistance value of the switching element 258 of the memory cell 271, and the impedance of the reference resistance 285b is larger than the impedance of the reference resistance 285a. The operation of the write circuit shown in FIG. 28 will be described.

  In the circuit shown in FIG. 28, when performing a write operation by setting “1” to the data input 450, programming is performed so that the impedance of the switch element 258 is lower than the resistance value of the reference resistor. For example, when the data 450 is set to “1” and a rising edge is input to the write pulse input 451, the output 452 becomes “0” and the output 466 becomes “1”. Then, the pMOS switch 454 is turned on, and a current is supplied to the pMOS current mirror circuit 456. Further, the nMOS switch 468 is turned on, and the plate line 257 is set to the ground potential.

  The access transistor 251 of the memory cell 271 selected by the word line 256 (the selected word line 256 is at the H level and the other word lines are at the L level) is in the ON state, and the current supplied from the pMOS current mirror circuit 456 is The current flows to the plate line 257 via the line 255, via the access transistor 251 of the memory cell 271 and the switch element 258. When the data 450 is set to “1”, the access transistor 474 of the first replica memory cell 284a is turned on, and the first replica memory cell 284a is selected.

  At this time, since a forward bias is applied to the switch element 258 of the selected memory cell 271, the impedance of the switch element 258 of the selected memory cell 271 gradually decreases.

  On the other hand, the current supplied from the pMOS current mirror circuit 456 flows into the replica memory cell 284a via the reference line 459. Since the pMOS current mirror circuit 456 flows the same current as the current flowing into the memory cell 271 from the reference line 459 to the replica memory cell 284a, the impedance of the resistance element (reference resistance) 285a is the impedance of the switching element 258 of the memory cell 271. If the impedance of the reference resistor 485 is larger than the impedance of the switching element 258 of the memory cell 271, the voltage of the reference line 459 is smaller than the voltage of the bit line 255. Becomes larger than the voltage of the bit line 255.

  For this reason, a forward bias is applied to the switch element 258 of the memory cell 271, the impedance of the switch element 258 of the memory cell 271 gradually decreases, and the impedance of the switch element 258 of the memory cell 271 is smaller than the impedance of the reference resistor 285a. When the voltage becomes lower, the output 470 of the voltage comparator 274 becomes “1”.

  Then, the output of the D-type flip-flop 471 is reset, the inverted output (/ Q) 452 becomes “1”, the normal output (Q) 466 becomes “0”, the pMOS switch 454 is turned off, and the bit line 255 is turned on. At the same time, the nMOS switch 468 is turned off, the plate line 257 is also opened, and the programming of the switch element 258 is completed.

  Conversely, when the data 450 is set to “0” and a rising edge is input to the write pulse input 451, the normal output 453 of the D-type flip-flop 472 is set to “1”, and the inverted output 467 is set to “0”. Become. Then, the nMOS switch 455 is turned on and the nMOS current mirror 457 is activated. Further, the pMOS switch 469 is turned on, and a current is supplied to the plate line 257.

  The access transistor 251 of the memory cell 271 arbitrarily selected by the word line 256 is in the on state, and the current supplied from the pMOS switch 469 via the plate line 257 accesses the switch element 258 of the selected memory cell 271. It flows to the bit line 255 via the transistor 251.

  At this time, since a reverse bias is applied to the switch element 258 of the memory cell 271, the impedance of the switch element 258 gradually increases.

  On the other hand, the selected second replica memory cell 284b (data input 450: “0” turns on the dummy access transistor 477) flows into the nMOS current mirror circuit 457 via the reference line 459. Here, the nMOS-type current mirror circuit 457 attempts to flow the same current as the current flowing through the memory cell 271 into the replica memory cell 284b. Therefore, if the impedance of the reference resistor 285b is larger than the impedance of the switch element 258, the voltage of the reference line 459 becomes smaller than the voltage of the bit line 255. Conversely, the impedance of the reference resistor 285b is larger than the impedance of the switch element 258. Is smaller, the voltage of the reference line 459 becomes larger than the voltage of the bit line 255.

  Therefore, a reverse bias is applied to the switch element 258 of the memory cell 271, and the impedance of the switch element 258 gradually increases, and when the impedance of the switch element 258 becomes higher than the impedance of the reference resistor 285b, the comparator 274 Output 470 becomes “1”. Then, the output of the D flip-flop 472 is reset, the normal output 453 is “0”, the inverted output 467 is “1”, the pMOS switch 469 is turned off, and the current supply to the plate line 257 is stopped. At the same time, the nMOS switch 455 is turned off, the bit line 255 is also opened, and the programming of the switch element 258 is completed.

  Thus, with the circuit configuration shown in FIG. 28, when the data 450 is set to “1” and the write operation is performed, the impedance of the switch element 258 is set to the impedance of the reference resistor 285a, and the data When the write operation is performed with 450 set to “0”, the impedance of the switch element 258 is set to the impedance of the reference resistor 285b.

  By using the circuit shown in FIG. 28, the switch element 258 can be accurately adjusted to an arbitrary impedance. For this reason, it is effective in writing multi-value information, reducing stress on the element due to the writing operation, and ensuring a programming operation for an element having a large variation in characteristics.

  FIG. 29 is a diagram showing an embodiment of a memory cell configuration to which the wiring structure of the present invention is applied. Referring to FIG. 29, the memory cell of the present invention includes an SRAM cell 310 having two flip-flops composed of two inverters (pMOS transistor MP1, nMOS transistor MN1, pMOS transistor MP2, nMOS transistor MN2) that are cross-connected, and two switches. Elements 311a and 311b and a control line 313 are provided. Reference numerals 317a and 317b denote access transistors, each of which has a gate connected to a word line (not shown), is turned on when the word line is at a high potential, and connects the flip-flop to a bit line pair (not shown). The switch elements 311a and 311b have a structure as shown at 103 in FIG. 1 or 118 in FIG. 2, and include an electrolyte material or a chalcogenide material inside. The on resistances of the switch elements 311a and 311b are higher than the on resistances of the pMOS transistors MP1 and MP2 constituting the two inverters.

  The circuit in FIG. 29 operates as a normal SRAM when power is supplied, and stores information as conductivity in the switch element 311 when the power is off. When the power is turned on again, the voltage levels of the nodes 314 and 315 are set due to the difference in conductivity of the switch element 311. For example, it is assumed that the terminal 314 is “H” (power supply voltage) and the terminal 315 is “L” (grounded) while the power is on. Here, by setting the control line 313 to an intermediate potential between the power supply voltage and the ground voltage, a forward bias is applied to the switch element 311a and a reverse bias is applied to the switch element 311b. When the power supply voltage is turned off in this state, the stored contents of the SRAM cell are lost, but the switch element 311a maintains a high conductivity state and the switch element 311b maintains a low conductivity state.

  When the power is turned on again, the control line 313 is set to be equal to the power supply voltage, so that the terminal 314 of the SRAM cell is connected to the power supply with high conductivity and the terminal 315 is connected to the power supply with low conductivity. Therefore, the voltage at the terminals 314 and 315 of the SRAM cell is unbalanced, and this unbalance is amplified by the cross-connection configuration of the inverter of the SRAM cell, and finally the node 314 is set to “H”. Thus, “L” is set in the node 315.

  In this manner, the memory cell of the present invention can realize an SRAM cell that retains memory even when the power is turned off and restores the original memory contents when the power is turned on again.

  Furthermore, since the switch element 311 is formed in the wiring layer, a nonvolatile memory can be realized without increasing the memory cell area with respect to a normal SRAM cell.

  FIG. 30 is a diagram showing a configuration of another embodiment of a memory cell to which the wiring structure of the present invention is applied. Referring to FIG. 30, the memory cell of the present invention includes an SRAM cell 310, two transistors 321a and 321b, two switch elements 322a and 322b, and a control line 313 for supplying a bias voltage. The switch elements 322a and 322b have the same configuration as that shown in 103 of FIG. 1 or 118 of FIG. 2, and include an electrolyte material and a chalcogenide material inside.

  The operation of the circuit of FIG. 30 is the same as the operation of the circuit shown in FIG. 29, and operates as a normal SRAM while the power is turned on. Is stored, and when the power is turned on again, the original stored contents are written back.

  However, the circuit of FIG. 30 is different from the circuit of FIG. 29 in that transistors 321a and 321b are added between the nodes 314 and 315 and the switch elements 322a and 322b, respectively.

  During normal operation, these transistors 321a and 321b can be turned off so that the switch element 322 does not affect the operation. Immediately before the power is turned off, the transistors 321a and 321b are turned on, information is written to the switch elements 322a and 322b, and when the power is turned on again, these memories are written back to the SRAM cell 310. By turning on the transistors 321a and 321b, voltage imbalance is generated in the nodes 314 and 315 due to the difference in conductivity between the switch elements 322a and 322b. This unbalance is amplified by the cross-connected flip-flops of the SRAM cells, and finally the original stored contents are set in the nodes 314 and 315. In this manner, the memory cell of the present invention can realize an SRAM cell that retains memory even when the power is turned off and restores the original memory contents when the power is turned on again.

  FIG. 31 is a diagram showing an embodiment of the wiring structure of the present invention. Referring to FIG. 31, the wiring structure of the present invention includes a horizontal wiring 480, a vertical wiring 481, and a switch element 232 disposed at the intersection of the vertical wiring and the horizontal wiring (see, for example, 232 in FIG. 19). ). The switch element 232 has a switch element formed in the wiring layer, like the switch element 103 in FIG. 1 or the switch element 118 in FIG. 2, and arbitrarily connects the wirings in four directions as shown in FIG. You can switch. An arbitrary wiring 483 can be formed by programming the switch element 232.

  FIG. 32 is a diagram showing another example of the wiring structure and the arrangement of the switch elements according to the present invention. Referring to FIG. 32, the wiring structure of the present invention has a vertical wiring 543, a horizontal wiring 544, a switching element 540 disposed at the intersection of the vertical wiring 543 and the horizontal wiring 544, and a switching element disposed in the horizontal wiring 544. 541 and a switch element 542 disposed in the vertical wiring 543. 32, switch elements 540 to 542 have the structure shown in FIG. 1 or FIG. The vertical wiring 543 and the horizontal wiring 544 may be formed in different wiring layers or in the same layer. When the vertical wiring 543 and the horizontal wiring 544 are formed in different wiring layers, the switch element 541 that connects the horizontal wirings 544 and the switch element 542 that connects the vertical wirings 543 have the structure shown in FIG. The switch element 540 that connects the vertical wiring 543 and the horizontal wiring 544 has a shape of a via that connects different wiring layers as shown in FIG.

  On the other hand, when the vertical wiring 543 and the horizontal wiring 544 are formed in the same wiring layer, the switch elements 540, 541, and 542 have the structure shown in FIG. An integrated circuit capable of programming an arbitrary wiring as shown in FIG. 31 can be configured by the layer structure as shown and the arrangement of the switch elements. In addition, the switch element between the wirings wired between the wirings of the same wiring layer may be about 1 μm to 10 mm in the first and second wiring layers. When the wiring resistances of the layers are different, the distance between the switch elements is set longer in the wiring layer having a relatively small wiring resistance than in the wiring layer having a relatively large wiring resistance. The wiring interval between the vertical wiring 543 and the horizontal wiring 544 may be about 1 μm to 10 μm, for example.

  FIG. 33 is a diagram showing the wiring structure and switch arrangement of FIG. 32, and shows a three-dimensional configuration example in which the vertical wiring 543 and the horizontal wiring 544 are formed in different layers.

  FIG. 34 is a diagram showing an example of a cross section of the wiring structure of the present invention. Referring to FIG. 34, the wiring structure of the present invention is formed in the semiconductor substrate 100, the via 126 connecting the wiring layers different from the semiconductor substrate and the wiring layer, the wiring layers 111, 112, and 550, and the wiring layer. A switch element 118 and a control gate 116 for controlling the conductivity of the switch element are provided. The switch element has the structure shown in FIG. 2, and can be arbitrarily set to the on state 118d or the off state 118c by controlling the voltage of the control gate 116.

  In general, as a wiring layer of an integrated circuit, a wiring layer close to a semiconductor substrate is used for local wiring, and an upper layer wiring is used as a global wiring for connecting larger blocks. As described above, the wiring of the integrated circuit has a hierarchical structure in which a signal propagation distance is different for each layer.

  In the wiring structure according to the present invention, the connection and release of the wiring can be arbitrarily programmed, so that the hierarchical structure of the wiring can be arbitrarily programmed. By applying this feature, an optimum circuit configuration without waste can be realized as necessary.

  FIG. 35 is a diagram showing an embodiment of a memory cell configuration using the wiring structure of the present invention. Referring to FIG. 35, the memory cell includes a first switch element 560, a second switch element 561, an input / output terminal 562, a first voltage source 563, and a second voltage source 564. Yes. The switch elements 561 and 562 are the switch elements shown in FIG. 1 or FIG. The switch elements 561 and 562 are both turned on when a negative voltage is applied to the upper terminal and a positive voltage (hereinafter referred to as “forward bias”) is applied to the lower terminal. When the voltage (referred to as “reverse bias”) is applied, the device is turned off. The voltage of the first voltage source 563 is set higher than the voltage of the second voltage source 564.

  In the circuit illustrated in FIG. 35, when a voltage higher than the voltage of the first voltage source 563 is input to the input / output terminal 562, a forward bias is applied to the switch element 560. In addition, since a reverse bias is applied to the switch element 561, the switch element 560 is turned on and the switch element 561 is turned off. When the input / output terminal 562 is opened in this state, the voltage of the first voltage source 563 appears at the input / output terminal 562. Conversely, when a voltage lower than the voltage of the second voltage source 564 is input to the input / output terminal 562, a forward bias is applied to the switch element 561. Further, since a reverse bias is applied to the switch element 560, the switch element 561 is turned on and the switch element 560 is turned off. When the input / output terminal 562 is opened in this state, the voltage of the second voltage source 564 appears at the input / output terminal 562. Further, when the power is turned off with the input / output terminal 562 open, the two switch elements can maintain the state. Assuming that the voltage of the first voltage source 563 is a voltage corresponding to the logical value “1” and the voltage of the second voltage source 564 is a voltage corresponding to the logical value “0”, this circuit Functions as a nonvolatile memory circuit.

  FIG. 36 is a diagram schematically showing a three-dimensional structure of a wiring structure in which two different wiring layers are connected using the switch element of the present invention. Referring to FIG. 36, the wiring structure of the present invention includes a first wiring layer 101, a second wiring 102, and a plurality of switch elements 103 that connect the first wiring 101 and the second wiring 102. By arranging a plurality of switch elements 103 in parallel, compared to the case of a single switch element, for example, resistance to stress (electromigration) due to current is increased, and one or more of the switch elements are destroyed. Even in such a case, the operation is possible, and the deterioration of the manufacturing yield due to the defect of the element can be improved.

[Another embodiment]
FIG. 38 is a diagram showing another embodiment of the wiring structure of the present invention. FIG. 38 shows a reconfigurable switch circuit used in an FPGA or the like. Referring to FIG. 38, the reconfigurable switch circuit turns on or off a connection between a semiconductor substrate 1100 and an electronic circuit 1120 formed on the substrate, such as a logic circuit, an arithmetic circuit, an analog circuit, and a memory circuit, and two terminals. The switch circuit 1121 that can be turned off, the contact or via 1122 for connecting the electronic circuit 1120 and the switch circuit 1121, and the wiring 1123 are included. If the switch circuit 1121 is programmed to the on state, the electronic circuits 1120a and 1120b are connected to each other, and if the switch circuit 1121 is programmed to the off state, the electronic circuits 1120a and 1120b are disconnected.

  FIG. 39 is a diagram showing a configuration example of the switch circuit 1121 in FIG. FIG. 39A shows an example in which the switch circuit 1121 is configured by an SRAM (Static Random Access Memory) 1124 and a pass transistor 1125, and FIG. 39B shows a flip-flop circuit 1128 and a pass circuit. An example in which a switch circuit 1121 is configured by a transistor 1125 is shown.

  When the switch circuit 1121 is configured by a circuit using these transistors, the switch circuit 1121 must be formed on the semiconductor substrate 1100 as shown in FIG. 38, and the switch circuit is fixed on the semiconductor substrate. Will occupy the area. In the FPGA, the switch circuit generally occupies about half the area of the semiconductor substrate, which increases the chip area and is a major cause of cost increase.

  FIG. 40 is a diagram showing a configuration of an example of a reconfigurable switch circuit according to the present invention. FIG. 40A is a switch circuit using the two-terminal element described with reference to FIG. 1, and FIG. 40B is a switch circuit using the three-terminal element described with reference to FIG. is there.

  Referring to FIG. 40A, the reconfigurable switch circuit of this embodiment includes a semiconductor substrate 1100 and electronic circuits 1120, 2 such as a logic circuit, an arithmetic circuit, an analog circuit, and a memory circuit formed on the substrate. A via 1103 having a switching function capable of changing the connection between terminals to ON or OFF, a contact 1122 for connecting the via 1103 and the electronic circuit 1120, and a wiring 1123 are included. If the via 1103 is programmed to the on state, the electronic circuits 1120a and 1120b are connected to each other, and if the via 1103 is programmed to the off state, the electronic circuits 1120a and 1120b are disconnected.

  Referring to FIG. 40B, the reconfigurable switch circuit of this embodiment includes a semiconductor substrate 1100 and an electronic circuit 1120 such as a logic circuit, an arithmetic circuit, an analog circuit, and a memory circuit formed on the substrate. , An electrolyte material 1113 containing metal ions, a gate electrode 1116 disposed so as to be in contact with the electrolyte material, a contact 1122 for connecting the electrolyte material 1113 and the electronic circuit 1120, and a wiring 1123. If a metal substance is deposited on the portion of the electrolyte material 1113 that is in contact with the wiring 1123a and the wiring 1123b, the metal precipitates are in contact with each other, and the space between the wiring 1123a and the wiring 1123b is programmed to be on. If 1120a and 1120b are connected to each other, and there is not enough metal deposit in the electrolyte material to connect the wirings 1123a and 1123b, and the circuit between the wirings 1123a and 1123b is programmed to be in an off state, the electronic circuit The connection between 1120a and 1120b is broken.

  By using the reconfigurable switch circuit of the embodiment described with reference to FIG. 40, it is possible to provide a switch function between wirings without forming a circuit on the semiconductor substrate 1100, such as an FPGA. In the programmable semiconductor integrated circuit, the chip area can be greatly reduced, and a programmable semiconductor integrated circuit can be realized at low cost.

  FIG. 41 is a diagram showing an embodiment of a circuit for programming a via (hereinafter referred to as “two-terminal switch element”) having a switching function described with reference to FIG. Referring to FIG. 41, the programming circuit of this embodiment includes a two-terminal switch element 1103, pMOS transistors 1203 and 1205, nMOS transistors 1204 and 1206, control input terminals 1207, 1208, 1209 and 1210, and voltage sources 1211 and 1212. Is done. The voltage supplied from the voltage sources 1211 and 1212 is higher than the signal voltage used for propagation of the logic signal. Since the transistors 1203, 1204, 1205, and 1206 handle a higher voltage than normal transistors that handle logic signals, it is preferable that the transistors have high withstand voltage. The two-terminal switch element 1103 has a voltage at a terminal 1201 (hereinafter referred to as “anode”) higher than a voltage at a terminal 1202 (hereinafter referred to as “cathode”) (hereinafter referred to as “forward bias” or “forward”). Programmed to the ON state when the voltage on the anode 1201 is lower than the voltage on the cathode 1202 (hereinafter referred to as “reverse bias” or “reverse bias”). Shall be.

  Here, when the terminals 1207 and 1208 are set to L (low level) and the terminals 1209 and 1210 are set to H (high level), a voltage is supplied from the voltage source 1211 to the anode 1201 of the switch element 1103, and the cathode 1202 The switch element 1103 is grounded and is in a forward bias state. Here, if the voltage supplied from the voltage source 1211 is higher than the threshold voltage of the switch element 1103, the switch element 1103 is programmed to be in an ON state. When the terminals 1207 and 1208 are set to H and the terminals 1209 and 1210 are set to L, the anode 1201 of the switch element 1103 is grounded, the cathode 1202 is supplied with voltage from the voltage source 1212, and the switch element 1103 is in a reverse bias state. become. Here, if the voltage supplied from the voltage source 1212 is higher than the threshold voltage of the switch element 1103, the switch element 1103 is programmed to the off state.

  As described above, by using the circuit shown in FIG. 41, the two-terminal switch element 1103 can be programmed to an arbitrary state of an on state or an off state.

  Conventionally, as the programmable two-terminal element, there is an antifuse. However, since the antifuse has no polarity, the bias of the programming circuit can be applied only in one direction.

  The switch element of the present invention has polarity, and it is necessary to pay attention to the polarity when programming. The switch element of the present invention can be reprogrammed, but a circuit for applying a bias voltage from both directions is required to perform reprogramming.

  The circuit shown in FIG. 41 is an essential basic circuit in order to take advantage of this switch feature of being reprogrammable.

  In addition, with an antifuse, a switch once turned on cannot be turned off, but with the switch of the present invention, it can be turned off by applying an appropriate voltage to the switch in the on state. Can do. Here, when a voltage is applied between the terminals of the switch element in order to turn off the switch element in the on state, a current flows between the terminals.

  In the switch element of the present invention, since the on-resistance is usually low, when a voltage is applied between the switch terminals, the current flowing through the switch increases. Therefore, in order to return the on-state switch element to the off-state, the transistors 1204 and 1205 in FIG. 41 need to have high current driving capability. This is also different from the antifuse programming circuit.

  FIG. 42 is a diagram showing a configuration of an embodiment of a circuit for programming a plurality of two-terminal switch elements connected in parallel. 42, the programming circuit of this embodiment includes a two-terminal switch element 1103, pMOS transistors 1203 and 1205, nMOS transistors 1204 and 1206, control input terminals 1207, 1208, 1209 and 1210, voltage sources 1211 and 1212, and a selection. A transistor 1215 and a control input terminal 1216 are provided.

  When the terminals 1207 and 1208 are set to L (low level), the terminals 1209 and 1210 are set to H (high level), the terminals 1216a and 1216c are set to L, and the terminal 1216b is set to H, the anode 1201b of the switch element 1103b is set. Is supplied with a voltage from the voltage source 1211, the cathode 1202 is grounded, and the switch element 1103b is in a forward bias state. Here, if the voltage supplied from the voltage source 1211 is higher than the threshold voltage of the switch element 1103, the switch element 1103b is programmed to be in an ON state. Since the selection transistors 1215a and 1215c are in the off state, the voltage from the voltage source 1211 is cut off, and no voltage is applied to the anode terminals 1201a and 1201c of the switch elements 1103a and 1103c, so that the switch state does not change. When the terminals 1207 and 1208 are set to H, the terminals 1209 and 1210 are set to L, the terminals 1216a and 1216c are set to L, and the terminal 1216b is set to H, the anode 1201b of the switch element 1103b is grounded, and the cathode 1202 is connected to the voltage source. A voltage is supplied from 1212, and the switch element 1103b is in a reverse bias state. Here, if the voltage supplied from the voltage source 1212 is higher than the threshold voltage of the switch element 1103, the switch element 1103 b is programmed to the off state.

  In this way, by using the circuit shown in FIG. 42, it is possible to program a plurality of two-terminal switch elements 1103a to 1103c connected in parallel to any state of an on state or an off state.

  FIG. 43 shows an embodiment of a circuit for programming the three-terminal switch element 118 described in FIG. 43, the programming circuit of this embodiment includes a three-terminal switch element 1118, pMOS transistors 1220, 1222, and 1224, nMOS transistors 1221, 1223, and 1225, and control input terminals 1226, 1227, 1228, 1229, 1230, and 1231. , Voltage sources 1232, 1233 and 1234. The three-terminal switch element 1118 has a voltage at a terminal 1116 (hereinafter referred to as “gate”) higher than a voltage at a terminal 1114 and a terminal 1115 (hereinafter referred to as “source” and “drain”) (hereinafter, referred to as “gate”). Programmed to the on state when called “forward bias” or “forward bias”), and the voltage at gate 1116 is lower than the voltage at source 1114 and drain 1115 (hereinafter “reverse bias” or “reverse bias”). Called off).

  Here, when the terminals 1230 and 1231 are set to L and the terminals 1226, 1227, 1228, and 1229 are set to H, a voltage is supplied from the voltage source 1234 to the gate 1116 of the switch element 1118, and the source 1114 and the drain 1115 are grounded. Thus, the switch element 1118 is in a forward bias state.

  Here, if the voltage supplied from voltage source 1234 is higher than the threshold voltage of switch element 1118, switch element 1118 is programmed to be in an on state. When the terminals 1230 and 1231 are set to H and the terminals 1226, 1227, 1228, and 1229 are set to L, the gate 1116 of the switch element 1118 is grounded, and the source 1114 and the drain 1115 are supplied with voltages from the voltage sources 1232 and 1233. The switch element 1118 is in a reverse bias state.

  Here, if the voltage supplied from voltage sources 1232 and 1233 is higher than the threshold voltage of switch element 1118, switch element 1118 is programmed to the off state.

  As described above, by using the circuit described with reference to FIG. 43, the three-terminal switch element 1118 can be programmed to any state of the on state or the off state.

  FIG. 44 shows a configuration of an embodiment of a circuit for programming a plurality of two-terminal switch elements 1103 connected in parallel. Referring to FIG. 44, the programming circuit of this embodiment includes two-terminal switch elements 1103a, 1103b, 1103c, 1103d, pMOS transistors 1252, 1258, nMOS transistor 1255, control input terminals 1251, 1254a, 1254b, 1254c, 1254d, 1257. , Voltage sources 1253 and 1259, and wirings 1250, 1256a, 1256b, 1256c and 1256d. Reference numeral 1201 denotes an anode terminal of the two-terminal switch element 1103, and reference numerals 1202a, 1202b, 1202c, and 1202d denote cathode terminals of the switch elements 1103a, 1103b, 1103c, and 1103d, respectively.

  Hereinafter, as an example, a case where the switch element 1103b is programmed to be in an on state will be described. In the initial state, the inputs 1251 and 1257 are at the H level, and the inputs 1254a, 1254b, 1254c, and 1254d are at the L level. When the input 1251 is set to the L level, a voltage is supplied from the voltage source 1253 to the wirings 1256a, 1256b, 1256c, and 1256d through the transistor 1252. Here, the voltage supplied from the voltage source 1253 is Vpp / 2.

  Next, the input 1251 is set to H level, and the input 1254b is set to H level. Then, the wiring 1256b is grounded through the transistor 1255b. Through the operations so far, the voltages of the wirings 1256a, 1256c, and 1256d are Vpp / 2, and the voltage of the wiring 1256b is 0 (ground potential).

  Next, when the input 1254b is returned to the L level and the input 1257 is set to the L level, the voltage of the voltage source 1259 is supplied to the anode 1201 of the two-terminal switch element 1103 through the transistor 1258. Here, when the voltage of the voltage source 1259 is Vpp, the voltage of the cathode terminals 1202a, 1202c, and 1202d of the switch elements 1103a, 1103c, and 1103d is Vpp / 2. Since Vpp / 2 and the voltage of the cathode terminal 1202b of the switch element 1103b is 0, the potential difference Vpp is applied between the two terminals of the switch element 1103b.

  Here, assuming that the threshold value of the two-terminal element is between Vpp / 2 and Vpp, switch element 1103b is programmed to be on because the potential difference between the two terminals exceeds the threshold value. Since the potential difference between the two terminals of the switch elements 1103a, 1103c, and 1103d does not exceed the threshold value, the state does not change. As described above, an arbitrarily selected switch element from a plurality of two-terminal switch elements connected in parallel can be programmed to an on state. In addition, the voltage used for propagation of the logic signal during normal operation is preferably lower than the threshold voltage of the two-terminal element 1103.

  FIG. 45 shows the configuration of an embodiment of a circuit for programming a plurality of two-terminal switch elements (hereinafter referred to as “switch matrix”) connected in parallel in a matrix in the vertical and horizontal directions. Referring to FIG. 45, the programming circuit of this embodiment includes two-terminal switch elements 1103aa, 1103ab, 1103ac, 1103ad, 1103ba, 1103bb, 1103bc, 1103bd, 1103ca, 1103cb, 1103cc, 1103cd, pMOS transistors 1252, 1258a, 1258b, 1258c, nMOS transistors 1255a, 1255b, 1255c, 1255d, control input terminals 1251, 1254a, 1254b, 1254c, 1254d, 1257a, 1257b, 1257c, voltage sources 1253, 1259, wirings 1250a, 1250b, 1250c, 1256a, 1256b, 1256c, 1256d.

  1201 is an anode terminal of the two-terminal switch element 1103, and 1202 is a cathode terminal of the switch element 1103.

  Hereinafter, as an example, a case where the switch element 1103bb is programmed to an on state will be described. In the initial state, the inputs 1251 and 1257a, 1257b, and 1257c are at the H level, and the inputs 1254a, 1254b, 1254c, and 1254d are at the L level. When the input 1251 is set to the L level, a voltage is supplied from the voltage source 1253 to the wirings 1256a, 1256b, 1256c, and 1256d through the transistor 1252. Here, when the voltage supplied from the voltage source 1253 is Vpp / 2, the voltages of the wirings 1256a, 1256b, 1256c, and 1256d are all charged up to Vpp / 2.

  Next, the input 1251 is set to H level, and the input 1254b is set to H level. Then, the wiring 1256b is grounded through the transistor 1255b. By the operation so far, the voltages of the wirings 1256a, 1256c, and 1256d are Vpp / 2, and the voltage of the wiring 1256b is 0. Next, when the input 1254b is returned to the L level and the input 1257b is set to the L level, the voltage of the voltage source 1259 is supplied to the anode 1201b of the two-terminal switch elements 1103ba, 1103bb, 1103bc, and 1103bd through the transistor 1258b. . Here, if the voltage of the voltage source 1259 is Vpp, the voltage of the cathode terminals 1202ba, 1202bc, and 1202bd of the switch elements 1103ba, 1103bc, and 1103bd is Vpp / 2. Therefore, the potential difference between the two terminals of these switch elements is Since Vpp / 2 and the voltage of the cathode terminal 1202bb of the switch element 1103bb is 0, the potential difference Vpp is applied between the two terminals of the switch element 1103bb.

  Assuming that the threshold value of the two-terminal element is between Vpp / 2 and Vpp, the switching element 1103bb is programmed to be in the on state because the potential difference between the two terminals exceeds the threshold value. Since the potential difference between the two terminals of the switch elements 1103ba, 1103bc, and 1103bd does not exceed the threshold value, the state does not change.

  Since the transistors 1258a and 1258c are not turned on, the voltages of the anode terminals 1201a and 1201c of the switch elements 1103aa, 1103ab, 1103ac, 1103ad, 1103ca, 1103cb, 1103cc, and 1103cd are 0, and the two terminals of these switch elements Since there is no potential difference of Vpp / 2 or more between them, the programming state of these switches does not change.

  As described above, an arbitrarily selected switch element from a plurality of two-terminal switch elements connected in parallel can be programmed to an on state. In addition, the voltage used for propagation of the logic signal during normal operation is preferably lower than the threshold voltage of the two-terminal element 1103.

  FIG. 46 shows a configuration of an embodiment of a circuit for turning off the connection state of the switch matrix. Referring to FIG. 46, the programming circuit of the present embodiment includes two-terminal switch elements 1103aa, 1103ab, 1103ac, 1103ad, 1103ba, 1103bb, 1103bc, 1103bd, 1103ca, 1103cb, 1103cc, 1103cd, pMOS transistor 1260, nMOS transistor 1264a, 1264b, 1264c, control input terminals 1261, 1263a, 1263b, 1263c, a voltage source 1262, wirings 1250a, 1250b, 1250c, 1256a, 1256b, 1256c, 1256d. 1201 is an anode terminal of the two-terminal switch element 1103, and 1202 is a cathode terminal of the switch element 1103.

  In the initial state, the input terminal 1261 is at the H level, and the input terminals 1263a, 1263b, and 1263c are all at the L level.

  Here, the case where the switch elements 1103ba, 1103bb, 1103bc, and 1103bd are programmed to the off state will be described. In this case, when the input terminal 1261 is set to the L level and the input terminal 1263b is set to the H level, the voltage of the voltage source 1262 is supplied to the wirings 1256a, 1256b, 1256c, and 1256d through the transistor 1260, and the switch elements 1103ba, 1103bb, The voltage of the voltage source 1262 is supplied to the cathode terminals 1202ba, 1202bb, 1202bc, and 1202bd of 1103bc and 1103bd. The anode terminal 1201b is grounded via the transistor 1264b.

  In this state, if a reverse bias is applied to the switch elements 1103ba, 1103bb, 1103bc, and 1103bd and the voltage between the two terminals exceeds the threshold voltage, the switch elements 1103ba, 1103bb, 1103bc, and 1103bd are in the off state. To be programmed.

  When all of the switch elements 1103aa, 1103ab, 1103ac, 1103ad, 1103ba, 1103bb, 1103bc, 1103bd, 1103ca, 1103cb, 1103cc, and 1103cd are programmed to be in the OFF state, the input terminal 1261 is set to the L level and the input terminal 1263a. , 1263b, 1263c are set to the H level. The wirings 1256a, 1256b, 1256c, and 1256d are supplied with the voltage of the voltage source 1262 through the transistor 1260, and the cathode terminals 1202aa, 1202ab, 1202ac, 1202ba, 1202ba, 1202bc, 1202bd, 1202ca, and 1202cb of all the switch elements 1103, The voltage of the voltage source 1262 is supplied to 1202cc and 1202cd. The anode terminals 1201a, 1201b, and 1201c are grounded through the transistors 1264a, 1264b, and 1264c. In this state, if a reverse bias is applied to all the switch elements 1103 and the voltage between the two terminals exceeds the threshold voltage, the switch elements 1103aa, 1103ab, 1103ac, 1103ad, 1103ba, 1103bb, 1103bc, 1103bd, All of 1103ca, 1103cb, 1103cc, and 1103cd are programmed to the off state.

  FIG. 47 is a diagram showing an example of the configuration of a programmable two-input logic circuit using the switch matrix of the present invention and its programming circuit. Referring to FIG. 47, the programmable logic circuit of this embodiment includes programming circuits 1270 and 1271, first wirings 1250a to 1250f, second wirings 1256a to 1256e, a selector circuit 1273, an inverter 1274, and a control signal input terminal. 1272, and a two-terminal switch element 1103 is disposed at each intersection of the wiring 1250 and the wiring 1256, and the anode terminal 1201 of the switching element 1103 is connected to any one of the first wirings 1250a to 1250f. The cathode terminal 1202 of the switch element 1103 is connected to one of the second wirings 1256a to 1256e. The programming circuits 1270 and 1271 correspond to the programming circuit and the erase circuit described with reference to FIGS.

  The selector circuit 1273 outputs the logical value of 1256a to 1256d when the logical value of 1256c is "L" (low) level, and 1256b when the logical value of 1256c is "H" (high) level. Is output to 1256d. The inverter 1274 outputs a value obtained by inverting the logical value of 1256d to 1256e.

  The circuit shown in FIG. 47 can realize an arbitrary two-input logic function by changing the connection between the wiring 1250 and the wiring 1256.

  FIG. 48 is a diagram illustrating an example of a circuit configuration in which AND, NAND, OR, NOR, XOR, and XNOR logic are realized using a selector and an inverter. For example, when the AND logic is realized, when the input A is “L” level, 0 is selected and output, so that the output is “L” level, and when the input A is “H” level, “B” is output. Therefore, the “H” level is output only when both A and B are at the “H” level. Further, by changing the value input to each input terminal of the selector 1273, OR logic, XOR logic, or the like can be configured.

  In the circuit of FIG. 48, for example, it is assumed that a logical value A is given to the wiring 1250a and a logical value B is given to the wiring 1250b, and that 1250c is always at the “L” level (logical value 0). Here, the programming circuits 1270 and 1271 are used to connect the wiring 1250a and the wiring 1256c, the wiring 1250b and the wiring 1256b, the wiring 1250c and the wiring 1256a, the wiring 1256d and the wiring 1250d, and the wiring 1256e and the wiring 1250e, respectively. When the terminal switch element 1103 is programmed, the “H” level appears in the wiring 1256d only when the logical values A and B are both “H” level. In this way, AND logic is realized.

  Similarly, a logical value of A is given to the wiring 1250a and a logical value of B is given to the wiring 1250b, and it is assumed that 1250f is always at the “H” level (logical value 1), and the wirings 1250a, 1256c, and 1250f are assumed. When the two-terminal switch element 1103 is programmed so that the wiring 1256a, the wiring 1250c and the wiring 1256b, the wiring 1256d and the wiring 1250d, and the wiring 1256e and the wiring 1250e are connected to each other, at least one of the logical value A and the logical value B "H" level appears in the wiring 1256d. In this way, OR logic is realized.

  As described above, by using the two-terminal switch matrix of the present invention and its programming circuit, a programmable logic circuit that can realize an arbitrary two-input logic function is configured.

  In the circuit shown in FIG. 47, the selector 1273 and the inverter 1274 use a three-state circuit capable of setting the output to high impedance, and when the switch matrix is programmed, the selector 1273 and the inverter 1274 are selected by the input signal from the control input 1272. It is desirable that the outputs of 1273 and the inverter 1274 have high impedance so that the outputs of these circuits do not affect the signal levels of the wirings 1256d and 1256e.

  FIG. 49 is a diagram showing a configuration of an embodiment of a field programmable logic circuit in which a two-terminal switch matrix according to the present invention and a programmable logic circuit to which the two-terminal switch matrix is applied are combined. Referring to FIG. 49, the field programmable logic circuit of this embodiment includes a plurality of programmable logic circuits 1281 having a selector 1273 and an inverter 1274, a vertical wiring 1256, a horizontal wiring 1250, and a two-terminal switch element 1103. A switch matrix 1283 and a two-terminal switch element 1103 that can be arbitrarily programmed to turn on or off each intersection of the vertical wiring 1256 and the horizontal wiring 1250, and can be programmed with the horizontal wiring 1250 The switch matrix 1284 that can be arbitrarily programmed to connect each terminal of the logic circuit 1281 to the on state or the off state, the horizontal wiring, the vertical wiring 1256, or the horizontal wiring 1250 are connected to each other. A switch that can be programmed to any of the states Circuit 1282, consists of.

  In the switch matrices 1283 and 1284, two-terminal switch elements 1103 are arranged at the intersections of the vertical wiring and the horizontal wiring, and the two terminals of the switch elements are connected to the vertical wiring and the horizontal wiring, respectively. Has a structured.

  The switch 1282 has a structure in which the switch element 1103 is connected in parallel with the source and drain terminals of the pass transistor 1280.

  An arbitrary logic function is programmed in each of the plurality of programmable logic circuits 1281, and the connection state of the switch matrices 1283 and 1284 and the switch 1285 is changed to interconnect the plurality of programmable logic circuits 1281. By arbitrarily programming, a logic circuit having a complicated logic function can be configured.

  FIG. 50 is a diagram for explaining a programming circuit of the switch matrix 1283 and the switch circuit 1285 of the field programmable logic circuit shown in FIG.

  Referring to FIG. 50, the programming circuit of the field programmable logic circuit of this embodiment includes a switch matrix 1283, a switch circuit 1285, a vertical wiring 1256, a horizontal wiring 1250, pMOS transistors 1290, 1292, 1294, and an nMOS transistor 1291. , 1293, 1295, control signal input terminals 1296a, 1296b, 1296c, and a voltage source 1297. Voltage source 1297 supplies a voltage Vpp higher than the threshold voltage of switch element 1103.

  Here, consider a case where the switch element 1103a in the switch matrix 1283 is programmed to the ON state. The transistors 1290 and 1295 are turned on, the transistors 1291, 1292, 1293, and 1294 are turned off. The vertical wirings 1256a, 1256c, 1256x, and 1256y, and the horizontal wirings 1250a and 1250c are supplied from the voltage source 1297. A voltage Vpp / 2 that is half of the supplied voltage Vpp is applied.

  Further, the control signal inputs 1296a, 1296b, and 1296c are all set to the “H” level, and the transistors 1280 are all turned on. Then, the voltage Vpp is supplied from the horizontal wiring 1250b to the anode terminal of the switching element 1103a, and the cathode terminal of the switching element 1103b is grounded through the vertical wiring 1256b.

  Here, since the voltage Vpp exceeding the threshold is applied between the two terminals of the switch element 1103a, the switch element 1103a is programmed to the ON state. Since the voltage of Vpp / 2 is applied to at least one terminal of the other switch elements, the potential difference between the two terminals is Vpp / 2 or less, and the connection state of the switch does not change.

  In this way, any switch element in the switch matrix 1283 can be programmed.

  In order to program (erase) all switch elements in the switch matrix 1283 in an off state, Vpp is applied to all the vertical wirings 1256, all the horizontal wirings are grounded, and all the transistors 1280 are turned on. The control signal inputs 1296a, 1296b and 1296c are all set to the “H” level so that

  Then, Vpp is applied to the cathode side of the switch element 1103 via the vertical wiring 1256, and the anode side of the switch element is grounded via the transistor 1280. For this reason, the programming state of the switch element 1103 is erased and set to the off state.

  Next, consider the case where the switch element 1103b in the switch 1285 is programmed. Transistors 1290 and 1293 are turned on, transistors 1291, 1292, 1294, and 1295 are all turned off, vertical wirings 1256 are all set to a potential of Vpp / 2, and control input signals 1296a and 1296c are set to the “H” level. The control input signal 1296b is set to the “L” level.

  Then, the voltage Vpp is supplied to one terminal of the switch element 1103b through the transistor 1290, and the other terminal of the switch element 1103b is grounded through the transistor 1293. Since the other switch elements connected in series with the switch element 1103b are in the on state, the transistors 1280a and 1280c connected in parallel with these switch elements are not applied with voltage.

  In addition, regarding the switch element connected to the intersection of the horizontal wiring 1250 and the vertical wiring 1256, a voltage of Vpp / 2 is applied to the vertical wiring 1256, and therefore, between the two terminals of the switch element. The potential difference is Vpp / 2 or less, and the programming state of the switch elements at these intersections does not change.

  In this way, the programming state of the switch element 1103b arbitrarily selected from the switches 1285 can be changed.

  FIG. 51 is a diagram showing an example of a circuit for verifying the state of programming of the switch matrix according to the present invention. Referring to FIG. 51, the verification circuit of this embodiment includes a two-terminal switch element 1103, a vertical wiring 1256, a horizontal wiring 1250, nMOS transistors 1255 and 1306, pMOS transistors 1301, 1303 and 1305, an input terminal 1254, 1300, 1302, and 1304, and an output terminal 1307. By using this verification circuit, it is possible to verify in line units whether all the switches that should be programmed to the ON state are in the ON state.

  For example, assume that switch elements 1103aa and 1103ac are programmed to an on state. In order to confirm this, an “L” level pulse is applied to the input terminal 1300 and all the vertical wirings 1256 are precharged through the transistor 1301. Next, a programming pattern to be verified is input (1254). For example, since 1103aa and 1103ac are programmed to be in the ON state here, the input 1254a and input 1254c corresponding to those columns are set to “H” level, and the other inputs 1254b and 1254d are set to “L” level.

  Then, the vertical wirings 1256a and 1256c are grounded through the transistors 1254a and 1254c, and the potential becomes zero. Next, when an “L” level pulse is applied to the input 1302, the output 1307 is precharged via the transistor 1303. Here, 1256b and 1256d remain precharged to "H" level, but 1256a and 1256c have zero potential, so that transistors 1306a and 1306c are off and output 1307 remains precharged. Keep.

  Next, when all the inputs 1254 are returned to the “L” level and the input 1304a is set to the “L” level, the wiring 1250a is set to the “H” level through the transistor 1305a. Here, if switch elements 1103aa and 1103ac are programmed to be in an ON state, wirings 1256a and 1256c are set to “H” level through these switch elements.

  Then, the transistors 1306a to 1306d are all turned on, the output 1307 is grounded, and becomes “L” level. If the switching element 1103aa or 1103ac is not normally programmed and remains off, the wiring 1256a or the wiring 1256c remains at the “L” level, and the transistor 1306a or 1306c remains off.

  Then, the output 1307 remains at the “H” level, and it can be detected that the switch that should have been programmed to the on state is in the off state. Here, the signal voltage used for these operations is preferably lower than the threshold voltage of the two-terminal element 1103.

  FIG. 52 is a diagram showing a configuration of an embodiment of a circuit for verifying the state of programming of the switch matrix. Referring to FIG. 52, the verification circuit of this embodiment includes a two-terminal switch element 1103, a vertical wiring 1256, a horizontal wiring 1250, nMOS transistors 1255 and 1312, pMOS transistors 1301, 1305, and 1311, an input terminal 1254, 1300, 1304, 1310 and an output terminal 1313. By using this verification circuit, it is possible to verify whether all the switches that should be programmed to the OFF state are in the OFF state. For example, assume that switch elements 1103aa and 1103ac are programmed to an on state and switch elements 1103ab and 1103ad are programmed to an off state. In order to confirm this, an H level pulse is applied to the input terminals 1254a to 1254d, all the vertical wirings 1256 are grounded, and all the potentials of the wirings 1256 are set to the "L" level.

  After that, an “L” level pulse is applied to the input terminal 1304a, and the horizontal wiring 1250a is precharged to the H level through the transistor 1305a. Here, since the switch elements 1103aa and 1103ac are in the ON state, the vertical wirings 1256a and 1256c are set to the “H” level. Next, a programming pattern to be verified is input (1254). For example, since 1103aa and 1103ac are programmed to be in the ON state here, the inputs 1254a and 1254c corresponding to those columns are set to “H” level, and the other inputs 1254b and 1254d are set to “L” level. Then, the vertical wirings 1256a and 1256c are grounded through the transistors 1254a and 1254c, and the potential becomes zero.

  Next, when an “L” level pulse is applied to the input 1310, the output 1313 is precharged via the transistor 1311. Here, 1256b and 1256d remain at the “L” level from when the wiring 1256 is first grounded, and 1256a and 1256c are precharged to the “H” level via the transistor 1305a and the switch elements 1103aa and 1103ac. Since it is grounded through the transistor 1255 by the input pattern given from the input terminal 1254, it is at the “L” level. Accordingly, the transistors 1312a to 1312d are all off, and the output 1313 is kept at the “H” level while being precharged.

  If the switch element 1103ab or 1103ad is not normally programmed and is in an ON state, when the “L” level pulse is applied to the input terminal 1304a, the wiring 1256b or the wiring 1256b is connected together with the wirings 1256a and 1256c. Even when the pattern 1256d is set to the “H” level and the pattern is applied from the input terminal 1254, the wiring 1256b or the wiring 1256d that is set to the “H” level remains at the “H” level.

  Then, the output 1313 is grounded via the transistor 1312b or 1312d, and outputs an “L” level. In this way, it can be detected that the switch that should have been programmed to the off state is in the on state. Here, the signal voltage used for these operations is preferably lower than the threshold voltage of the two-terminal element 1103.

  FIG. 53 is a diagram showing a configuration of an embodiment of a circuit for verifying that some or all of the switch elements of the switch matrix are in the OFF state. Referring to FIG. 53, the verification circuit of this embodiment includes a two-terminal switch element 1103, a vertical wiring 1256, a horizontal wiring 1250, nMOS transistors 1306 and 1321, pMOS transistors 1301 and 1303, and control input terminals 1300 and 1302. 1320 and an output terminal 1307. By using this verification circuit, it is possible to verify on a row basis or the entire switch matrix whether there are any switches in the on state among the switches that should be programmed to the off state. In order to perform this verification, an “L” level pulse is applied to the input terminal 1300, and all the vertical wirings 1256 are precharged to the “H” level through the transistor 1301.

  Next, the transistor 1321 of the row to be verified is turned on. For example, when verifying two rows at a time, the input terminals 1320a and 1320b are set to the “H” level, and the horizontal wirings 1250a and 1250b are grounded via the transistors 1321a and 1321b.

  Here, if one of the switch elements 1103 is in an on state, the wiring 1256 precharged to the “H” level is grounded via the switch element in the on state, the wiring 1250, and the transistor 1321. L ”level.

  Next, when an “L” level pulse is input to the input terminal 1302, the output 1307 is precharged to the “H” level via the transistor 1303. Here, if all the switch elements 1103 are off, the vertical wirings 1256 are all kept at the “H” level, so that the output 1307 is grounded via the transistor 1306 and outputs the “L” level. If some of the switch elements 1103 are in the on state, some of the vertical wirings are at the “L” level, so that the transistor 1306 in that column is in the off state, and the output 1307 is not grounded. Keep H ”level.

  In this way, it is possible to verify whether or not there is an on-state switch element in the switch matrix. Here, the signal voltage used for these operations is preferably lower than the threshold voltage of the two-terminal element 1103.

  54 is a diagram showing a configuration of an embodiment of a circuit for verifying connection in the field programmable logic circuit described with reference to FIGS. 49 and 50 in a structure in which a plurality of switch circuits 1282 are connected in series. It is. Referring to FIG. 54, the verification circuit of this embodiment includes a plurality of two-terminal switch elements 1103 connected in series, a transistor 1280 having a source terminal and a drain terminal connected in parallel to the switch elements, and a gate of the transistor A control input terminal 1296 connected to the terminals, a pMOS transistor 1325, an nMOS transistor 1327, control input terminals 1324 and 1326, and output terminals 1328 and 1329 are provided.

  Here, a case is considered in which it is verified whether the connection of the switch element 1103a is in an on state or an off state. The input signal 1296a is set to “L” level, and 1296b is set to “H” level. Next, an “L” level pulse is added to the input signal 1324. Then, the output signal 1328 is precharged. Next, when the input signal 1326 is set to the “H” level, the output signal 1329 is grounded. Here, if the switch element 1103a is in an on state, the charge precharged to the input signal 1328 is grounded through the transistor 1280b, the switch element 1103a, and the transistor 1327, so that the output 1328 outputs an “L” level. The

  On the other hand, if the switch element 1103a is in the off state, the precharged electric charge is held in the output terminal 1328, so that the “H” level is output. At this time, the switch element 1103b other than the switch element 1103a to be verified is turned on between the two terminals by the transistor 1280b connected in parallel with the switch element 1103b, whether the switch element 1103b is on or off. Therefore, the verification of 1103a is not affected.

  According to the procedure described above, it is possible to check the connection state of an arbitrary switch element from a plurality of two-terminal switch elements connected in series. In this verification, an “H” level pulse is first applied to the input terminal 1326 to set the output 1329 to the “L” level, and then an “L” level pulse is applied to the input terminal 1324 to Similar results can be obtained by the method of determining the level. Here, the signal voltage used for these operations is preferably lower than the threshold voltage of the two-terminal element 1103.

  FIG. 55 is a flowchart showing a programming procedure of the two-terminal switch element 1103 using the write / erase circuit and the verification circuit described above. Referring to FIG. 55, the programming procedure of the two-terminal switch element includes the following steps.

  Some or all of the plurality of switch elements are programmed to the off state (step 1330).

  It is verified whether all the switches programmed to the off state are in the off state (step 1331).

  The result is discriminated (step 1332). If there is an ON switch here, the procedure starting from step 1330 is repeated. On the other hand, if all the switches are off, the selected switch element is programmed to the on state (step 1333).

  It is verified (verified) whether or not the selected switch element is on (step 1334).

  The result is discriminated (step 1335). If there is any switch element that remains off, the procedure starting from step 1333 is repeated. Conversely, if all the switch elements that have been programmed to the on state are programmed to the on state, the programming is terminated.

  Step 1330 for programming all switches to the OFF state can be realized by using the circuit of FIG.

  The circuit shown in FIG. 53 can be used in step 1332 to verify whether all the switches programmed to the off state are in the off state (step 1331) and determine the result.

  The circuit shown in FIG. 45 can be used in step 1333 for programming the switch element to the ON state.

  The circuit shown in FIGS. 51 and 52 can be used in step 1335 for verifying whether the selected switch element is in the on state (step 1334) and determining the result.

  By the procedure described above, a desired connection can be reliably programmed in a circuit in which a plurality of switch elements 1103 are connected.

  FIG. 56 is a diagram showing a configuration of an embodiment of a programmable input / output (I / O) circuit using a switch matrix according to the present invention. Referring to FIG. 56, in the I / O circuit of this embodiment, one wiring is arranged at each intersection of vertical wiring 1256, horizontal wiring 1250, wiring 1256 and wiring 1250, and one terminal is wiring 1256. In addition, a two-terminal switch element 1103 having the other terminal connected to the wiring 1250, a three-state buffer 1340 capable of setting the output to three states of “H” level, “L” level, and high impedance, and two inverters 1341 , 1342 and an input / output terminal 1343. For example, when the “H” level is input from the wiring 1256a, the 3-state buffer 1340 outputs the value input from the wiring 1256b to the input / output terminal 1343, and when the “L” level is input from the wiring 1256a. The output is assumed to be high impedance.

  Considering the case where the value of the wiring 1250a in the LSI is output to the outside through the input / output terminal 1343 using this I / O circuit as an output buffer, the wiring 1256a and the wiring 1250b, The switching element at the intersection of the wiring 1256a and the wiring 1250b and the switching element at the intersection of the wiring 1256b and the wiring 1250a are programmed to be in an ON state so that the 1256b and the wiring 1250a are connected to each other. All other switch elements are programmed to the off state. Here, when the signal of “H” level is always supplied to the wiring 1250 b, the three-state buffer 1340 outputs the signal of the wiring 1250 a propagated through the wiring 1256 b to the input / output terminal 1343.

  In addition, when this I / O circuit is used as an input buffer, a value of a signal input from the outside of the LSI to the input / output terminal 1343 is input to the wiring 1250d inside the LSI, and a value obtained by inverting the value is input to the wiring 1250e. Considering, as an example of switch connection, the switch element at the intersection of the wiring 1256a and the wiring 1250b, and the wiring 1256c so that the wiring 1256a and the wiring 1250b, the wiring 1256c and the wiring 1250d, and the wiring 1256d and the wiring 1250e are connected, respectively. And the switch element at the intersection of the wiring 1250d and the switch element at the intersection of the wiring 1256d and the wiring 1250e are programmed to the ON state. All other switch elements are programmed to the off state. Here, if the signal of “L” level is always supplied to the wiring 1250b, the output of the three-state buffer 1340 is in a high impedance state, so that the value of the wiring 1256b affects the input / output terminal 1343. There is no.

  A value input from the input / output terminal 1343 is propagated through the inverters 1341 and 1342 and the wiring 1256c and output to the wiring 1250d. A value obtained by inverting the value input from the input / output terminal 1343 is propagated through the inverter 1341 and the wiring 1256d and output to the wiring 1250e. As described in the above example, by changing the switch matrix connection, it can be used for both input and output, and signals from any wiring in the chip can be input to the outside, or signals input from the outside can be It is possible to realize an I / O circuit that can output to any of the wirings.

  FIG. 57 is a diagram showing a configuration of an example of a switch matrix using the three-terminal switch element described in FIG. Referring to FIG. 57, the switch matrix of this embodiment includes a vertical wiring 1400, a vertical program control line 1401, a horizontal program control line 1402, a horizontal wiring 1403, a switch element 1118, and the like. , And an inverter 1404.

  The switch element 1118 is arranged at each intersection of the vertical wiring 1400 and the horizontal wiring 1403, and the source terminal or the drain terminal is connected to the wiring 1400 or the wiring 1403, respectively. The gate terminal is connected to the output terminal of the inverter 1404. A vertical program control line 1401 is connected to the gate input terminal of the inverter, and a horizontal program control line 1402 is connected to the power input of the inverter. As shown in FIG. 57B, the inverter 1404 includes an input terminal 1405, an output terminal 1406, a power input 1407, a pMOS transistor 1408, and an nMOS transistor 1409, and an “H” level is input to the input terminal 1405. Then, the output terminal 1406 outputs 0 volt. When the “L” level is input to the input terminal 1405, the output terminal 1406 outputs the voltage applied to the power input 1407.

  In the circuit shown in FIG. 57, the case where the switch element 1118a is programmed to be in an on state and the wiring 1400a and the wiring 1403a are connected will be described below. The vertical wiring 1400 and the horizontal wiring 1403 are all grounded, and the potentials of the source terminal and the drain terminal of the three-terminal switch element 1118 are all zero (ground potential).

  Next, the vertical program control line 1401b is set to "H" level, 1401a is set to "L" level, 0 volt is applied to the horizontal program control line 1402b, and voltage Vpp is applied to 1402a. Here, the voltage Vpp is a voltage larger than the threshold value of the three-terminal switch element. Then, inverter 1404a outputs Vpp, and 1404b outputs 0 volts. Therefore, the voltage Vpp is applied only to the gate of the switch element 1118a, and the source terminal and the drain terminal of the 1118a are programmed to be in an on state.

  When all the switch elements 1118 are programmed to be in the OFF state, the voltage Vpp is applied to all the vertical wirings 1400 and all the horizontal wirings 1403, and all the vertical program control lines 1401 are set to “H”. By setting the level or setting the lateral program control lines 1402 to all 0 volts, the voltage Vpp is applied to all the source terminals and drain terminals, and the voltages of all the gate terminals become 0 volts. Thus, all switch elements 1118 are programmed to the off state.

  As described above, the switch matrix using the three-terminal elements according to the present invention can collectively erase and selectively program the three-terminal switch elements.

  In addition, since the switch matrix using the three-terminal switch element described above can be realized simply by arranging two transistors and a three-terminal switch element at each intersection of wiring, the conventional switch as shown in FIG. Compared with the configuration in which the circuit is arranged at each intersection of the wiring, the circuit area can be reduced to a fraction.

  FIG. 58 is a diagram showing a configuration of an embodiment of a switch matrix that can be configured without using a transistor according to the present invention. Referring to FIG. 58, the switch matrix of this embodiment includes a vertical wiring 1400, a horizontal wiring 1403, a program control line 1402, and a switch element 1118.

  The switch element 1118 is arranged at each intersection of the vertical wiring 1400 and the horizontal wiring 1403, and the source terminal or the drain terminal is connected to the wiring 1400 or the wiring 1403, respectively. The gate terminal is connected to the program control line 1402. Further, the program control lines 1402 may be connected to a portion indicated by a broken line in the drawing.

  According to the switch matrix of this embodiment, the intersection between one of the wirings 1400 and one of the wirings 1402 is the same as there is only one intersection between one of the wirings 1400 and one of the wirings 1403. There is only one point, and there is only one point of intersection between one of the wirings 1403 and one of the wirings 1402. That is, the wiring 1402 has a structure that is not connected to gate terminals of two or more switches in the same row or column of the switch matrix. For example, if the switch element of the switch matrix of m columns × n rows is Sx, y (x <m, y <n), one of the wirings 1402 is Sn, n (n = 1, 2, 3,. ) And the other one of the wirings 1402 is connected to Sn + 1, n.

  The circuit shown in FIG. 58 also satisfies this condition. Further, in the circuit shown in FIG. 58, program control is performed by connecting 1402b and 1402g, 1402c and 1402f, and 1402d and 1402e, respectively, as indicated by broken lines. This condition is satisfied even when the number of lines is four.

  Consider the case where the switch element 1118a is programmed to the on state in the switch matrix of FIG. 58 and the wirings 1400a and 1403a are connected. The wiring 1400a and the wiring 1400b connected to the source terminal and the drain terminal of the switch element 1118a are grounded, and the voltage Vpp is applied to the program control line 1402a connected to the gate terminal of the switch element 1118a. In addition, wirings 1400b, 1403b, and 1402b that are not connected to any terminal of the switch element 1118a are set to a voltage of Vpp / 2. Here, voltage Vpp exceeds the threshold voltage of switch element 1118, and half of the voltage Vpp / 2 does not exceed the threshold voltage.

  Under such conditions, the source terminal and the drain terminal of the switch element 1118a are applied with 0 volt, and Vpp is applied to the gate terminal. Therefore, the potential difference between the gate and the channel is Vpp, and the switch element 1118a is programmed to the on state. The Since the voltage of Vpp / 2 is applied to the source terminal and drain terminal of the other switch elements connected to the program control line 1402a, the potential difference from the gate is Vpp / 2, and the programming state is It does not change. In other switch elements, the gate terminal voltage is Vpp / 2 and the source terminal and drain terminal voltages are 0 to Vpp / 2. Therefore, the potential difference is 0 to Vpp / 2, and the programming state changes. do not do.

  In order to selectively program the switch element 1118a in the on state to the off state, the wirings 1400a and 1403a are set to Vpp, the program control line 1402a is set to 0 volt, and the other terminals are set to Vpp / 2. realizable. In this way, one arbitrarily selected switch element can be programmed to an on state or an off state.

  When all the switch elements are programmed to be in the OFF state, the voltage Vpp is applied to all of the wirings 1400 and all of the wirings 1403, and all the program control lines 1402 are grounded. In this case, since the voltage Vpp is applied to the source terminal and the drain terminal of all the switch elements and all the gate terminals are 0 volts, a voltage of −Vpp is applied between the gate and the channel. Programmed to the off state.

  As described above, in the switch matrix configured without using the transistors shown in FIG. 58, the switch elements can be erased collectively and selectively programmed.

  The switch matrix that does not use a transistor according to the present invention does not require an SRAM or FF compared to a conventional SRAM or FF combined with a path and a runges. Therefore, it can be configured by simply arranging the three-terminal switch elements in the wiring layer, and the circuit area can be further reduced. In addition, since transistors can be freely arranged under the wiring layer that constitutes the switch matrix, it becomes possible to arrange another transistor circuit and the switch matrix in three dimensions, thereby dramatically improving the area efficiency of the LSI. be able to.

  FIG. 59 is a diagram illustrating a configuration of a nonpolar switch using the switch element 1118. Referring to FIG. 59, this switch has two two-terminal switch elements 1118a and 1118b connected in parallel so that their polarities are opposite to each other, and has a symmetrical structure between terminal 1410 and terminal 1411. It has become. For example, when a voltage Vpp exceeding the threshold voltage is applied to this element from the terminal 1410 side and 0 volt (ground potential) is applied from the terminal 1411 side, a forward bias is applied to the switch element 1103a. Is programmed to be on. Even if the voltages applied to the terminals 1410 and 1411 are switched, a forward bias is applied to the switching element 1103b, so that the terminal 1410 and the terminal 1411 are programmed to be in an ON state.

  In this way, it is possible to configure a nonpolar switch that can be programmed to be turned on regardless of the voltage applied from either terminal. Since this element basically operates in the same manner as an antifuse, it can be applied to an existing antifuse circuit.

  FIGS. 60A, 60B, and 60C show a circuit configuration, a layout diagram, and a cross-sectional view of an embodiment of a memory cell array using the two-terminal switch element 1103. FIG. Referring to FIG. 60, the memory cell array of the present invention includes a two-terminal switch element 1103, a word line 1500, a bit line 1501, a plate line 1502, a wiring or via 1503, and a transistor 1504.

  The transistor 1504 has a gate terminal connected to the word line 1500, and a source terminal and a drain terminal connected to the anode terminal and the cathode terminal of the switch element 1118.

  A plurality of memory cells in which the switch element and the transistor are connected in parallel are connected in series. A plurality of transistors 1504 connected in series share a source and a drain between adjacent transistors. A plurality of memory cells connected in series are arranged in parallel, and a word line is shared between them.

  An example of programming an arbitrarily selected memory cell in this memory cell array will be described with reference to FIG. As an example, when programming the switch element 1103ba, the word line 1500b to which the memory cell to be programmed is connected is set to “L” level, and the other word lines 1500a, 1500c, 1500d are all set to “H”. To level.

  Further, the word line 1509a is set to the “H” level in order to connect the memory cell column to be programmed with the bit line and the plate line. Since the memory cells 1103ab to 1103dn are not programmed, the word lines 1509b to 1509n are all set to the “L” level.

  Under such conditions, the voltages of the bit line 1516 and the plate line 1517 are switched via the transistors 1504aa, 1504ca, and 1504da, respectively, regardless of whether the switch elements 1103aa, 1103ca, and 1103da are in the on state or the off state. It is transmitted to both terminals of the element 1103ba.

  In addition, since the transistor 1504ba connected in parallel with the switch element 1103ba is in an off state, no current flows, and the voltage of the bit line 1516 and the voltage of the plate line 1517 are applied between the two terminals of the anode and the cathode of the switch element 1103ba. Is done. Here, signals are applied to the input terminals 1505, 1506, 1507, and 1508, and the voltages of the bit line 1516 and the plate line 1517 are controlled by appropriately setting the transistors 1512, 1513, 1514, and 1515 to an on state or an off state, A forward bias or a reverse bias can be applied to the switch element 1103ba. Further, the switch elements 1103aa, 1103ca, and 1103da do not generate a potential difference sufficient for rewriting between the two terminals because the transistors 1504aa, 1504ca, and 1504da connected in parallel are turned on.

  In addition, the switch elements 1103ab, 1103bb, 1103cb, 1103db, 1103an, 1103bn, 1103cn, and 1103dn are disconnected from the bit line 1516 and the plate line 1517 by the transistors 1510b, 1510n, 1511b, and 1511n. The voltage of the plate line 1517 is not applied to the switch element, and the program state does not change. In this way, the programming state of one arbitrarily selected switch element can be changed.

  The memory cell structure of the present invention reduces the memory cell area as compared with a configuration in which a transistor and a switch element are connected in series as described in a patent document (claim 12 of US Pat. No. 6,487,106). There is an advantage that the storage capacity per unit area of the chip can be increased.

  FIG. 62 is a diagram showing a configuration obtained by improving the memory cell array using the two-terminal switch element shown in FIG. 60. FIGS. 62 (a), (b), and (c) show the circuit configuration, layout, and cross section. The configuration is shown. The two-terminal switch element 1103 has a structure in which the directions of the anode and the cathode are alternately reversed. That is, the adjacent two-terminal switch element 1103 has a structure in which anodes and cathodes are connected to each other.

  In the memory cell array of FIG. 60, a normal metal wiring via 1503V and a switching element 1103 in the shape of a via are arranged one by one in one memory cell, and the via diameter and spacing are limited. Therefore, it becomes difficult to reduce the cell area.

  On the other hand, in the structure of the memory cell array shown in FIG. 62, the via 1503V of the metal wiring is shared by two memory cells, so that one memory cell includes ½ via 1503V. And one switch element 1103 is arranged. Thus, by reducing the number of vias 1503V, the cell interval can be narrowed, and the storage capacity per unit area of the chip can be further increased as compared with the configuration shown in FIG.

  However, the switch elements 1103 vertically connected in series are odd-numbered and even-numbered, and the polarities are inverted. For this reason, in the odd-numbered memory cells and the even-numbered memory cells, the bias direction at the time of programming is reversed, or the assignment of the logical values “0” and “1” to the on state and the off state at the time of reading is reversed. These functions are preferably realized by a writing circuit or a reading circuit.

  FIG. 63 shows a layout diagram (FIG. 63A) and a cross-sectional view (FIG. 63B) of one embodiment of a memory cell array using the two-terminal switch element 1103. Referring to FIG. 63, in this memory cell array, a vertical wiring 1523 is formed of a metal wiring, and a horizontal wiring is formed of an N well 1521. The N well 1521 is connected to the wiring 1522 through the N + diffusion layer 1524. A two-terminal switch element 1103 is disposed at each intersection of the wiring 1523 and the N well 1521. Since the switch element 1103 and the N well 1521 are connected via the P + diffusion layer 1525, the switch element 1103 and the N well 1521 are connected to each other. A diode is connected in series between the wells 1521.

  The anode terminal of the two-terminal element 1103 is connected to the P + diffusion layer 1525 and the cathode terminal is connected to the wiring 1523. Since this memory cell array does not require an access transistor for reading and writing, the cell area can be made smaller than that of the conventional configuration.

  FIG. 64 is a circuit diagram (equivalent circuit) showing the layout configuration of FIG. 63A in order to explain reading and writing of the memory cell described with reference to FIG. In FIG. 64, the junction between the N well 1521 and the P + diffusion layer 1525 is described as a diode 1530. The diode 1530 is connected in series with the switch element 1103, and the anode terminal of the diode 1530 and the anode terminal of the switch element 1103 are connected to each other.

  Further, the threshold value of switch element 1103 is assumed to be 0.7 V or more lower than voltage Vpp, and it is assumed that the ON state is erased and the OFF state is write. In the initial state, it is assumed that the voltage of the anode terminal of all the diodes is about 0 to 0.7 volts.

  First, the case of erasing all bits will be described below. Here, all of the wirings 1522 are grounded, and −Vpp, which is a lower voltage than the state of grounding all of the wirings 1523, is applied. Then, since the voltage of about 0 to 0.7 volts is applied to the anode of the switch element 1103 and −Vpp is applied to the cathode, the switch element 1103 is in the forward bias state, and all the switch elements 1103 are in the on state. become. Here, since the diode 1530 is provided, no current flows from the wiring 1522 to the wiring 1523 even when the switch is turned on. In this way, all switch elements are erased. When all the switches are turned on, all the wirings 1523 are grounded.

  Next, a case where the selected bit is written will be described. As an example, when the switch element 1103ba is written in the ON state, a positive voltage Vpp is applied to the wiring 1523a, and 1523b, 1523c, and 1523d are grounded. Further, the wiring 1522b is grounded, and a positive voltage (for example, Vpp or Vpp / 2) is applied to 1522a and 1522c.

  Then, a positive voltage (Vpp) is applied from the wiring 1523a to the cathode terminal of the switching element 1103ba, and the anode terminal is grounded via the diode 1530ba and the wiring 1522b, so that the switching element 1103ba is in a reverse bias state. Written in the off state. When written off, the potential on the anode side of the switch element 1103ba converges to a voltage of about 0 to 0.7 volts via the diode 1530ba. Since voltage is applied to the anode and the cathode to the switch elements 1103aa and 1103ca via the wirings 1522a and 1522c, respectively, as long as the potential difference between the anode and cathode terminals does not exceed the threshold voltage. , Not written off state. In addition, since the wirings 1523b, 1523c, and 1523d are grounded, no reverse bias is applied to the switch elements connected thereto, and writing is not performed.

  In addition, since the diode cuts off the voltage from the wirings 1522a and 1522c, no forward bias is applied to the switch element 1103, so that the memory contents of the two-terminal element programmed to the off state are not destroyed.

  In the case of reading data from the wiring 1523ba (switching element 1103ba), the potential of the wiring 1522b is set to be 0.7 V or more lower than the potential of the wiring 1523a. The potentials of the wirings 1522a and 1522c are equal to or higher than the potential of the wiring 1523a, and the potentials of the wirings 1523b, 1523c, and 1523d are set to be equal to or lower than the potential of the wiring 1522b.

  Then, since only the diode 1530ba is in a forward bias condition, if the switch element 1103ba is in the on state, a current flows from the wiring 1523a to 1522b via the diode 1530ba, and if it is in the off state, no current flows anywhere. Not flowing. Here, the state programmed in the switch element 1103ba can be read by detecting the current of the wiring 1523a or the wiring 1522b or detecting whether the voltage precharged in the wiring 1523b is maintained. .

  FIG. 65 is a diagram showing a configuration of an embodiment in which the switch array according to the present invention is three-dimensionally arranged. Referring to FIG. 65, the switch array of this embodiment includes a semiconductor substrate 1100, a switch element 1103, a first wiring layer 1123a, a second wiring layer 1123b, a third wiring layer 1123c, and a fourth wiring layer. Wiring layer 1123d, and a switch element 1103 is disposed between the wiring layers.

  Since a conventional switch circuit composed of semiconductor elements is formed on a semiconductor substrate 1100 in a planar manner, there is a problem that the area occupied by the switches increases in proportion to the number of switches.

  On the other hand, since the switch array structure according to the present invention uses switches formed in the wiring layer, the switch elements can be formed in multiple layers by embedding in the wiring layer formed in multiple layers. As a result, the number of switches per unit area can be increased, and the degree of integration can be increased.

  With respect to the above-described semiconductor integrated circuit having a switch element in the conflict region and the wiring layer, those skilled in the art will be able to make various modifications without departing from the principle and scope of the invention described in the claims. Needless to say, changes, changes and modifications are included.

It is a figure for demonstrating one Embodiment of this invention, (A) is a figure which shows typically the three-dimensional structure of a wiring structure provided with a switch element in a via, (B) equips a via with a switch element. It is a figure which shows typically the cross section of a wiring structure. It is a figure which shows a wiring structure provided with the switch element with a control gate by other embodiment of this invention. It is a figure which shows the wiring structure which can change the connection of a logic circuit by one Embodiment of this invention. It is a figure which shows the wiring structure which can change the connection of a logic circuit by other embodiment of this invention. It is a figure which shows the structure of one Example of the programmable logic circuit using the switch element concerning this invention. It is a figure which shows the structure of one Example of the programmable selector circuit using the switch element based on this invention. It is a figure which shows the structure of another Example of the programmable selector circuit using the switch element based on this invention. It is a figure which shows the structure of another Example of the programmable selector circuit using the switch element based on this invention. It is a figure which shows the structure of another Example of the programmable selector circuit using the switch element based on this invention. It is a figure which shows the structure of one Example of the logic circuit which has a selector using the switch element based on this invention. It is a figure which shows the structure of another Example of the logic circuit which has a selector using the switch element based on this invention. It is a figure which shows the structure of one Example of PLD which has the selector and logic gate using the switch element based on this invention. It is a figure which shows the example of the semiconductor integrated circuit which can program a logic function to which the wiring structure which concerns on this invention is applied, (a), (b) is a half adder and its equivalent circuit, (c), (d ) Is a diagram showing a flip-flop and its equivalent circuit. It is a figure for demonstrating an example of the method of changing the connection of the switch matrix of the semiconductor integrated circuit shown in FIG. It is a figure for demonstrating an example of the method of changing the connection of the switch matrix of the semiconductor integrated circuit shown in FIG. It is a figure for demonstrating the method to change the connection of the switch matrix of the semiconductor integrated circuit shown in FIG. 14 shows an example of a three-dimensional structure of a switch matrix of the semiconductor integrated circuit shown in FIG. It is a figure which shows an example of the three-dimensional structure of the switch matrix which makes a comparative example. It is a figure which shows one Example of the switch box to which the wiring structure which concerns on this invention is applied. 1 is a diagram showing an example of a programmable semiconductor integrated circuit to which a wiring structure according to the present invention is applied. It is a figure which shows the structure of one Example of the memory cell to which the wiring structure which concerns on this invention is applied, (A) is a cross-sectional structure, (B) has shown the circuit structure. It is a figure which shows the structure of another Example of the memory cell to which the wiring structure based on this invention is applied, (A) is a cross-sectional structure, (B) has shown the circuit structure. It is a figure which shows the structure of one Example of the memory cell array using the memory cell based on this invention. It is a figure which shows the structure of one Example of the write circuit or read-out circuit of the memory cell to which the wiring structure which concerns on this invention is applied. It is a figure which shows the structure of the other Example of the write circuit or read-out circuit of the memory cell to which the wiring structure which concerns on this invention is applied. It is a figure which shows the structure of another Example of the write circuit or read circuit of a memory cell to which the wiring structure of this invention is applied. It is a figure which shows the structure of another Example of the write circuit or read-out circuit of the memory cell to which the wiring structure of this invention is applied. FIG. 26 is a diagram showing an example of a detailed circuit configuration of a write circuit of the memory shown in FIG. 25. It is a figure which shows one Example of a structure of the memory cell to which the wiring structure which concerns on this invention is applied. It is a figure which shows the structure of the other Example of the memory cell to which the wiring structure which concerns on this invention is applied. It is a figure which shows one Example of the wiring structure of this invention. It is a figure which shows the other Example of the wiring structure of this invention. It is a figure which shows the wiring structure of FIG. 32, and arrangement | positioning of a switch. It is a figure which shows one Example of the cross section of the wiring structure of this invention. It is a figure which shows the structure of one Example of the memory cell using the wiring structure which concerns on this invention. It is the figure which showed typically the three-dimensional structure of the example which connected two different wiring layers using the switch element which concerns on this invention. It is a figure for demonstrating operation | movement of the 3 terminal switch element based on the Example of this invention. It is a figure which shows the structure of the integrated circuit formed on the semiconductor substrate by another Example of this invention. It is a figure which shows the structure of the conventional switch circuit which can be programmed. It is a figure which shows the structure of the programmable switch circuit by the switch element using the solid electrolyte which concerns on the Example of this invention. It is a figure which shows the structure of the programming circuit of the 2 terminal switch element based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the two-terminal switch element connected in parallel based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the 3 terminal switch element based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the two-terminal switch element connected in parallel based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the switch matrix based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the switch matrix based on the Example of this invention. It is a figure which shows the structure of the programmable logic circuit using the switch matrix based on the Example of this invention. It is a figure which shows the operation example of the programmable logic circuit based on the Example of this invention. It is a figure which shows the structure of the field programmable logic circuit based on the Example of this invention. It is a figure which shows the structure of the switch circuit in the field programmable logic circuit based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the switch matrix provided with the connection verification circuit based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the switch matrix provided with the connection verification circuit based on the Example of this invention. It is a figure which shows the structure of the programming circuit of the switch matrix provided with the connection verification circuit based on the Example of this invention. It is a figure which shows the structure of the connection verification circuit of the switch circuit connected in series which concerns on the Example of this invention. It is a figure which shows the structure of the programming procedure of the switch circuit which concerns on the Example of this invention. It is a figure which shows the structure of the programmable input / output circuit based on the Example of this invention. It is a figure which shows the structure of the switch matrix using the 3 terminal switch element based on the Example of this invention. It is a figure which shows the structure of the switch matrix using the 3 terminal switch element based on the Example of this invention. It is a figure which shows the structure of the nonpolar switch circuit based on the Example of this invention. (A), (b), (c) is a figure which shows the circuit diagram of the memory cell array based on the Example of this invention, a layout diagram, and sectional drawing. FIG. 61 is an explanatory diagram of the operation of the memory cell array of FIG. 60. (A), (b), (c) is a figure which shows the circuit diagram of the memory cell array based on the Example of this invention, a layout diagram, and sectional drawing. (A), (b) is a figure which shows the layout figure and sectional drawing of the memory cell array based on the Example of this invention. FIG. 64 is a diagram for explaining the operation of the memory cell array in FIG. 63. It is a figure which shows the structure of the integrated circuit by which the switch element based on the Example of this invention is arrange | positioned in the wiring layer in three dimensions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 101 1st wiring layer 102 2nd wiring layer 103 Via (switching element) which can change electrical conductivity
104 Copper sulfide 105 Electrode 106 Electrode 111 First wiring layer 112 Second wiring layer 113 Conductivity variable member (electrolyte material)
114 Source electrode 115 Drain electrode 116 Gate electrode 117 Void 118 Switch element 119 Conductive metal deposit 1120 Electronic circuit 121, 122, 123, 131, 132, 133 Logic circuit 126 Via 150 Input terminal 151 Selector 152 Switch element 153 Sense circuit 153-1 Inverter 153-2 Transistor 154 Output terminal 155 Constant voltage source 160 Input / output terminal 161 Switch element 162 Input / output terminal 171 Transistor 172 Control input 180 Resistive element, transistor, or a combination thereof 181 Constant voltage source 190 Transistor 191 Control terminal 200 input terminal 201 selector 202 logic circuit 203 output terminal 204 global wiring 211 selector 213 output terminal 220 input terminal 221 Switch element 222 logic gates 223 output terminal 230 output terminal 231 the switch element 232 switch box 240 logic block 241 the switching circuit (switch box)
251 Access transistor 255 Bit line 256 Word line 257 Plate line 258 Switch element 270 Current source 271 Memory cell 273 Reference voltage 274 Voltage comparator 275 Output terminal 284 Replica memory cell 285 Resistance element 290 Voltage source 292 Reference current 293 Current comparator 294 Output Terminal 310 SRAM cell 311 Switch element 313 Bias voltage 314, 315 Terminal 317 Access transistor 321 Transistor 322 Switch element 400 Switch matrix 401-404 NAND gate 405-408 Inverter 409, 410 Switch matrix 411 On-state switch element 420 Switch element 422 Vertical Wiring 424 side wiring 426 transistor 430 logic gate 431 wiring 432 Switch element 433 Switch matrix 442 Memory element 443 Pass transistor 450 Data input 451 Write pulse 452, 467 Inverted output 453, 466 Normal output 454 pMOS switch 455 nMOS switch 456 pMOS type current mirror circuit 457 nMOS type current mirror circuit 459 Reference line 461 Memory cell array 468 nMOS switch 469 pMOS switch 470 Voltage comparison output (reset signal)
471, 472 D-type flip-flop 474, 477 Dummy access transistor 478, 479 Inverter 480 Horizontal wiring 481 Vertical wiring 483 Programmed wiring 500 Vertical wiring 501 Horizontal wiring 502 Control line 504 Switch element 505 Transistor 510 Vertical wiring 511 Horizontal wiring 512 Control line 513 Three-terminal switch element 540 Switch element connecting vertical wiring and horizontal wiring 541 Switch element connecting horizontal wiring 542 Switch element connecting vertical wiring 543 Vertical wiring 544 Horizontal wiring 550 Third wiring layer 560, 561 Switch element 562 Input / output terminal 563 First voltage source 564 Second voltage source 1100 Semiconductor substrate 1103 Via (two-terminal switch element)
1113 Electrolyte material 1114 Source 1115 Drain 1116 Gate electrode 1118 Three-terminal switch 1120 Electronic circuit 1121 Switch circuit 1122 Contact or via 1123 Wiring 1124 SRAM
1125 Pass transistor 1126 Programmable switch first terminal 1127 Programmable switch second terminal 1128 Flip flop 1201 Anode electrode 1202 Cathode electrode 1203 pMOS transistor 1204 nMOS transistor 1205 pMOS transistor 1206 nMOS transistor 1207 Control input 1208 Control input 1209 control input 1210 control input 1211 voltage source 1212 voltage source 1215 selection transistor 1216 control input 1220 pMOS transistor 1221 nMOS transistor 1222 pMOS transistor 1223 nMOS transistor 1224 pMOS transistor 1225 nMOS transistor 1226 control input 1227 control Input 1229 Control input 1230 Control input 1231 Control input 1232 Voltage source 1233 Voltage source 1233 Voltage source 1234 Voltage source 1250 Wiring 1251 Control input 1252 pMOS transistor 1253 Voltage source 1254 Control input 1255 nMOS transistor 1256 Wiring 1257 Control input 1258 pMOS transistor 1259 Voltage source 1261 Control input 1262 Voltage source 1263 Control input 1264 nMOS transistor 1270 Programming circuit 1271 Programming circuit 1272 Three-state circuit control input 1273 Selector 1274 Inverter 1280 Pass transistor 1281 Logic circuit or arithmetic circuit 1282 Switch circuit 1283 Switch matrix 1284 between wirings 1284 Logic circuit 1 Switch matrix 1285 connecting the wirings to the wiring 1285 Switch circuit connecting the vertical wirings or the horizontal wirings 1290 pMOS transistor 1291 nMOS transistor 1292 pMOS transistor 1293 nMOS transistor 1294 pMOS transistor 1295 nMOS transistor 1296 Control input 1297 Voltage source 1300 Control input 1301 pMOS transistor 1302 Control input 1303 pMOS transistor 1304 Control input 1305 pMOS transistor 1306 nMOS transistor 1307 Output terminal 1310 Control input 1311 pMOS transistor 1312 nMOS transistor 1313 Output terminal 1320 Control input 1321 nMOS transistor 1324 Control input 1324 25 pMOS transistor 1326 control input 1327 nMOS transistor 1328 output terminal 1329 output terminal 1330 process for programming switch element to OFF state 1331 process for confirming whether or not normally programmed to OFF state 1332 1331 whether there is any abnormality in process Judgment 1333 Process of programming the selected switch element to the ON state 1334 Process of confirming whether the switch element selected by the 1333 has been programmed to the ON state 1335 Judging whether there is no abnormality in the process of 1334 1340 Three-state buffer 1341 Inverter 1342 Inverter 1343 Input / output terminal 1400 Wiring 1401 Program control line 1402 Program control line 1403 Wiring 1404 Program control gate (inverter)
1405 control input 1406 control output 1407 power input 1408 pMOS transistor 1409 nMOS transistor 1410 first input / output terminal 1411 second input / output terminal 1500 word line 1501 bit line 1502 plate line 1503 wiring or via 1504 transistor 1505 control input 1506 control input 1507 Control input 1508 Control input 1509 Word line 1510 Access transistor 1511 Access transistor 1512 pMOS transistor 1513 nMOS transistor 1514 pMOS transistor 1515 nMOS transistor 1516 Bit line 1517 Plate line 1520 Silicon substrate 1521 N well 1522 Wiring 1523 Wiring 1524 25+ Tier 15 0 diode

Claims (9)

A first electrode;
A second electrode;
An ion conductor interposed between the first electrode and the second electrode and conducting metal ions;
Have
The second electrode is made of a material having a lower ionization tendency than the first electrode,
A two-terminal switch element in which the conductivity between the first electrode and the second electrode is changed by an oxidation-reduction reaction of the metal ions;
First and second transistors of different polarities connected to the first electrode;
Third and fourth transistors of different polarities connected to the second electrode;
Including
The connection state of the first electrode and the second electrode of the two-terminal switch element can be variably set to a short circuit, an open state, or an intermediate state between the short circuit and the open state via the ion conductor. ,
The first transistor comprises a first pMOS transistor having a drain terminal connected to the first electrode and a source terminal connected to a constant voltage source;
The second transistor comprises a first nMOS transistor having a drain terminal connected to the first electrode and a source terminal grounded;
The third transistor comprises a second pMOS transistor having a drain terminal connected to the second electrode and a source terminal connected to a constant voltage source;
The fourth transistor comprises a second nMOS transistor having a drain terminal connected to the second electrode and a source terminal grounded;
The first electrode and the second electrode are connected to a terminal of a logic circuit or an arithmetic circuit;
The gate terminals of the first and second pMOS transistors and the gate terminals of the first and second nMOS transistors are connected to a control signal, respectively.
The voltage supplied from the constant voltage source is a voltage higher than a power supply voltage of the logic circuit or the arithmetic circuit. The switch circuit according to claim 1 , wherein a plurality of the two-terminal switch elements are connected in parallel. Between the first electrode of the two-terminal switch element and the first pMOS transistor and the first nMOS transistor, or between the second electrode and the second pMOS transistor and the second pMOS transistor Between nMOS transistors,
The switch circuit according to claim 2 , comprising at least one transistor. A first electrode;
A second electrode adjacent to the first electrode;
A third electrode facing the first electrode and the second electrode;
An ion conductor that conducts metal ions interposed between the first electrode, the second electrode, and the third electrode;
Have
At least one of the first electrode and the second electrode is a material having a lower ionization tendency than the third electrode,
A three-terminal switch element in which the conductivity between the first electrode and the second electrode is changed by an oxidation-reduction reaction of the metal ions;
First and second transistors of different polarities connected to the first electrode;
Third and fourth transistors of different polarities connected to the second electrode;
Fifth and sixth transistors of different polarities connected to the third electrode;
A switch circuit comprising: The first transistor includes a first pMOS transistor having a drain terminal connected to the first electrode and a source terminal connected to a constant voltage source.
The second transistor comprises a first nMOS transistor having a drain terminal connected to the first electrode and a source terminal grounded,
The third transistor comprises a second pMOS transistor having a drain terminal connected to the second electrode and a source terminal connected to a constant voltage source.
The fourth transistor includes a second nMOS transistor having a drain terminal connected to the second electrode and a source terminal grounded.
The fifth transistor includes a third pMOS transistor having a drain terminal connected to the third electrode and a source terminal connected to a constant voltage source.
The sixth transistor comprises a third nMOS transistor having a drain terminal connected to the third electrode and a source terminal grounded,
The gate terminals of the first, second, and third pMOS transistors and the gate terminals of the first, second, and third nMOS transistors are connected to a control signal, respectively. Item 5. The switch circuit according to item 4 . A first wiring set composed of n wirings arranged in parallel;
A second wiring set comprising m wirings arranged in parallel;
a first program control line set consisting of n wires;
a second program control line set comprising m wires;
n × m three-terminal switch elements according to claim 4 ;
n × m pMOS transistors;
n × m nMOS transistors;
With
The first wiring set and the second wiring set are arranged to cross each other,
5. One of the three-terminal switch elements according to claim 4 is provided at an intersection of n × m places where n wirings of the first wiring set and m wirings of the second wiring set intersect. One by one,
The first terminal of the three-terminal switch element is connected to the wiring of the first wiring set, the second terminal is connected to the wiring of the second wiring set,
N wirings of the first program control line set are respectively arranged in parallel and close to n wirings of the first wiring set;
The m wirings of the second program control line set are arranged in parallel and close to the m wirings of the second wiring set, respectively.
At the intersection of n × m places where the n wirings of the first program control line set and the m wirings of the second program control line set intersect, the pMOS transistor, the nMOS transistor, Are arranged one by one, the source terminal of the pMOS transistor is connected to the wiring of the second program control line set, and the gate terminal of the pMOS transistor is connected to the wiring of the first program control line set. , The drain terminal of the pMOS transistor is connected to the third terminal of the three-terminal switch element;
The source terminal of the nMOS transistor is grounded, the gate terminal of the nMOS transistor is connected to the wiring of the first program control line set, and the drain terminal of the nMOS transistor is the third terminal of the three-terminal switch element. A switch circuit connected to the switch. A first wiring set composed of n wirings arranged in parallel;
A second wiring set comprising m wirings arranged in parallel;
a program control line set comprising n or more (n + m−1) or less wires;
n × m three-terminal switch elements according to claim 4 ;
With
The first wiring set and the second wiring set are arranged so as to cross each other, and n wirings of the first wiring set and n wirings of the second wiring set cross each other. The three-terminal switch elements are arranged one by one at intersections of × m places,
The first terminal of the three-terminal switch element is connected to the wiring of the first wiring set,
The second terminal of the three-terminal switch element is connected to the wiring of the second wiring set,
The third terminal of the three-terminal switch element is connected to the wiring of the program control line set,
The program control line set wiring crosses the first wiring set wiring and the second wiring set near an intersection of the first wiring set wiring and the second wiring set wiring, respectively. Arranged to
Each wiring of the program control line set is connected to the three-terminal switch elements in the same row only at one place, and is connected to the three-terminal switch elements in the same column only at one place,
Third terminals of the three-terminal switch elements in the same row are respectively connected to different wires of the program control line set,
3. The switch circuit according to claim 1, wherein third terminals of the three-terminal switch elements in the same column are respectively connected to different wires of the program control line set. A method of programming a switch circuit according to claim 4 ,
A first voltage is supplied to the third electrode;
Programming to turn on the switch when the first and second electrodes are grounded;
A programming method comprising: programming to turn off a switch when the third voltage is grounded and the second voltage is supplied to the first and second electrodes. A method of programming a switch circuit according to claim 4 ,
Programming to turn on the switch when the third electrode is grounded and a second voltage is applied to the first and second electrodes;
A programming method comprising: programming to turn off a switch when a first voltage is supplied to the third electrode and the first and second electrodes are grounded.

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