WO2007052207A1

WO2007052207A1 - Memory matrix composed of memory cells each constituted by a transistor and a memory element connected in parallel

Info

Publication number: WO2007052207A1
Application number: PCT/IB2006/054000
Authority: WO
Inventors: Victor M. G. Van Acht; Nicolaas Lambert; Pierre H. Woerlee; Andrei Mijiritskii
Original assignee: Nxp B.V.
Priority date: 2005-11-01
Filing date: 2006-10-30
Publication date: 2007-05-10

Abstract

A memory matrix (10) in an electronic circuit comprises rows and columns of cells (100), each cell comprising an access control transistor (106) and a memory circuit element (104). Each column comprises a series arrangement (102) of main current channels of a plurality of the access control transistors (106). The memory element (104) in each cell (100) is coupled in parallel to the main current channel of the access control transistor (106) of the cell (100). Word lines (14) are coupled to control electrodes of the access control transistors (106) in cells (100). During readout an addressed one of access control transistors (106) of the series arrangement (102) is switched to a non-conductive state and the remaining ones of the access control transistors (102) of said series arrangement (102) are switched to a conductive state during access to the memory cells (100). A sensing circuit (16) coupled to the series arrangements (102) for measuring conductivity of the series arrangements (102), which is determined mainly by the conductivity of the memory element (104) of the selected cell.

Description

MEMORY MATRIX COMPOSED OF MEMORY CELLS EACH CONSTITUTED BY A TRANSISTOR AND A MEMORY ELEMENT CONNECTED IN PARALLEL

The invention relates to an electronic circuit that comprises a memory matrix. Matrix organization is a well-known form of realizing large memories. As used in SRAM and DRAM memories, the matrix contains cells that are each individually connected to a bit line, through an access transistor that can be switched on and off to select the cell. The bit lines in turn are coupled to a sensing circuit for determining the content of the selected cells.

A similar structure may be used for non- volatile memories that use floating gate transistors. In this case, the function of memory cell and access transistor is combined in one floating gate transistor and the drains of a plurality of floating gate transistors are connected in parallel to a bit line, the sources being coupled to ground. Because of its structural similarity to NOR logic gates, such a structure is called a NOR memory. In contrast, a different non- volatile memory structure is called NAND memory, because of its similarity to NAND gates.

Here the series arrangement of main current channels of a plurality of floating gate transistors is coupled to a bit line. Sensing is performed by measuring the conductivity of the series arrangement when all but a selected transistor in the series arrangement to a fully conductive state and while the selected transistor is driven so that its conductivity depends on its stored information. The advantage of a NAND structure is its high layout density. No drain contacts or source contacts to the transistors inside the series arrangement are needed. Floating gate transistors are only one type of non- volatile memory element.

Many other types of memory elements have been developed that exhibit conductivity dependent on stored information. One simple example of a memory element is a fuse, i.e. a circuit element that initially has high conductivity, until it is "blown" to change the stored information. Other examples include hysteresis elements, which retain one conductivity level after application of a high positive voltage across their terminals, until a high negative voltage has been applied, after which they retain a different conductivity level. Further examples include phase change elements. Here the phase assumed by material in the memory element (e.g. amorphous or crystalline) depends on the speed of change of a high voltage across the material. The conductivity depends on the phase. Hence such phase change elements exhibit different semi-permanent conductivity, dependent on a last previous speed of change of a high voltage across their terminals.

To realize a memory matrix, known circuit arrange each memory element of this type in series with an access control transistor and the series arrangements are coupled in parallel to a bit line. That is, the known structures correspond to the NOR structure of floating gate transistor memory.

Among others, it is an object to realize a high memory density in a memory that uses memory element that have a conductivity dependent on stored information.

According to one aspect a circuit according to claim 1 is provided. Herein, a series arrangement of main current channels of a plurality of access control transistors is used, and memory element coupled in parallel to the main current channel of respective ones of the access control transistors. During reading an addressed one of access control transistors of the series arrangement is switched to a non-conductive state and the remaining ones of the access control transistors to a conductive state. A sensing circuit measures conductivity of the series arrangement, which is determined by the conductivity of the memory circuit element that is in parallel with the access control transistor that is in the non-conductive state. .

Preferably, the electronic circuit is implemented on a semi-conducting substrate or layer, that comprises channel regions for respective ones of the columns, crossed by the word lines to form gate electrodes of the access control transistors. Respective structures, each comprising the memory elements are implemented in a further layer or layers over said substrate or layer, the structures each being coextensive with a corresponding channel region. Thus a highly compact memory matrix can be realized.

Preferably, each column comprises a plurality of series arrangements, a bit line conductor, and a plurality of selection transistors, each with a main current channel coupled between the bit line conductor and a respective one of the series arrangements for the column. Thus, the number of memory circuit elements per series arrangement in a column can be limited, which provides for more reliable read-out.

Preferably, writing is performed by applying a write pulse over the series arrangement while an addressed one of access control transistors of the series arrangement has been switched to a non-conductive state and the remaining ones of the access control transistors to a conductive state have been switched to a conducting state. These and other objects and advantages of the invention will be illustrated with the following description of exemplary embodiments, using the accompanying figures. Figure 1 shows an electrical circuit structure of a memory Figure 2 shows a cross-section of part of a memory in an integrated circuit Figure 2 A shows a top view of part of a memory in an integrated circuit

Figure 3 shows a cross-section of part of a memory in an integrated circuit Figure 4 shows a circuit structure of a memory

Figure 1 shows an electrical circuit structure of a memory. The memory contains a matrix 10 of memory cells 100 (only one indicated explicitly for the sake of clarity), a row addressing circuit 12, word lines 14 and a sensing circuit 16. Each cell 100 contains a memory element 104 and an access control transistor 106. Cells 100 are arranged in rows and columns. Row addressing circuit 12 has outputs coupled to word lines 14. Each word line 14 corresponds to a respective row and is connected to the control electrodes of the access control transistors 106 in the cells 100 in the row.

In each column a group of cells 100 is connected in a series arrangement 102. In each series arrangement 102 the main current channels of the access control transistors 106 of the cells 100 are coupled in series. In each cell the memory element 104 is coupled in parallel to the main current channel of the access control transistor 106, with a first and second terminal of the memory element 104 coupled to the source and drain of the access control transistor 106 respectively. Each series arrangement 102 is coupled to sensing circuit 16.

In operation, during readout, an address is applied to row addressing circuit 12. In response, row-addressing circuit 12 applies voltages to word lines 14 so that the access control transistors 106 of cells in an addressed row are driven to a non-conductive state and the access control transistors 106 of cells in the remaining rows in the series arrangement 102 are driven to a conductive state. Thus, ideally only the memory elements 104 of the cells in the addressed rows substantially affect the conductivity of the series arrangement 102. Sensing circuit 16 detects the information content stored in the memory elements 104 of the addressed row by comparing the conductivity to a reference level. This may be done in a conventional way, for example by applying a voltage across the series arrangement 102 and comparing the resulting current with a reference. Figure 2 shows a cross-section of part of a memory in an integrated circuit. The cross section corresponds to a series arrangement of cells 100 (only one indicated for the sake of clarity). The cross-section shows a substrate (or well) region 20, source/drain regions 22, word lines 14 that act as gate electrode, a layer of memory material 24 and connections 26. Isolating material (shown as space that is not specifically labelled) is provided between different elements. The integrated circuit may be manufactured by steps that are known per se from conventional IC manufacturing processes.

In substrate (or well) region 20 source/drain regions 22 have been defined in a conventional way, for example by diffusion. Word lines 14 run transverse to the plane of cross-section and form gate electrodes over a channel area between successive source/drain regions 22. Thus, a series arrangement of access control transistors is realized.

The layer of memory material 24 is provided over this series arrangement. Connections 26 electrically connect successive points in the layer of memory material 24 to source/drain regions that form nodes between successive access control transistors 106 in series arrangement 102.

Figure 2A shows a see-through top view of the integrated circuit, wherein the plane of cross-section of figure 2 has been indicated by a dashed line 28. Isolation barriers 29 are provided between the series arrangements of successive columns. In the embodiment of figure 2A the layer of memory material 24 has locally narrowed parts 24a between the connections 26 to the nodes between the transistors. As may be appreciated the layout provides for a high density. The underlying semi-conductor structure can be realized as a channel region that runs on through all access control transistors 106 of the series arrangement 102 and which is crossed by conductors that form gate electrodes. Minimal dimensions can be used for the source/drain contacts and the gate width. Layer of memory material 24 does not need to add to the surface area occupied by the access control transistors, as it is implemented in a different layer, preferably overlying the area occupied by the access control transistors. Preferably layer of memory material 24 overlies the underlying channel region of all access control transistors in the series arrangement, the part of the layer of memory material 24 that forms memory elements extending substantially as far as the part of the channel region that forms the corresponding access control transistors. Herein, the term "coextensive" to the channel region will be used for such an arrangement of said part of layer of memory material 24. Alternatively the layer of memory material 24 may be provided at an offset with that part of the channel region. In this case the memory material is also said to be coextensive with the channel region, i.e. to have a length that extends substantially as far as the corresponding access control transistors.

In one embodiment the layer of memory material 24 is made of a fuse material which is known per se and which can be "blown" by generating a high current density. During writing access control transistors 106 of all but one row are driven to a conductive state using word lines 14. A current is passed through the series arrangement 102. The strength of this current is set to a size sufficient to "blow" the layer of memory material 24 in a narrowed part 24a but insufficient to blow the layer of memory material 24 in wider parts, such as over connections 26. This current is shunted away from the layer of memory material 24 by the access control transistors 106 of unselected rows. In a selected row the access control transistor is not driven to a conductive state, so that the layer of memory material 24 is blown selectively in the selected row. Narrowed parts 24a ensure that blowing is localized. Preferably, irreversible blowable material is used. However, alternatively some form of reversible phase change material may be used that can be restored, for example by using a lower amplitude write pulse or a write pulse of opposite sign.

As will be understood, this technique of writing is not limited to blowing of fuses. Layers of memory material 24 with different properties may be used, for example a phase change material such as a chalcogenide alloy similar to the ones used in CD-RW and DVD-RW, in which case a speed of change of the current through the series arrangement may be used to control the stored information (a write pulse with an abrupt termination leaving the material in an amorphous state, corresponding to one logic value, and a write pulse with a slow decay with a time constant higher than a predetermined value decrease leaving the material in a crystalline state, corresponding to a second logic value). In another embodiment updates of the stored information may be performed in two steps: first using a (relatively long) erase pulse, optionally with a decay with a time constant above the predetermined value, for cells in all columns, and subsequently using (relatively short) programming pulses for selected ones of the column for changing the logic values in the cells of the selected columns.

Yet another type of material is of the anti-fuse type, where after production the material is non-conducting (as opposed to the previously described fuse that is conducting after production), but similar to the fuse it can be 'blown' to become conductive. Anti- fuses can be constructed from a thin layer of non-conducting material such as oxides or nitrides between conducting materials such as doped silicon or metals (See also Fig 3). As described, the information stored in a selected memory cell is read by comparing the conductivity of the series arrangement to a reference when the access control transistors 106 in a series arrangement 102 of all but a selected row have been driven to a conductive state, the access control transistors 106 in the selected row being driven to a non- conductive state. The comparison may be performed for example by applying a voltage and comparing the current through the series arrangement with a reference. Preferably, only two nominal conductivity levels of a memory element 104 are used to represent a logic one and a logic zero respectively. Alternatively, however, a greater number of conductivity levels may be used to represent a larger amount of information, such as ternary information (which one of three logic states is stored in memory element 104), quaternary information etc.

There are limitations on the number of cells that can be included in a series arrangement, due to the fact that access control transistors 106 are not perfect conductors when in the conductive state and/or not perfect isolators when in the non-conductive state. As a result of this, the conductivity of memory elements 104 in unselected rows contribute slightly to the conductivity of the series arrangement. Preferably, the number N of cells in a series arrangement 102 is selected so small that the maximum possible contribution to conductivity differences from the not-addressed cells is below the minimum conductivity differences due to different states in the addressed cell.

In terms of a mathematical formula for the resistance of the series arrangement:

Toff//Ra + (N-I) Ton//R > Toff//Rb + (N-I) Ton//R'

Herein the term on the left of the > sign is the resistance of series arrangement 102 when the memory element 104 of an addressed cell 100 is in a first information state with less than maximal conductivity (characterized by resistance Ra) and the memory elements 104 in all N-I other cells 100 in the series arrangement 102 are in an information state with maximum possible conductivity (characterized by resistance R).

The term on the right of the > sign is the resistance of series arrangement 102 when the memory element 104 of an addressed cell 100 is in a second information state with the next conductivity (characterized by resistance Rb) above that of the first information state and the memory elements 104 in all N-I other cells 100 in the series arrangement 102 are in an information state with minimum possible conductivity (characterized by resistance R'). In the case of binary information Ra=R and Rb=R. For reliable readout the term on the left of the > sign should be much larger than the term on the right. This imposes a maximum on the number N of cells 100 in a series arrangement:

N « 1 + ( Toff//Ra - Toff//Rb )/ (Ton//R' - Ton//R )

As one would expect, the maximum possible number N of cells in a series arrangement increases with increased difference between the high and low resistances of memory elements 104. In a practical memory Toff and Ton, the resistance of the access control transistor 106 in the non-conductive state and the conductive state respectively, may be approximately 1 GigaOhm and 3 Kilo Ohm.

Alternatively the layer of memory material 24 of figure 2 may be replaced by a layer with alternating first and a second layer parts that are made of conductive material and memory material respectively. The parts with conductive material being contacted to the source/drain regions. Thus a higher resistance ratio can be realized between logic one and zero states.

Figure 3 shows an embodiment wherein the layer of memory material 24 is replaced by a more structured configuration. Alternating first and second conductors 30, 32 are provided, which are not directly mutually connected. Layer parts of memory material 34 couple successive pairs of first and second conductors 30, 32. Furthermore, each of the first and second conductors 30, 32 is connected to the source/drain region 22 that correspond to a respective one of the nodes between successive access control transistors 106, via a connection 26. This configuration can be manufactured for example by first depositing and patterning the first conductors 30, then depositing and patterning layer parts of memory material 34 and then depositing and patterning the second conductors 32. In this way a thin layer of memory material 34 is provided, wherein localized writing is possible. Since the remainder of the connections between the memory material is implemented by means of conductors, a high ratio between the resistance of the memory material in different logic states is possible. This allows the use of a higher number N of cells in the series arrangement.

It should be noted that advantageously a very high density can be realized, because the superstructure with layer of memory material 34 does not need occupy more area than the minimum area required for the series arrangement of the access control transistors. Various types of memory material may be used as memory material 34. For example, S13N4 In one embodiment thin metal electrodes (not shown) may be provided on both sides of memory material 34 between conductors 40, 32. These thin metal electrodes may be made of Tungsten (W) and/or TiW. Relatively thick oxides (larger than used for other transistors in the integrated circuit) may be used for the access control transistors to reduce the risk of breakdown.

Figure 4 shows an circuit with a memory matrix 10 wherein each columns contains a bit line conductor 40, a plurality of series arrangements 102 of cells, a plurality of selection transistors 42 and a programming circuit 44. Each selection transistor 42 has a main current channel coupled in series between a first terminal of a respective series arrangement 102 and the bit line conductor 40 of the column. A second terminal of each series arrangement 102 is coupled to a reference conductor 46 e.g. a power supply conductor. Row addressing circuit 12 has outputs, each coupled to the control electrodes of selection transistors 42 of corresponding series arrangements 102 in a plurality of columns. In operation, when row addressing circuit 12 receives an address of a row, row addressing circuit 12 drives the control electrodes of the selection transistors 42 of the series arrangements 102 to which the cells in the addressed rows belong to a conductive state. Row addressing circuit 12 drives the control electrodes of the other selection transistors 42 to a non-conductive state. Also, as described before, the access control transistors (not labelled explicitly shown) of the addressed row are driven to a non-conductive state. The access control transistors of the not-addressed rows in at least the series arrangement 102 that contains a cell coupled to the addressed row are driven to the conductive state.

In this way, sensing circuit 16 is made to measure conductivity of a selected series arrangement 102 that contains an addressed cell. Each series arrangement contains no more than a number N of cells that allows for detection, but each row contains a plurality of series arrangements, so that a larger number than N (typically an integer multiple of N) cells can be used in a row.

Programming is performed by activating programming circuit 44. In one embodiment writing to selected memory cells is realized as follows. Row addressing circuit 12 receives the address of a row of the memory cells. Row addressing circuit 12 converts the address to control signals that make all but that access control transistors 106 of the cells in the series arrangement 102 that contains the selected row conductive. Row addressing circuit 12 makes the access control transistors 106 of the cells in the selected row non-conductive. Row addressing circuit 12 makes the selection transistors 42 of the series arrangements 102 that contain the selected row conductive and the selection transistors 42 of the other series arrangements 102 non-conductive.

In this state (starting earlier or later) programming circuit 44 applies a high voltage (higher than the normal read voltage) to the bit line conductors 40 of those columns where a first bit value must be written and a lower voltage to the other bit line conductors. In the case of the fuse implementation of memory elements 104, the high voltage is selected so high that sufficient voltage develops over the memory elements 104 in the selected row to blow the fuses, but so low that the voltage developed over the conductive transistors remains so low that no other fuses in the series arrangement 102 will be blown. In the case of an arrangement where the programmed data value depends on the duration of application of the high voltage, or the speed at which the high voltage is reduced, programming circuit 44 applies correspondingly longer or shorter, or more slowly and rapidly changing pulses to the bit line conductors 40.

In the case of an arrangement where the memory elements have to be erased before programming, programming circuit first applies an erase signal to the bit line conductors 40 of all columns, before applying programming signals to bit line conductors 40 of selected columns. Alternatively, separate erase circuit and programming circuits may be used for this purpose. An erase circuit of this type may be coupled to all columns in parallel for example, or to a number of series arrangements in different columns in parallel. In one embodiment, erasing is performed for selected rows for a plurality of series arrangements in the same column. In this embodiment row addressing circuit 12 makes selection transistors 42 of a plurality (e.g. all) of series arrangements 102 in the same column are conductive together. Also row addressing circuit 12 makes one selected access control transistor 106 in each of these series arrangements 102 non-conductive and the remaining access control transistors 106 in these series arrangements 102 are made conductive. Then programming circuit 44, or a separate erase circuit applies an erase pulse to bit line conductors 40. Thus, time is saved during erasing.

Although programming has been described in the context of figure 4, that is for an embodiment with selection transistors 42 and a plurality of series arrangements 102 per column, it should be appreciated a similar programming circuit 44 may be coupled directly to a single series arrangement 102 or through other circuits.

Claims

CLAIMS:

1. An electronic circuit comprising a memory matrix (10) comprising rows and columns of cells (100), each cell comprising an access control transistor (106) and a memory circuit element (104), each column comprising a series arrangement (102) of main current channels of a plurality of the access control transistors (106), the memory element (104) in each cell (100) being coupled in parallel to the main current channel of the access control transistor (106) of the cell (100), word lines (14) each coupled to control electrodes of the access control transistors (106) in cells (100) in a respective one of the rows; - a sensing circuit (16) coupled to the series arrangements (102) for measuring conductivity of the series arrangements (102).

2. An electronic circuit according to claim 1, comprising a row addressing circuit (12) with an address input and outputs coupled to the word lines (14) and arranged to switch an addressed one of access control transistors (106) of the series arrangement (102) to a non- conductive state and the remaining ones of the access control transistors (102) of said series arrangement (102) to a conductive state during access to the memory cells (100).

3. An electronic circuit according to claim 1, implemented on a semi-conducting substrate or layer, the substrate or layer comprising channel regions (20) for respective ones of the columns, crossed by the word lines (14) to form gate electrodes of the access control transistors (106), respective structures (24, 26, 30, 32, 34), each comprising the memory elements (104) being implemented in a further layer or layers over said substrate or layer, the structures (24, 26, 30, 32, 34) each being coextensive with a corresponding channel region (20).

4. An electronic circuit according to claim 3, wherein each structure (24, 26) comprises a layer of memory material (24) that is coextensive the corresponding channel region and contacts (26) between said layer and source/drain contacts in the channel region (20).

5. An electronic circuit according to claim 3, wherein each structure comprises a alternate layer parts of conductor material and memory material, and contacts between said the layer parts of conductor material and source/drain contacts (22) in the channel region (20).

6. An electronic circuit according to claim 3, wherein each structure comprises a plurality of layer parts (34); - first contacts (30) between upper faces of the layer parts (34) and a first subset of source/drain contacts (22) in the channel region (20); second contacts (32) between lower faces of the layer parts (34) and a second subset of source/drain contacts (22) in the channel region, wherein source/drain contacts (22) of the first subset alternate with source/drain contacts of the second subset.

7. An electronic circuit according to claim 1, wherein each column comprises a plurality of series arrangement (102) of main current channels of a plurality of the access control transistors (106), the memory element (104) in each cell (100) being coupled in parallel to the main current channel of the access control transistor (106) of the cell (100), each column further comprising a bit line conductor (40), a plurality of selection transistors (42), each with a main current channel coupled between the bit line conductor (40) and a respective one of the series arrangements (102) for the column.

8. An electronic circuit according to claim 1, wherein each column comprises writing circuit (44) coupled to the series arrangement (102) and arranged to apply a write pulse over the series arrangement (102) while an addressed one of access control transistors (106) of the series arrangement (102) has been switched to a non-conductive state and the remaining ones of the access control transistors (106) of the series arrangement (106) have been switched to a conductive state.

9. An electronic circuit according to claim 1, wherein each memory element (104) comprises a blowable fuse or anti-fuse material.

10. An electronic circuit according to claim 1, wherein each memory element (104) comprises a phase-change materials of which a conductivity depends on a history of voltage difference signal waveforms applied across the phase-change material

11. An electronic circuit according to claim 1 , wherein each memory element (104) comprises material of which the conductivity depends on a sign of a last prior extreme driving condition.