JP4118500B2 - Point contact array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a point contact array using a plurality of elements for controlling conductance by forming or cutting point contacts between opposing electrodes.
[0002]
[Prior art]
A method for controlling conductance by configuring point contacts is disclosed in, for example, J. Pat. K. Gimzeski and R.M. Moller: Phy. Rev. B36 (1987) 1284, J.A. L, Costa-Kramer, N.M. Garcia, P .; Garcia-Mochales, P.A. A. Serena, M .; I. Marques and A.M. Corrcia: Phys. Rev. B55 (1997) 5416, H.I. Ohnishi, Y .; Kondo and K. Takayanagi: Nature 395 (1998) 780 and the like.
[0003]
These require piezo elements for the construction and control of point contacts. That is, by driving the piezo element, the metal probe attached to the piezo element is positioned with high accuracy with respect to the counter electrode, a point contact is constructed between the probe and the counter electrode, and its state is controlled.
[0004]
Apart from these, as a prior art [2], a method for controlling the conductance of a point contact and using an organic molecule is disclosed in C.I. P. Collier et al ,: Science 285 (1999) 391.
[0005]
In this method, the conductivity of rotaxan molecules sandwiched between opposing electrodes with a single molecular thickness is changed by applying a high voltage between the electrodes. That is, rotaxan molecules sandwiched between electrodes initially exhibit conductivity, but when a voltage of a certain polarity or higher is applied, the molecules are oxidized to reduce conductivity, and the electrodes are insulated.
[0006]
[Problems to be solved by the invention]
However, the above-described prior art [1] requires at least one piezo element for each point contact and a complicated control circuit for driving it, and it is extremely difficult to integrate them. .
[0007]
Further, in the method of the prior art [2] described above, once oxidized molecules cannot be reduced to restore conductivity, the use thereof is extremely limited.
[0008]
In view of the above situation, the present invention controls the conductance between the electrodes electrically and reversibly, and also has a plurality of point contacts that can be applied to arithmetic circuits, logic circuits, memory elements, etc.・ The purpose is to provide an array.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
[1] In a point contact array, a first electrode made of a mixed conductor material having ion conductivity and electron conductivity When Second electrode made of conductive material Between the first electrode and the second electrode by the formation or disappearance of a bridge made of mobile ions in the mixed conductor material A plurality of electronic elements capable of controlling conductance between the electrodes are used.
[0010]
[2] In the point contact array according to [1] above, mobile ions (M ions: M is a metal) original The mixed conductor material having a child) is formed on the movable ion source (M).
[0011]
[3] In the point contact array according to [1] or [2], the mixed conductor material is Ag. ₂ S, Ag ₂ Se, Cu ₂ S or Cu ₂ It is characterized by being Se.
[0012]
[4] In the point contact array according to the above [1], [2] or [3], a bridge is formed between the first electrode and the second electrode by the movable ions contained in the mixed conductor material. The method uses a change in conductance between the electrodes.
[0013]
[5] In the point contact array according to [1], [2] or [3], ions can be dissolved between the first electrode and the second electrode, and the ions can be dissolved. A semiconductor or insulator material that exhibits ionic conductivity with electrons, and when the movable ions contained in the mixed conductor material flow into the semiconductor or insulator material, the conductance of the semiconductor or insulator Is characterized by changing
[6] In the point contact array according to [5], the semiconductor or insulator material is GeS. _x , GeSe _x , GeTe _x Or WO _x It is characterized by being a crystalline or amorphous body (0 <x <100).
[0014]
[7] In the point contact array according to [1], [2], [3], [4], [5] or [6], at least a part of the first electrode covered with a mixed conductor material A plurality of metal wires constituting at least one electrode, and a point contact is provided at each intersection between the metal wires. Features.
[0015]
[8] In the point contact array according to [1], [2], [3], [4], [5], [6] or [7], the conductance of the point contact is quantized. It is characterized by that.
[0016]
[9] The point contact array according to the above [8], wherein a multiple recording memory type element using a quantized conductance of the point contact as a recording state is configured.
[0017]
[10] In the point contact array according to [8], addition or subtraction is performed between the input signals by using the quantized conductance of the point contacts as an input signal and controlling the potential of each electrode. It is characterized by that.
[0018]
[11] In the point contact array according to [1], [2], [3], [4], [5], [6] or [7], the potential at one end of the point contact is defined as an input signal. The logic circuit which comprises is comprised.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
FIG. 1 is a schematic perspective view showing a point contact array in which a plurality of point contacts according to the present invention are arranged.
[0021]
As shown in FIG. 1, a point formed by movable ions (atoms) 5 at the intersection of a metal wire (first electrode) 2 covered with a mixed conductor 1 and metal wires 3 and 4 (second electrode). Contacts (crosslinking) 6 and 7 are formed. These are installed on an insulating substrate 8 and fixed by an insulating material (not shown).
[0022]
When a semiconductor or insulator material is inserted between the first and second electrodes, the conductance of the semiconductor changes due to the mobile ions dissolved in the semiconductor or insulator.
[0023]
As a result, the conductance between the electrodes changes. Note that the amount of change depends on the amount of mobile ions dissolved in the semiconductor or insulator material.
[0024]
For the sake of simplicity, in FIG. 1, a point contact array comprising one metal wire (first electrode) 2 covered with the mixed conductor 1 and two metal wires (second electrodes) 3 and 4 is shown. It is shown. The number of point contacts is a multiplication of the number of metal lines constituting the electrode, and here, 2 × 1 two point contacts are formed. If the number of metal lines constituting the first electrode and the second electrode is increased, an n × n point contact array can be formed.
[0025]
In the present invention, a voltage is applied between the first electrode 2 and the second electrodes 3 and 4 to form or extinguish the bridges 6 and 7 made of ion atoms, and the point contact formed between the electrodes Control conductance. More specifically, when an appropriate negative voltage is applied to the second electrodes 3 and 4 with respect to the first electrode 2, mobile ions (atoms) in the mixed conductor material precipitate due to the effect of the voltage and current. As a result, bridges 6 and 7 are formed between the electrodes. As a result, the conductance between the electrodes increases. Conversely, when an appropriate positive voltage is applied to the second electrodes 3 and 4, mobile ions (atoms) return to the mixed conductor material, and the bridges 6 and 7 disappear. That is, the conductance decreases.
[0026]
Thus, by independently controlling the voltage applied to each metal line, the voltage applied to the point contact formed at each intersection of the first electrode 2 and the second electrodes 3 and 4 can be controlled independently. it can. That is, the conductance of the point contact at each intersection can be controlled independently.
[0027]
Thereby, it is possible to configure an electronic element such as a memory element or an arithmetic element including a point contact array and an electric circuit including them.
[0028]
In the following, the mixed conductor material Ag ₂ Although an example using the first electrode made of S and the movable ion supply source Ag and the second electrode made of Pt will be described, it goes without saying that the same result can be obtained even if other materials are used.
[0029]
The formation of the bridge is sufficient if there are about 10 Ag atoms. From the measurement results, when the voltage is 100 mV and the initial interelectrode resistance is 100 kΩ, 10 Ag atoms are mixed into the mixed conductor Ag. ₂ The time required to extract from S, ie the time required to form a cross-link, was estimated at most tens of nanoseconds. Also, the power required to form a bridge is as small as nanowatts. For this reason, if this invention is used, a high-speed and low power consumption type | mold element can be constructed | assembled.
[0030]
First, a first embodiment of the present invention will be described.
[0031]
FIG. 2 is a schematic diagram of a point contact array applied to a multiple memory device according to the present invention.
[0032]
For simplicity, a sample consisting of two point contacts was used as in FIG. Here, Ag is used as the mixed conductor material 11 constituting the first electrode. ₂ Ag was used as the metal wire 10 for S. In addition, Pt wires were used as the metal wires 13 and 14 constituting the second electrode. The first electrode is grounded, and voltages V1 and V2 are independently applied to the second electrodes 13 and 14, respectively. When a negative voltage is selected as V1 and V2, Ag atoms 12 in the mixed conductor material 11 are deposited, and bridges 15 and 16 are formed. When V1 and V2 are set to positive voltages, the Ag atoms 12 in the bridges 15 and 16 return to the mixed conductor material 11, and the bridges 15 and 16 disappear. This detailed mechanism has been proposed by the present inventor as Japanese Patent Application No. 12-265344.
[0033]
In the present invention, the following new function is realized by using a plurality of point contacts.
[0034]
In this example, the point contact conductance was controlled by applying a pulse voltage. That is, in order to increase conductance, a voltage of 50 mV was applied for 5 milliseconds. When reducing the conductance, a voltage of −50 mV was applied for 5 milliseconds. This realized the transition between quantized conductances at each point contact. That is, this corresponds to a write operation as a memory.
[0035]
Therefore, in order to read the recording state, V1 and V2 are set to 10 mV so that the recorded conductance value is not changed by the reading operation. In this state, the current I flowing in the metal wires 13 and 14 constituting the second electrode of each point contact ₁ , I ₂ Was measured. The result is shown in FIG.
[0036]
In FIG. ₁ With a thin solid line, I ₂ Is indicated by a thick solid line. A writing operation was performed on the point contacts 15 to 16 every second, and the recorded state was read each time. The left vertical axis indicates the actually measured current value, and the right vertical axis indicates the corresponding quantized conductance. The conductance is obtained by dividing the measured current by the applied voltage (10 mV).
[0037]
This figure shows that the conductance of each point contact is quantized. That is, the quantum number of the quantized conductance of the first point contact by the bridge 15 is expressed as N ₁ , The quantum number of the quantized conductance of the second point contact by bridge 16 is N ₂ N ₁ = 0 to 3, N ₂ A total of 16 recording states of 0 to 3 are realized.
[0038]
In this embodiment, only four quantization states of N = 0 to 3 are used, but the recording density can be increased by using a state having a larger quantum number. It goes without saying that the recording density can be increased by increasing the number of point contacts.
[0039]
Next, a second embodiment of the present invention will be described.
[0040]
First, an embodiment in which an adder circuit is realized using the configuration shown in the first embodiment will be described.
[0041]
In the summing circuit according to the invention, the input is the quantum number N of the quantized conductance of the point contact by the bridges 15 and 16. ₁ , N ₂ It is. The input operation is controlled by controlling the voltages V1 and V2. ₁ , N ₂ Is set to a desired value. As a result of the calculation, the current I flowing out from the first electrode 10 to the ground potential is set by setting V1 and V2 to a read voltage, for example, 10 mV. _out Is obtained by measuring.
[0042]
FIG. 4 is a diagram showing the calculation result of the second embodiment of the present invention. Below the graph, the entered N ₁ , N ₂ N measured _out Is shown corresponding to the horizontal axis of the graph. Obtained current value I _out Is N ₁ + N ₂ It can be seen that it has a quantized conductance corresponding to. That is, the addition is performed accurately. In this embodiment, as in the first embodiment, N ₁ = 0 to 3, N ₂ Although 16 kinds of addition results corresponding to 0 to 3 are shown, a larger quantum number may be used. The same can be achieved even if the number of point contacts used, that is, the number of inputs is three or more.
[0043]
Next, a third embodiment of the present invention will be described.
[0044]
The configuration shown in the first embodiment can also be applied to a subtraction circuit. The input control is performed in the same manner as described in the second embodiment. When performing the subtraction operation, it is only necessary to select voltages having the same absolute value and opposite polarity as V1 and V2. For example, if V1 is set to 10 mV and V2 is set to -10 mV, N ₁ -N ₂ The current I corresponding to the quantized conductance corresponding to _out Flows out from the first electrode to the ground potential. At this time, if the current direction is from the first electrode to the ground potential, the calculation result has a positive value, and if the current direction is from the ground potential to the first electrode, the calculation result has a negative value.
[0045]
The calculation results of the third embodiment are shown in FIG.
[0046]
N ₁ -N ₂ The calculation of is performed accurately. Furthermore, if three or more point contacts are used, N ₁ + N ₂ -N _Three It is possible to perform operations such as For example, in this case, calculation may be performed with V1 and V2 set to 10 mV and V3 set to −10 mV.
[0047]
Next, a fourth embodiment of the present invention will be described.
[0048]
This is an embodiment in which a logic circuit is configured using the point contact of the present invention. When configuring the logic circuit, unlike the first to third embodiments, the transition between the quantized conductance states at the point contact is not used. That is, a point contact is used as an on / off switching element. Typically, the resistance value in the on state is 1 kΩ or less, and the resistance value in the off state is 100 kΩ or more.
[0049]
FIG. 6 is a schematic diagram of an OR gate configured using the point contact of the present invention.
[0050]
Ag lines 21 and 22 are Ag ₂ It is covered with S23, 24 to constitute the first electrode. These Ag ₂ Ag bridges 25 and 26 deposited from S 23 and 24 are opposed to the Pt electrode 20 as the second electrode to form a point contact. One end of the Pt electrode 20 is connected to the reference voltage V via a resistor 27 (10 kΩ in this embodiment). _S The other end is the output terminal and the output voltage V _out Is output. When the input voltages V1 and V2 are applied to the Ag lines 21 and 22, the bridges 25 and 26 are thereby formed or disappeared, and the point contact functions as an on / off switching element.
[0051]
FIG. 7 shows the operation result. In this embodiment, the input V is changed every second, that is, V1 and V2 are changed and the output V _out Was measured.
[0052]
In the two-input OR gate, the output must be at a high level if either one of the low level and high level binarized inputs is at a high level.
[0053]
Accordingly, FIG. 7A shows the result when the operation is performed using 0 V as the low level (same for the reference potential Vs) and 200 mV as the high level.
[0054]
According to this figure, when either one of the two inputs V1 and V2 is 200 mV, the output V _out Is approximately 200 mV, indicating that it is operating normally. The same result [FIG. 7B] was obtained even when the high level voltage was increased to 500 mV.
[0055]
FIG. 8 is a diagram showing an equivalent circuit of this logic circuit.
[0056]
The bridges 25 and 26 (FIG. 6) are generated and disappeared by the reference voltage Vs and the input voltages V1 and V2, and the resistance values of the resistors R1 and R2 (point contact portion resistance formed by the bridge) are changed. There is a slight resistance R12 (several Ω to several tens of Ω) between the two point contacts on the electrode 20 (FIG. 6), but it is negligible compared to R0 (10 kΩ), R1, R2 (1 kΩ to 1 MΩ). It is a size.
[0057]
First, when both V1 and V2 are 0V, the three voltages connected to the system are all 0V. _out Inevitably becomes 0V. Next, when V1 is 0 V and V2 is 200 mV (500 mV), the bridge 25 (FIG. 6) grows and the resistance value of the resistor R2 decreases. Typically, it is 1 kΩ or less.
[0058]
As a result, since the resistance value of R2 is smaller by one digit or more than R0, V2 ′ is about 200 mV (500 mV). At this time, V1 ′ is also approximately 200 mV (500 mV). 6 For FIG. 6, a voltage at which cross-linking disappears is applied, and R1 takes a large value of 1 MΩ or more. As a result, even if V1 is 0V, R0, R1 >> R2, so V1 ′ is about 200 mV (500 mV), which is the same as V2 ′. As a result, the output is 200 mV (500 mV). More precisely, the growth of bridge 25 and bridge 2 6 Cuts occur in parallel, resulting in the results described above.
[0059]
The same can be said when V1 is 200 mV (500 mV) and V2 is 0V. When both V1 and V2 are 200 mV (500 mV), the bridges 25 and 26 grow together, so that the voltage of V1 and V2, that is, 200 mV (500 mV) is output.
[0060]
Next, a fifth embodiment of the present invention will be described.
[0061]
An embodiment in which an AND gate is configured will be described with reference to FIG.
[0062]
In this example, Ag ₂ One end of the Ag wire 30 covered with the S thin film 31 is connected to the reference voltage Vs via the resistor 37. The other end is an output terminal. Further, bridges 33 and 34 formed by precipitation of Ag atoms as mobile ions are formed toward the two Pt electrodes 35 and 36. The input voltages V1 and V2 are applied to the two Pt electrodes 35 and 36. In FIG. 9, 32 is Ag. ₂ Ag ions in the S thin film 31.
[0063]
FIG. 10 shows the calculation result of the AND gate. In the 2-input AND gate, only when both inputs are at the high level, the output V _out Becomes High level.
[0064]
FIG. 10A shows the result when the operation is performed with the High level set to 200 mV. At this time, the reference voltage was also set to 200 mV.
[0065]
FIG. 10 (b) shows the results when operating with the High level set to 500 mV. The reference voltage at this time is 500 mV.
[0066]
According to FIG. 10, when the high level is 200 mV, V1 is 0 V, and V2 is 200 mV, the output V _out Indicates a halfway value (about 50 mV). However, other than this, 0 V which is Low level or 200 mV which is High level is output. Further, when 500 mV is set as the High level, it operates normally for all input patterns. Even in the case of 200 mV operation, there is no problem if the critical voltage that determines Low-High is set to 100 mV. This cause will be described later.
[0067]
Again, the operation principle of the AND gate will be described with reference to FIG. In this embodiment, the reference voltage Vs is at a high level (200 to 500 mV). First, when both V1 and V2 are 0 V, since the bridges 33 and 34 (FIG. 9) grow together, the resistance values of the resistors R1 and R2 are typically 1 kΩ or less. That is, since the output terminal is connected to an input voltage at a low level with a resistance value one digit or more smaller than that of the resistor R0 (10 kΩ), _out Becomes 0V. Next, when V1 is 0 V and V2 is 200 mV (500 mV), only the bridge 33 (FIG. 9) grows.
[0068]
On the other hand, the bridge 34 is smaller than 200 mV (500 mV) because the voltage V2 'is the voltage V1. That is, a polarity voltage at which the bridge disappears is applied, the bridge 34 disappears, and the resistance value of R2 increases to about 1 MΩ. If the potential difference between V2 'and V2 at this time is small, the disappearance of the bridge is not sufficient, and therefore the resistance value of R2 does not become sufficiently large, so that the halfway output described above may occur. However, if the high level voltage is set to 500 mV, the potential difference between V2 ′ and V2 becomes sufficiently large, and the operation is completely normal.
[0069]
The same applies when V1 is 200 mV (500 mV) and V2 is 0V. However, since the characteristics of the bridges 33 and 34 constituting the point contact are slightly different, in this case, a normal output is obtained even at an operating voltage of 200 mV. Finally, when both V1 and V2 are 200 mV (500 mV), in this case, the generation and disappearance of the bridges 33 and 34 do not occur. Since all the voltages are 200 mV (500 mV), the output voltage is also 200 mV (500 mV).
[0070]
The logic circuit using the point contact has been described above. In the above embodiment, a two-input logic circuit has been described. However, if three or more point contacts according to the present invention are used, a logic circuit having three or more inputs can be configured based on the above-described operation principle.
[0071]
Next, a sixth embodiment of the present invention will be described.
[0072]
Here, a method for manufacturing a point contact array will be described.
[0073]
FIG. 11 is a diagram showing a method for manufacturing a point contact array according to the sixth embodiment of the present invention.
[0074]
As shown in FIG. 11, Ag lines 41 and 42 are formed on an insulating substrate 40, and the surfaces thereof are sulfurized to form Ag. ₂ S films 43 and 44 are formed. By placing Pt lines 45 and 46 thereon, the main part of this point contact array is completed. The important thing here is Ag ₂ This is that bridges 47 and 48 of Ag atoms are formed at the intersections of the Ag lines 41 and 42 covered with the S films 43 and 44 and the Pt lines 45 and 46.
[0075]
For this reason, in the present invention, when the Pt lines 45 and 46 are placed, a voltage is applied between the Pt lines 45 and 46 and the Ag lines 41 and 42 to obtain Ag. ₂ Ag was deposited from the S films 43 and 44 to form bridges 47 and 48. Thus, for example, the present invention can be realized only by placing the Pt lines 45 and 46 by a wiring device or the like.
[0076]
In addition, Ag may be vapor-deposited in advance at the intersection by vapor deposition using a mask, or Ag. ₂ Ag atoms may be deposited by irradiating an electron beam to the Ag line covered with the S film. What is important is that the Ag constituting the first electrode ₂ Ag exists between S and Pt constituting the second electrode.
[0077]
Further, a Pt line is formed in advance on another substrate, and Ag ₂ It may be bonded to a substrate on which an Ag line covered with an S film is formed.
[0078]
Next, a seventh embodiment of the present invention will be described.
[0079]
Here, the manufacturing method and structure of another point contact array will be described.
[0080]
FIG. 12 is a schematic diagram of a point contact array for controlling the conductivity of a semiconductor according to a seventh embodiment of the present invention.
[0081]
In FIG. 12, Ag is again formed on the insulating substrate 50. ₂ Ag lines 51 and 52 covered with S films 53 and 54 are formed. On top of that, semiconductors or insulators 57, 58, 59, 60 capable of dissolving Ag atoms are formed only at portions corresponding to the intersections of the Ag lines 51, 52 and the Pt lines 55, 56. In addition, although the insulating material which covers these is not shown in FIG. 12, all the parts shown in the figure are embedded inside the element.
[0082]
In this case, Ag ions are converted into Ag by the same principle as described above. ₂ It flows out from the S films 53 and 54. The outflowed Ag ions are dissolved in the semiconductors or insulators 57, 58, 59, 60 to change the conductivity of the semiconductors or insulators, and the same thing as the above-described embodiment can be realized. In this case, since a space for generating and annihilating the bridge is not necessary in the element, it can be easily embedded in the insulating member.
[0083]
If an Ag thin film is formed in advance instead of a semiconductor or an insulator, the same structure as described in the sixth embodiment is obtained. In this case, Ag atoms in the thin film Ag are Ag ₂ The thin film disappears by entering the S film.
[0084]
In the present invention, as a semiconductor or insulator capable of dissolving Ag ions, GeS _x , GeSe _x , GeTe _x Or WO _x A crystal or amorphous material (0 <x <100) was used.
[0085]
Next, an eighth embodiment of the present invention will be described.
[0086]
FIG. 13 shows an embodiment in which a part of the metal wiring as the first electrode is covered with a mixed conductor. In this embodiment, at the intersection of the metal wire constituting the first electrode and the metal wire constituting the second electrode, “metal constituting the first electrode / mixed conductor / bridge or semiconductor / second electrode constituting It is only necessary to form a point contact made of “metal”.
[0087]
Therefore, as shown in FIG. 13, even if the mixed conductors 73 and 74 are formed only in the vicinity of the intersection between the metal wire 70 constituting the first electrode and the metal wires 71 and 72 constituting the second electrode, Point contacts (bridges) 75 and 76 can be formed between the bodies 73 and 74 and the metal wires 71 and 72.
[0088]
Furthermore, the metal composing the first electrode may be different from the portion in contact with the mixed conductor and the wiring material between the point contacts. For example, in this embodiment, a mixed conductor (Ag ₂ S) Ag wires 79 and 80 were used for the portions in contact with 77 and 78, and tungsten wires were used for the other portions 81 to 83. In addition, the member of the part which contact | connects a mixed conductor needs to be comprised with the same element as the movable ion atom in a mixed conductor. Therefore, in this embodiment, Ag is used as the mixed conductor. ₂ Since S was used, Ag was used for the member in contact with this.
[0089]
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0090]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to construct a point contact array that operates at high speed and with low power consumption, and realizes a multi-recording memory element, a logic circuit, an arithmetic circuit, and the like. be able to.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view showing a point contact array in which a plurality of point contacts according to the present invention are arranged.
FIG. 2 is a schematic diagram showing a point contact array constituting a multiple storage memory according to the present invention.
FIG. 3 is a diagram showing a read result of a multiplex memory stored in the first embodiment of the present invention.
FIG. 4 is a diagram illustrating a calculation result of an adder circuit configured by a point contact array according to a second embodiment of the present invention.
FIG. 5 is a diagram illustrating a calculation result of a subtraction circuit configured by a point contact array according to a third embodiment of the present invention.
FIG. 6 is a schematic diagram of an OR gate constituted by a point contact array according to a fourth embodiment of the present invention.
FIG. 7 is a diagram showing an operation result of an OR gate constituted by a point contact array according to a fourth embodiment of the present invention.
FIG. 8 is an equivalent circuit diagram of a point contact array logic circuit showing a fourth embodiment of the present invention.
FIG. 9 is a schematic diagram of an AND gate constituted by a point contact array according to a fifth embodiment of the present invention.
FIG. 10 is a diagram showing a calculation result of an AND gate constituted by a point contact array according to a fifth embodiment of the present invention.
FIG. 11 is a diagram showing a method for manufacturing a point contact array according to a sixth embodiment of the present invention.
FIG. 12 is a schematic view of a point contact array for controlling the conductivity of a semiconductor according to a seventh embodiment of the present invention.
FIG. 13 is a schematic view of a point contact array having an electrode partially covered with a mixed conductor according to an eighth embodiment of the present invention.
[Explanation of symbols]
1 Mixed conductor
2, 10, 70 Metal wire (first electrode)
3, 4, 13, 14, 71, 72 Metal wire (second electrode)
5,32 Mobile ions (atoms)
6,7,15,16,25,26,33,34,47,48,75,76 Point contact (Bridge)
8, 40, 50 Insulating substrate
11, 73, 74, 77, 78 Mixed conductor material (Ag ₂ S)
12 Ag atoms
20 Pt electrode
21, 22, 30, 41, 42, 51, 52, 79, 80 Ag wire (Ag electrode)
23,24 Ag ₂ S
27 Resistance
31 Ag ₂ S thin film
35, 36, 45, 46, 55, 56 Pt line (Pt electrode)
37 resistors
43, 44, 53, 54 Ag ₂ S film
49 Power supply
57, 58, 59, 60 Semiconductor or insulator
81, 82, 83 Tungsten wire

Claims (11)

And a second electrode consisting of the first electrode and the conductive material comprising a mixed conducting material having ion conductivity and electron conductivity, between the first electrode and the second electrode, wherein the mixed conducting material A point contact array comprising a plurality of electronic elements whose conductance between the electrodes can be controlled by forming or annihilating a bridge made of mobile ions . Mobile ions (M ion: M is a metal atom) point contact array according to claim 1, wherein the mixed conducting material is characterized by being formed on said movable ion source (M) having a. The mixed conductive material is Ag ₂ S, Ag ₂ Se, claim 1 or 2 point contact array according to characterized in that the Cu ₂ S or Cu ₂ Se. The use of the fact that a mobile ion contained in the mixed conductor material forms a bridge between the first electrode and the second electrode and changes a conductance between the electrodes. Or point contact array according to 3. A semiconductor or an insulating material capable of dissolving ions between the first electrode and the second electrode and exhibiting electron conductivity and ion conductivity by dissolving the ions is provided. 4. The point contact according to claim 1, 2 or 3, wherein the conductance of the semiconductor or the insulator is changed by the mobile ions contained in the mixed conductor material flowing into the body material.・ Array. 6. The point contact according to claim 5, wherein the semiconductor or insulator material is a crystalline or amorphous substance of GeS _x , GeSe _x , GeTe _x , or WO _x (0 <x <100). Array. A metal wire constituting the first electrode and at least a part of which is coated with a mixed conductor material; and a metal wire constituting the second electrode, wherein there are a plurality of metal wires constituting at least one of the electrodes. 7. The point contact array according to claim 1, wherein a point contact is provided at each intersection between the lines. 8. A point contact array according to claim 1, wherein the conductance of the point contact is quantized. 9. The point contact array according to claim 8, wherein the point contact array comprises a multiple recording memory type device that uses the quantized conductance of the point contact as a recording state. 9. The point contact array according to claim 8, wherein the quantized conductance of the point contact is used as an input signal, and addition or subtraction is performed between the input signals by controlling the potential of each electrode. 8. The point contact array according to claim 1, wherein the point contact array comprises a logic circuit having a potential at one end of the point contact as an input signal.

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