JP4992368B2 - Layout design program, recording medium recording the program, layout design method, and layout design apparatus - Google Patents

Description

  The present invention relates to a layout design program for designing a layout of a semiconductor integrated circuit, a recording medium recording the program, a layout design method, and a layout design apparatus.

  In recent years, with the increase in density and speed of semiconductor integrated circuits, circuit malfunctions and performance degradation due to crosstalk in semiconductor chips and semiconductor packages have become prominent. Therefore, in the design of a semiconductor integrated circuit, it is necessary to take measures to reduce it by considering the influence of crosstalk in advance.

  In the prior art, with regard to the crosstalk about the circuits and wiring inside the semiconductor chip, before the layout design inside the semiconductor chip, the wiring that is likely to cause crosstalk is identified in advance in the circuit and wiring inside the semiconductor chip. There are some which are considered as design constraints at the time of design (see, for example, Patent Document 1 below).

  For crosstalk between internal wirings of semiconductor packages, the electromagnetic field analysis program is used to extract the capacitance and inductance from the semiconductor package circuit / wiring patterns, and the effects of crosstalk are determined by circuit simulation using these. A method for evaluating the above is known.

  In the prior art, by performing the semiconductor chip layout and semiconductor package pattern design by the above-described method, it is possible to develop a semiconductor integrated circuit having a high-quality semiconductor chip or semiconductor package in which crosstalk noise hardly occurs. Has been.

Japanese Patent Application No. 2001-227619

  However, in the prior art described in Patent Document 1, the semiconductor chip and the semiconductor package are generated in consideration of the layout of the semiconductor chip and the layout of the semiconductor package, when the semiconductor chip and the semiconductor package are designed. Layout design that avoids problems caused by crosstalk cannot be performed. For this reason, crosstalk noise occurs between the circuit component or wiring arranged on the semiconductor chip and the circuit component or wiring arranged on the semiconductor package, and a low-quality semiconductor chip and semiconductor package are manufactured. Problems arise.

  This problem will be described with reference to the drawings. FIG. 13 is an explanatory diagram showing crosstalk that occurs between a semiconductor chip and a semiconductor package in the prior art. As shown in FIG. 13, the semiconductor circuit 1301 is bonded to the internal circuit or wiring 1303 of the semiconductor chip 1301, the semiconductor chip 1301 through the bonding portion 1305, and the printed circuit board (not shown). There is a problem that crosstalk occurs in the internal circuit of the package substrate 1302 or the wiring 1304.

  In order to solve the above-described problems caused by the prior art, the present invention provides a high-quality semiconductor chip and semiconductor package in which crosstalk noise between a circuit component arranged in a semiconductor chip and a circuit component arranged in a semiconductor package is unlikely to occur. It is an object of the present invention to provide a layout design program that can perform layout design, a recording medium that records the program, a layout design method, and a layout design apparatus.

  In order to solve the above-described problems and achieve the object, a layout design program, a recording medium storing the program, a layout design method, and a layout design apparatus according to the present invention can input an arbitrary area on a layout of a semiconductor chip. And identifying the type of circuit in the area, and associating information about the area with information about the type of circuit.

  According to the present invention, it is possible to associate an arbitrary region on the layout of the semiconductor chip with a circuit type in the region.

  In the above invention, the information about the associated area and the information about the type of circuit are acquired, and the information about the acquired area (hereinafter referred to as “first area information”) is the first on the layout of the semiconductor package. When designing the layout of the semiconductor package by converting into the area information of the second area, the second area information converted from the first area information is associated with the information on the circuit type on the layout of the semiconductor package. May be displayed.

  According to the present invention, when designing the layout of the semiconductor package, the information for determining an arbitrary region on the layout of the semiconductor chip is associated with the information for determining the type of circuit in the region, It can be displayed on the layout of the semiconductor package.

  A layout design program, a recording medium on which the program is recorded, a layout design method, and a layout design apparatus according to the present invention receive an input of an arbitrary area on the layout of a semiconductor package and specify a circuit type in the area In this case, the information on the area is associated with the information on the circuit type.

  According to the present invention, it is possible to associate an arbitrary region on the layout of the semiconductor package with a circuit type in the region.

  Further, in the above invention, information relating to the associated area and information relating to the type of circuit are obtained, and information relating to the obtained area (hereinafter referred to as “first area information”) is the first on the layout of the semiconductor chip. When designing the layout of the semiconductor chip by converting to the area information of the second area, the second area information converted from the first area information is associated with the information on the circuit type on the layout of the semiconductor chip. May be displayed.

  According to the present invention, when designing the layout of the semiconductor chip, the information for determining an arbitrary region on the layout of the semiconductor package is associated with the information for determining the type of circuit in the region, It can be displayed on the layout of the semiconductor chip.

  According to the layout design program, the recording medium storing the program, the layout design method, and the layout design apparatus according to the present invention, the crosstalk noise between the circuit component arranged in the semiconductor chip and the circuit component arranged in the semiconductor package As a result, it is possible to design a layout of a high-quality semiconductor chip and a semiconductor package that are less likely to cause the problem.

  Exemplary embodiments of a layout design program, a recording medium recording the program, a layout design method, and a layout design apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment)
(Hardware configuration of layout design device)
First, the hardware configuration of the layout design apparatus according to the embodiment of the present invention will be described. FIG. 1 is a block diagram showing a hardware configuration of a layout design apparatus according to an embodiment of the present invention.

  In FIG. 1, the layout design apparatus 100 determines the influence area of an aggressor circuit (a circuit that easily generates noise) or the influence area of a victim circuit (a circuit that is susceptible to noise) on a semiconductor chip or a semiconductor package (hereinafter, referred to as a noise circuit). A device such as a personal computer that performs a process for designing a layout of a semiconductor chip or a semiconductor package (hereinafter referred to as a “layout design process”), and includes a CPU 101, a ROM 102, a RAM 103, and an HDD (Hard disk drive) 104, HD (hard disk) 105, FDD (flexible disk drive) 106, FD (flexible disk) 107 as an example of a removable recording medium, display 108, I / O And (interface) 109, a keyboard 110, a mouse 111, a scanner 112, a printer 113 includes a respective component is connected through a bus 120.

  Here, the CPU 101 controls the entire layout design apparatus 100. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106 or reads data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a text, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to another device such as a user terminal device via the network 114. The I / F 109 serves as an interface between the network 114 and the layout design apparatus 100 and controls input / output of data from an external apparatus. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and captures image data into the layout design apparatus 100. The scanner 112 may have an OCR function. The printer 113 prints image data and text data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Functional configuration of layout design device)
Next, a functional configuration of the layout design apparatus 100 according to the embodiment of the present invention will be described. FIG. 2 is a block diagram showing a functional configuration of the layout design apparatus 100 according to the embodiment of the present invention. In FIG. 2, the layout design apparatus 100 includes an acquisition unit 201, a display unit 202, an input unit 203, a determination unit 204, a specification unit 205, an association unit 206, an output unit 207, a conversion unit 208, It is composed of

  In FIG. 2, the acquisition unit 201 performs information related to the layout of the first circuit (in the present embodiment, the semiconductor chip is the first circuit and the semiconductor package is the second circuit) in the marking process (hereinafter, referred to as “the first circuit”). (Referred to as first circuit information 220). In addition, the acquisition unit 201 acquires the marking information 230 in the layout design process.

  Here, the marking information 230 is information indicating the influence range of the aggressor circuit or the influence range of the victim circuit (hereinafter referred to as “specific region”) on the first circuit. , Output by the marking process. Specifically, the acquisition unit 201 realizes its function by causing the CPU 101 to execute programs stored in the ROM 102, the RAM 103, the HD 105, and the FD 107 shown in FIG.

  The display unit 202 displays the layout of the first circuit based on the first circuit information 220 acquired by the acquisition unit 201 in the marking process. In the marking process, the display unit 202 displays the specific area specified by the input unit 203 so as to overlap the layout of the first circuit based on the first circuit information 220 acquired by the acquisition unit 201. Note that an example of the layout of the first circuit displayed by the display unit 202 will be described later with reference to FIG. In addition, an example of the specific area displayed so as to overlap the layout of the first circuit will be described later with reference to FIG.

  Further, the display unit 202 displays a specific area specified by the marking information 230 converted by the conversion unit 208 at the layout position of the first circuit on the layout of the second circuit in the layout design process. . In the layout design process, the display unit 202 displays the circuit component input by the input unit 203 at the position on the layout of the second circuit that is also designated by the input unit 203. Note that an example of an arrangement position of the first circuit on the layout of the second circuit will be described later with reference to FIG. An example of the specific area displayed on the layout of the second circuit will be described later with reference to FIG. An example of the circuit component displayed on the layout of the second circuit will be described later with reference to FIG.

  Then, the display unit 202 displays information related to the result determined by the determination unit 204 in the layout design process (the quality of the layout generated by the layout design process). For example, the display unit 202 displays warning information when the determination unit 204 determines that the layout generated by the layout design process is defective. Specifically, the display unit 202 realizes its function by the display 108 shown in FIG. 1, for example. An example of the warning information displayed by the display unit 202 will be described later with reference to FIG.

  The input unit 203 accepts designation of a specific area (arbitrary area) for the layout of the first circuit in the marking process. Further, the input unit 203 accepts designation of a circuit component to be arranged on the layout of the second circuit and its position in the layout design process. Specifically, the input unit 203 realizes its function by the keyboard 110 and the mouse 111 shown in FIG. 1, for example.

  In the layout design process, the determination unit 204 determines whether the layout of the second circuit generated by the layout design process is good or bad. Specifically, whether or not the position of the circuit component placed on the layout of the second circuit specified by the input unit 203 overlaps with the specific area specified by the marking information 230 acquired by the acquisition unit 201. Judging.

  If the determination unit 204 determines that there is an overlap in the determination process, the determination unit 204 determines that the layout of the second circuit generated by the layout design process is defective. On the other hand, when it is determined that there is no overlap, it is determined that the layout of the second circuit generated by the layout design process is excellent. Specifically, the determination unit 204 realizes its function when the CPU 101 executes a program stored in, for example, the ROM 102, the RAM 103, the HD 105, and the FD 107 shown in FIG.

  In the marking process, the specifying unit 205 specifies whether the specific region specified by the input unit 203 is the influence region of the aggressor circuit or the influence region of the victim circuit. Specifically, the specifying unit 205 realizes its function when the CPU 101 executes a program stored in the ROM 102, RAM 103, HD 105, and FD 107 shown in FIG.

  In the marking process, the associating unit 206 generates marking information 230 in which the information related to the specific area for the layout of the first circuit specified by the input unit 203 is associated with the information related to the result specified by the specifying unit 205. . Specifically, the associating unit 206 realizes its function when the CPU 101 executes a program stored in the ROM 102, RAM 103, HD 105, and FD 107 shown in FIG.

  The output unit 207 outputs the marking information 230 generated by the associating unit 206 in the marking process. Further, in the layout design process, the output unit 207 outputs information (hereinafter referred to as second circuit information 240) related to the layout of the second circuit whose circuit component and its position are designated by the input unit 203. An example of the marking information 230 output by the output unit 207 will be described later with reference to FIG.

  An example of the second circuit information 240 output by the output unit 207 will be described later with reference to FIG. Specifically, the output unit 207 realizes its function when the CPU 101 executes a program stored in the ROM 102, RAM 103, HD 105, and FD 107 shown in FIG.

  The conversion unit 208 converts information regarding the specific area indicated in the marking information 230 acquired by the acquisition unit 201 in the layout design process. Specifically, in the marking information 230, the coordinate value indicated by the coordinate system of the first circuit is converted into the coordinate value by the coordinate system of the second circuit. Specifically, the conversion unit 208 realizes its function by causing the CPU 101 to execute programs stored in the ROM 102, the RAM 103, the HD 105, and the FD 107 shown in FIG.

(Example of layout of first circuit displayed on display unit 202)
Next, an example of the layout of the first circuit displayed by the display unit 202 will be described. FIG. 3 is an explanatory diagram showing an example of the layout of the first circuit displayed by the display unit 202.

  In FIG. 3, a circuit diagram 300 shows a layout of the first circuit based on the first circuit information 220. In the circuit diagram 300, circuit components 301 and 302 indicate an aggressor circuit or victim circuit (hereinafter referred to as a “specific circuit”) such as an AD conversion circuit among the circuit components arranged on the semiconductor chip. It is. Here, the first circuit information 220 is not limited to the layout in which the specific circuit is arranged as described above, but is related to the layout in which the area susceptible to noise or the area in which noise is easily generated is indicated. It may be.

(An example of a specific area displayed overlaid on the layout of the first circuit)
Next, an example of the specific area displayed so as to overlap the layout of the first circuit will be described. FIG. 4 is an explanatory diagram showing an example of the specific area displayed in a superimposed manner on the layout of the first circuit.

  A circuit diagram 300 shown in FIG. 4 is obtained by superimposing areas 401 and 402 designated by the input unit 203 on the circuit diagram 300 shown in FIG. In the circuit diagram 300 shown in FIG. 4, areas 401 and 402 indicate specific areas. Here, the region 401 has the name “ractA”, and its position and range can be specified by the coordinates (xa1, ya1) and the coordinates (xa2, ya2). The region 402 has the name “actB”, and the position and range can be specified by the coordinates (xb1, yb1) and the coordinates (xb2, yb2).

  An area 401 is indicated by a solid line, and it can be specified that the area is an influence range of the aggressor circuit. Further, the region 402 is indicated by a double line, and the region 401 can be identified as being in the affected range of the victim circuit. The areas 401 and 402 may be visually specified by a GUI operation by the user, or may be automatically specified based on the first circuit information 220 or the like.

(An example of the marking information 230 output by the output unit 207)
Next, an example of the marking information 230 output by the output unit 207 will be described. FIG. 5 is an explanatory diagram illustrating an example of the marking information 230 output by the output unit 207.

  In FIG. 5, marking information 230 indicates information for specifying the specific area described with reference to FIG. For example, it is shown that the position and range of a specific area having the name “ractA” can be specified by coordinates (xa1, ya1) and coordinates (xa2, ya2). In addition, “ag (aggressor)” is set for the specific area so that it can be specified that the area is the influence range of the aggressor circuit.

  Further, the position and range of the specific area having the name “ractB” can be specified by the coordinates (xb1, yb1) and the coordinates (xb2, yb2). Then, “vc (victim)” is set for the specific area so that it can be specified that it is within the influence range of the victim circuit.

  This marking information 230 is temporarily recorded in, for example, the RAM 103 shown in FIG. 1 by the output unit 207 in the marking process according to the procedure described later with reference to FIG. Then, the marking information 230 recorded in the RAM 103 is read from the RAM 103 by the acquisition unit 201 in a layout design process according to a procedure described later with reference to FIG. Note that the recording medium on which the marking information 230 is recorded is not limited to the RAM 103, and may be, for example, the HD 105 and the FD 107 shown in FIG.

(Example of arrangement position of first circuit on layout of second circuit)
Next, an example of the arrangement position of the first circuit on the layout of the second circuit will be described. FIG. 6 is an explanatory diagram illustrating an example of an arrangement position of the first circuit on the layout of the second circuit.

  In FIG. 6, a circuit diagram 600 shows a layout of the second circuit in a state where circuit components are not arranged. In the circuit diagram 600, a region 610 indicates a position and a range where the first circuit is arranged. This area 610 is visually designated by a GUI operation by the user, for example.

(Example of specific area displayed on layout of second circuit)
Next, an example of the specific area displayed on the layout of the second circuit will be described. FIG. 7 is an explanatory diagram illustrating an example of the specific area displayed on the layout of the second circuit.

  In the circuit diagram 600 shown in FIG. 7, from the state of the circuit diagram 600 shown in FIG. 6, a specific region (region 401) specified by the marking information 230 shown in FIG. , 402) is displayed. Here, the region 401 is indicated by a solid line, and it can be specified that the region is an influence range of the aggressor circuit. Further, the region 402 is indicated by a double line, and the region 401 can be identified as being in the affected range of the victim circuit.

  As described above, since the specific area of the first circuit is displayed on the layout of the second circuit, the user can grasp the specific area, and therefore the specific area of the first circuit is avoided. As described above, the layout design of the second circuit such as placement processing and wiring processing may be performed. As a result, it is possible to design a high-quality second circuit layout that is less likely to cause crosstalk between the circuit components arranged in the first circuit and the circuit components arranged in the second circuit.

(Example of circuit component displayed on the layout of the second circuit)
Next, an example of a circuit component displayed on the layout of the second circuit will be described. FIG. 8 is an explanatory diagram illustrating an example of a circuit component displayed on the layout of the second circuit.

  The circuit diagram 600 shown in FIG. 8 is changed from the state of the circuit diagram 600 shown in FIG. 6 by the input unit 203 so as to avoid specific regions (regions 401 and 402) in the region 610 provided in the circuit diagram 600. The input circuit components 801, 802, and 803 are displayed, and the layout of the high-quality second circuit is less likely to cause crosstalk.

(Example of warning information displayed by display unit 202)
Next, an example of warning information displayed by the display unit 202 will be described. FIG. 9 is an explanatory diagram illustrating an example of warning information displayed by the display unit 202.

In FIG. 9, warning information 900 is further superimposed on the circuit diagram 600 showing the layout of the second circuit displayed on the display unit 202 by the display unit 202.
The warning information 900 is displayed by the display unit 202 because the second circuit layout is determined to be defective by the determination process of the second circuit layout by the determination unit 204.

  This warning information 900 is displayed, for example, when the arrangement position of the circuit component designated by the input unit 203 overlaps or is close to the specific area of the first circuit. Note that the method for outputting the warning information 900 is not limited to the screen display as described above, and for example, sound may be output from a speaker or the like provided on the display 108.

(An example of the second circuit information 240 output by the output unit 207)
Next, an example of the second circuit information 240 output by the output unit 207 will be described. FIG. 10 is an explanatory diagram illustrating an example of the second circuit information 240 output by the output unit 207.

  FIG. 10 shows a layout of the second circuit based on the second circuit information 240 output by the output unit 207. In FIG. 10, circuit components 801, 802 and 803 input by the input unit 203 are displayed in the layout of the second circuit. The circuit components 801, 802, and 803 are arranged so as to avoid a specific area of the first circuit. As a result, the layout of the second circuit is a high-quality layout in which crosstalk hardly occurs.

(Marking procedure)
Next, the marking process procedure will be described. FIG. 11 is a flowchart illustrating an example of the procedure of the marking process.

  In FIG. 11, first, the acquisition unit 201 acquires the first circuit information 220 (step S1101). Next, the layout of the first circuit based on the first circuit information 220 acquired in step S1101 is displayed by the display unit 202 (step S1102).

  Next, designation of a specific area for the layout of the first circuit displayed in step S1102 is accepted by the input unit 203 (step S1103). Next, the display unit 202 displays the specific area designated in step S1103 so as to overlap the layout of the first circuit already displayed (step S1104).

  Next, the identification unit 205 identifies whether the specific area specified in step S1103 is the influence area of the aggressor circuit or the influence area of the victim circuit (step S1105). Then, the associating unit 206 generates marking information 230 in which the information related to the specific area specified in step S1103 and the information related to the result specified in step S1105 are associated (step S1106). Thus, the marking information 230 generated in step S1106 is output (step S1107), and the series of processing ends.

(Layout design process)
Next, the layout design process will be described. FIG. 12 is a flowchart illustrating an example of the procedure of the layout design process.

  In FIG. 12, first, the layout of the second circuit is displayed on the display unit 202 (step S1201). At this time, no circuit components are arranged on the layout of the second circuit, and only the arrangement position of the first circuit is designated. Next, the marking information 230 is acquired by the acquisition unit 201 (step S1202).

  Next, the conversion unit 208 converts the information related to the specific area indicated in the marking information 230 acquired in step S1202 (step S1203). Next, the display unit 202 displays the specific area specified by the marking information 230 converted in step S1203 at the position of the first circuit on the layout of the second circuit (step S1204). Next, the input unit 203 receives designation of a circuit component to be arranged on the layout of the second circuit and its position (step S1205).

  Next, the circuit component specified in step S1205 is displayed by the display unit 202 at the position specified in step S1205 on the layout of the second circuit (step S1206).

  Next, the determination unit 204 determines whether or not the layout of the second circuit generated by the layout design process is excellent (step S1207). If it is determined in step S1207 that the layout of the second circuit generated by the layout design process is excellent (step S1207: Yes), the output unit 207 outputs the second circuit information 240 (step S1207). S1210), a series of processing ends.

  On the other hand, when it is determined in step S1207 that the layout generated by the layout design process is defective (step S1207: No), warning information is displayed on the display unit 202 (step S1208), and the input unit 203 is displayed. Thus, the correction of the circuit component to be arranged on the layout of the second circuit and its position is accepted (step S1209), and the process returns to step S1206.

  As described above, according to the layout design program, the recording medium recording the program, the layout design method, and the layout design apparatus according to the embodiment of the present invention, the marking information output by the marking process is acquired, A specific area of the semiconductor chip specified by the marking information is displayed, and then the placement process / wiring process of the circuit components of the semiconductor package is performed so as to avoid the specific area of the semiconductor chip. Therefore, it is possible to design a layout of a high-quality semiconductor package in which crosstalk noise between the circuit component and the circuit component arranged in the semiconductor package is unlikely to occur.

  In the present embodiment, the semiconductor chip is the first circuit and the semiconductor package is the second circuit. Conversely, the semiconductor package may be the first circuit and the semiconductor chip may be the second circuit. In this case, after acquiring the marking information output by the marking process, displaying the specific area of the semiconductor package specified by the marking information, and then avoiding the specific area of the semiconductor package, the circuit component of the semiconductor chip By performing the placement processing and wiring processing, it is possible to design a layout of a high-quality semiconductor chip in which crosstalk noise between the circuit component placed on the semiconductor chip and the circuit component placed on the semiconductor package is unlikely to occur.

  The layout design method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer, a workstation, or a CAD. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

(Supplementary Note 1) An input step for accepting input of an arbitrary region on the layout of the semiconductor chip;
A specific step of identifying the type of circuit in the region input in the input step;
An associating step for associating information relating to the region with information relating to the type of circuit identified by the identifying step;
A layout design program for causing a computer to execute.

(Additional remark 2) The acquisition process which acquires the information regarding the said area | region linked | related by the said correlation process, and the information regarding the kind of said circuit,
A conversion step of converting information about the region acquired by the acquisition step (hereinafter referred to as “first region information”) into second region information on a layout of the semiconductor package;
When designing the layout of the semiconductor package, the second region information converted from the first region information by the conversion step on the layout of the semiconductor package and the type of the circuit acquired by the acquisition step A display step for displaying information related to
The layout design program according to appendix 1, wherein the program is executed by a computer.

(Supplementary Note 3) An input process for accepting input of an arbitrary region on the layout of the semiconductor package;
A specific step of identifying the type of circuit in the region input in the input step;
An associating step for associating information relating to the region with information relating to the type of circuit identified by the identifying step;
A layout design program for causing a computer to execute.

(Additional remark 4) The acquisition process which acquires the information regarding the said area | region linked | related by the said correlation process, and the information regarding the kind of said circuit,
A conversion step of converting information on the region acquired by the acquisition step (hereinafter referred to as “first region information”) into second region information on a layout of the semiconductor chip;
When designing the layout of the semiconductor chip, on the layout of the semiconductor chip, the second region information converted from the first region information by the conversion step and the type of the circuit acquired by the acquisition step A display step for displaying information related to
4. The layout design program according to appendix 3, wherein the program is executed by a computer.

(Additional remark 5) The computer-readable recording medium which recorded the layout design program as described in any one of additional remark 1-4.

(Appendix 6) An input process for receiving an input of an arbitrary area on the layout of the semiconductor chip;
A specific step of identifying the type of circuit in the region input in the input step;
An associating step for associating information relating to the region with information relating to the type of circuit identified by the identifying step;
A layout design method characterized by including:

(Appendix 7) An input process for receiving an input of an arbitrary region on the layout of the semiconductor package;
A specific step of identifying the type of circuit in the region input in the input step;
An associating step for associating information relating to the region with information relating to the type of circuit identified by the identifying step;
A layout design method characterized by including:

(Supplementary Note 8) Input means for receiving input of an arbitrary region on the layout of the semiconductor chip;
Specifying means for specifying the type of circuit in the region input to the input means;
Associating means for associating information relating to the area with information relating to the type of circuit identified by the identifying means;
A layout design apparatus comprising:

(Supplementary Note 9) Input means for receiving input of an arbitrary region on the layout of the semiconductor package;
Specifying means for specifying the type of circuit in the region input to the input means;
Associating means for associating information relating to the area with information relating to the type of circuit identified by the identifying means;
A layout design apparatus comprising:

  As described above, the layout design program, the recording medium on which the program is recorded, the layout design method, and the layout design apparatus according to the present invention are useful for layout design work of a semiconductor integrated circuit, and in particular, generate crosstalk noise. It is suitable for use in layout design work of high-quality semiconductor integrated circuits that are unlikely to cause any problems.

It is a block diagram which shows the hardware constitutions of the layout design apparatus concerning embodiment of this invention. It is a block diagram which shows the functional structure of the layout design apparatus concerning embodiment of this invention. It is explanatory drawing which shows an example of the layout of the 1st circuit displayed by the display part. It is explanatory drawing which shows an example of the specific area | region displayed superimposed on the layout of the 1st circuit. It is explanatory drawing which shows an example of the marking information output by the output part. It is explanatory drawing which shows an example of the arrangement position of the 1st circuit on the layout of a 2nd circuit. It is explanatory drawing which shows an example of the specific area | region displayed on the layout of the 2nd circuit. It is explanatory drawing which shows an example of the circuit component displayed on the layout of a 2nd circuit. It is explanatory drawing which shows an example of the warning information displayed by the display part. It is explanatory drawing which shows an example of the 2nd circuit information output by the output part. It is a flowchart which shows an example of the procedure of a marking process. It is a flowchart which shows an example of the procedure of a layout design process. It is explanatory drawing which shows the crosstalk which arises with the semiconductor chip and semiconductor package in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Layout design apparatus 201 Acquisition part 202 Display part 203 Input part 204 Judgment part 205 Identification part 206 Association part 207 Output part 220 1st circuit information 230 Marking information 240 2nd circuit information

Claims (7)

A first acquisition step of acquiring first circuit information of the first semiconductor out of the combined first semiconductor and second semiconductor ;
An input step of receiving an input of an arbitrary region on the layout of the first semiconductor;
A specifying step of specifying the type of the first circuit included in the first circuit information in the region;
Associating information about the region with information about the type of the first circuit, and generating marking information;
A second acquisition step of acquiring second circuit information of the second semiconductor;
An evaluation step of evaluating a layout of the second circuit included in the second circuit information based on the region acquired from the marking information and the type of the first circuit;
A layout design program for causing a computer to execute.   The layout design program according to claim 1, wherein the first semiconductor and the second semiconductor include a semiconductor chip or a semiconductor package.   The layout design program according to claim 1 or 2, wherein the specifying step specifies whether the first circuit is an aggressor circuit or a victim circuit.   The said evaluation process evaluates the layout of the said 2nd circuit as a defect when the said 2nd circuit is contained in the said area | region acquired from the said marking information, or when it adjoins. The layout design program according to any one of the above. Computer readable recording medium recording a layout design program according to claim 1 or 2. A computer comprising an acquisition means, an input means, an identification means, an association means, and an evaluation means,
A first acquisition step of acquiring first circuit information of the first semiconductor out of the combined first semiconductor and second semiconductor by the acquisition means;
An input step of receiving an input of an arbitrary region on the layout of the first semiconductor by the input means;
A specifying step of specifying the type of the first circuit included in the first circuit information in the region by the specifying means;
An association step of associating information relating to the region with information relating to the type of the first circuit by the association means, and generating marking information;
By the acquisition unit, a second acquisition step of acquiring a second circuit information of said second semiconductor,
An evaluation step of evaluating a layout of the second circuit included in the second circuit information based on the region acquired from the marking information and the type of the first circuit by the evaluation means;
The layout design method characterized by performing. Obtaining means for obtaining first circuit information of a first semiconductor and second circuit information of a second semiconductor coupled to the first semiconductor ;
Input means for receiving an input of an arbitrary region on the layout of the first semiconductor;
Specifying means for specifying the type of the first circuit included in the first circuit information in the region;
Associating means for associating information on the region with information on the type of the first circuit, and generating marking information;
Evaluation means for evaluating the layout of the second circuit included in the second circuit information based on the region acquired from the marking information and the type of the first circuit;
A layout design apparatus comprising:

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