JP4984998B2 - Overcurrent detection circuit, DC-DC converter, and overcurrent detection method - Google Patents

Description

  The present invention relates to a technique for reducing current consumption of an electronic circuit.

Even in an electronic circuit such as a DC-DC converter, a low current consumption is strongly demanded for an electronic circuit used for a portable device or the like.
FIG. 3 shows a first circuit example of a conventional overcurrent detection circuit that can be used in a DC-DC converter or the like. Note that the circuit shown in the figure is also cited as a prior art in Patent Document 1.

  In FIG. 3, FETs M0 and M1 are both n-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Here, the FET M0 is a main FET in the output stage of the DC-DC converter, and drives the driving load ZL. The drain current Id0 of the FET M0 flows from the power supply line VD to the ground (ground potential) through the driving load ZL and the FET M0. Further, the FET M1 has a function as a reference load, and a current from the power supply line VDD by a reference current source Iref (constant current value is also referred to as Iref), which is a constant current source, flows to the ground as a drain current Id1. . That is, Id1 = Iref.

In this circuit, for simplicity of explanation, the gate potential VG is set to the same level in both the FETs M0 and M1, and the mirror ratio between the FET M0 and the FET M1 is set to 1.
Here, when the relationship between the drain current Id0 of the FET M0 and the drain current Id1 of the FET M1 is Id0> Id1 (= Iref), that is, the relationship between the drain potential Vd0 of the FET M0 and the drain potential Vd1 of the FET M1 is Vd0> Vd1. In this case, the drain current Id0 of the FET M0 is determined as an overcurrent.

  The comparator COMP compares the drain voltage Vd0 of the FET M0 with the reference voltage Vd1 generated by the FET M1. Here, when Vd0 <Vd1 changes to Vd0> Vd1, that is, when the drain current Id0 of the FET M0 exceeds Iref, the output is shifted from the “H” level to the “L” level, and this overcurrent Announce the condition.

  The value of Iref, which is the overcurrent determination threshold in the overcurrent detection circuit shown in FIG. 3, is determined by the relative characteristics of the FET M0 and the FET M1. Here, if the FETM0 and the FETM1 are formed on the same semiconductor substrate, for example, if the tendency of fluctuations in the electrical characteristics of both of them is made uniform, this determination threshold is stable against disturbances such as temperature fluctuations. It has the characteristic that it has high property.

  Next, FIG. 4 will be described. This figure shows a second circuit example of a conventional overcurrent detection circuit that can be used in a DC-DC converter or the like. The circuit shown in the figure implements the invention according to a patent application (Japanese Patent Application No. 2005-274786) filed prior to the present application by the applicant of the present application.

  In FIG. 4, the main MOSFET Mm, the reference MOSFET Mr, and the FETs M01 and M02 are all n-channel MOSFETs. Further, the FETs M03 and M04 are both p-channel MOSFETs.

In this circuit, for simplicity of explanation, the main MOSFET Mm and the reference M
The gate potential Vg is fixed at the same level in both the OSFET Mr and the mirror ratio between the main MOSFET Mm and the reference MOSFET Mr is 1.

The circuit in FIG. 4 detects whether or not the value of the current flowing between the drain and source of the main MOSFET Mm is larger than a predetermined value.
In FIG. 4, a comparator (comparator) 100 is configured to include a differential amplifier unit including FETs M01 and M02 and FETs M03 and M04, and a constant current source Iref that supplies a bias current to the differential amplifier unit. Yes.

  Both gate terminals of the FETs M01 and M02 and the drain terminal of the FET M01 are collected and connected to the drain terminal of the FET M03. Therefore, the FETs M01 and M02 are current mirrors that match the drain current of the FET M02 with the drain current of the FET M01. The drain terminal of the FET M02 is connected to the drain terminal of the FET M04, and this connection point is the output Vout of the differential amplifier. From this output Vout, the potential difference between the gate terminals of the FETs M03 and M04, which are the two inputs of the differential amplifier, is amplified and output.

  The current from the power supply line VDD by the constant current source Iref is divided into two and input to the drain terminals of the FETs M03 and M04. Both source terminals of the FETs M01 and M02 are connected to a drain terminal of a reference MOSFET Mr that functions as a reference load.

  FETs M03 and M04 constitute an input differential pair. The detection voltage Vin is applied to the gate terminal of the FET M04 that is the inverting input in the input differential pair. This detection voltage Vin is a drain-source voltage of the main MOSFET Mm. Here, since the source terminal of the main MOSFET Mm is connected to the ground (ground potential), the detection voltage Vin becomes a voltage value corresponding to the current value flowing between the drain and source of the main MOSFET Mm.

  On the other hand, the reference voltage Vr is applied to the gate terminal of the FET M03 which is the non-inverting side input in the input differential pair. The reference voltage Vr is a voltage obtained corresponding to the reference current Iref, and is a reference when the bias current supplied from the constant current source Iref to the above-described differential amplifier is supplied as a drain current to the reference MOSFET Mr. This is the drain-source voltage of MOSFET Mr. The source terminal of the reference MOSFET Mr is connected to the ground (ground potential).

  The comparator 100 compares the detection voltage Vin with the reference voltage Vr. Here, when Vin> Vr, the output voltage Vout becomes the “L” level. This indicates that the current value flowing between the drain and source of the main MOSFET Mm is larger than a predetermined value.

The circuit of FIG. 4 operates as described above. Here, if the main MOSFET Mm and the reference MOSFET Mr are formed on the same semiconductor substrate, for example, if the tendency of fluctuations in both electrical characteristics with respect to disturbances is made uniform, the dependence on the drive voltage and ambient temperature is small. Current determination can be performed. Further, in the circuit of FIG. 4, since the bias current to the differential amplifier supplied by the constant current source Iref is supplied to the reference MOSFET Mr, a dedicated current source for the reference MOSFET Mr is unnecessary and consumed. The power is reduced.
JP 2004-140423 A (paragraphs [0005]-[0006], FIG. 5)

  In the circuit of FIG. 3, the reference voltage Vd1 cannot be a negative voltage because it is generated by flowing the constant current Iref from the reference current source to the FET M1 that is the reference load. Also in the circuit of FIG. 4, the reference voltage Vr cannot be a negative voltage because it is generated by passing the bias current of the differential amplifier through the reference MOSFET Mr. Therefore, the direction of the current that can detect the overcurrent using the circuits of FIGS. 3 and 4 is limited to the positive direction (the direction in which the main MOSFET Mm flows from the drain terminal to the source terminal). For this reason, for example, in a DC-DC converter, an application for limiting the peak value of the inductor current (for detecting a forward current of a MOSFET that is a high-side switching element) and an application for detecting the reverse current (for a low-side switching element). The circuit shown in FIG. 4 can be used for detecting the forward current of a certain MOSFET, etc., but for applications that limit the bottom value of the inductor current (for detecting the reverse current of a MOSFET that is a low-side switching element), etc. I can not use it.

  In addition, in the circuit of FIG. 3, since it is necessary to prepare the constant current source Iref, there is a problem relating to low consumption. That is, in the above description, the mirror ratio is set to 1. However, even if the mirror ratio M (= drain current of the FET M0 / drain current of the FET M1) is increased to reduce Iref, there is a limit to the size of the mirror ratio. If the current flowing through the main FET FETM0 is a large current, the constant current Iref must be set to a certain level. The circuit of FIG. 4 solves the problem related to the constant current Iref, and it is necessary to solve this also in the present invention.

  The present invention has been made in view of the above-described problems, and a problem to be solved is to provide a new technique capable of performing overcurrent determination with low power consumption.

  An overcurrent detection circuit according to one aspect of the present invention includes a differential amplifier that amplifies a potential difference between two inputs, and a reference load that obtains a voltage corresponding to the reference current when a reference current is passed. The level shift voltage, which is a voltage obtained by flowing at least a part of the bias current flowing through the differential amplifier to the reference load and passing the current through the reference load, is used for overcurrent detection. A voltage obtained by shifting the level of the detection voltage corresponding to the magnitude of the target current is input to one of the two inputs of the differential amplifier, and a predetermined reference voltage is input to the differential amplifier. It is characterized by inputting to the other of the two inputs, and the above-described problems are solved by this feature.

  In the overcurrent detection circuit according to the present invention, the reference load is a first MOSFET whose gate potential when obtaining the level shift voltage is fixed, and the current that is the target of the overcurrent detection is The drain current of the second MOSFET can be used.

  According to the above configuration, the result of the magnitude comparison between the voltage obtained by shifting the level of the detection voltage by the level shift voltage and the predetermined reference voltage can be obtained from the output of the differential amplifier. From this result, it can be determined whether or not the current to be detected is in an overcurrent state. Here, according to the above configuration, since at least a part of the bias current flowing in the differential amplifying unit is caused to flow to the reference load, a dedicated current source for flowing current to the reference load is provided. It is unnecessary. As a result, the total current consumption in the entire circuit is reduced.

  In the above-described overcurrent detection circuit according to the present invention, the drain current that is the target of the overcurrent detection can be a current that flows from the source terminal to the drain terminal of the second MOSFET. That is, in the present invention, since the magnitude of the voltage obtained by shifting the level of the detection voltage by the level shift voltage and the predetermined reference voltage is compared, overcurrent detection is performed for the reverse drain current of the second MOSFET. be able to.

At this time, the predetermined reference voltage can be a ground potential. By doing so, a configuration for obtaining a reference voltage having a potential different from the ground potential becomes unnecessary.
In the above-described overcurrent detection circuit according to the present invention, the first MOSFET and the second MOSFET can be formed on a single semiconductor substrate.

  In this way, since the tendency of fluctuations in the electrical characteristics with respect to the disturbance between the first MOSFET and the second MOSFET is uniform, it is possible to perform overcurrent determination with little dependency on the drive voltage and ambient temperature. become.

  The above-described overcurrent detection circuit according to the present invention further includes an amplifying unit that amplifies the output from the differential amplifying unit, and a bias that is supplied to the differential amplifying unit to obtain the level shift voltage. A configuration may be adopted in which at least a part of a bias current that is supplied to the amplifying unit is supplied to the reference load together with at least a part of the current.

  In this way, since the hysteresis characteristic can be realized by utilizing the fact that the current flowing from the amplifier to the reference load changes according to the output of the differential amplifier, the circuit after the overcurrent detection result is obtained Malfunction is prevented.

  Further, in the overcurrent detection circuit according to the present invention described above, the current flowing through the first MOSFET in order to obtain the level shift voltage is applied to the first MOSFET during a period in which the first MOSFET is in an off state. Further, it can be configured to further include bypass means for bypassing.

Here, the bypass means may be a third MOSFET that is turned on in a period in which the second MOSFET is in an off state.
According to this configuration, a flow path for the bias current that flows in the differential amplifier section is ensured during the period in which the second MOSFET is in the off state.

  A DC-DC using the overcurrent detection circuit according to the present invention described above, wherein the overcurrent detection target by the overcurrent detection circuit is the drain current of the MOSFET of the output stage that drives the load. The converter also relates to the present invention.

  In the DC-DC converter having the above-described configuration, it is possible to detect that the drain current of the MOSFET of the output stage that drives the load is in an overcurrent state, and to stop the operation of the MOSFET. Converter failure is prevented. Here, by using the above-described overcurrent detection circuit according to the present invention, the total current consumption in the entire circuit is reduced.

  Further, when a reference current is supplied, at least a part of a bias current that is supplied to a differential amplifier that amplifies a potential difference between two inputs is supplied to a reference load that obtains a voltage corresponding to the reference current. A voltage obtained by shifting the level of the detection voltage corresponding to the magnitude of the current that is the target of overcurrent detection with a level shift voltage that is a voltage obtained by flowing the current through the reference load is supplied to the differential amplification unit. An overcurrent detection method is also provided according to the present invention, wherein the input is input to one of the two inputs, and a predetermined reference voltage is input to the other of the two inputs of the differential amplifier. With this method as well, the above-described problems are solved as a result of the same effects as the above-described overcurrent detection circuit according to the present invention.

  According to the present invention, it is possible to perform an overcurrent determination with respect to the above-described reverse current with low power consumption.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, FIG. 1 will be described. This figure shows the configuration of an overcurrent detection circuit embodying the present invention.

1, the same components as those shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
The circuit in FIG. 4 detects whether the current value in the reverse direction (direction flowing from the source terminal to the drain terminal) flowing between the drain and source of the main MOSFET Mm is larger than a predetermined value.

  The circuit of FIG. 1 does not apply the detection voltage Vin to the inverting side input (gate terminal of the FET M04) of the input differential pair constituted by the FETs M03 and M04 in the comparator 100, but the inverting side input is grounded (grounded). The detection voltage Vin is applied to the source terminal instead of connecting the point connected to the potential) and the source terminal of the reference MOSFET Mr functioning as a reference load to the ground (ground potential). 4 is different from the circuit shown in FIG. 4 in that the drain terminal of the main MOSFET Mm is connected.

  In the circuit of FIG. 1, the bias current supplied from the constant current source Iref to the differential amplifier unit composed of the FETs M01 and M02 and the FETs M03 and M04 flows from the drain terminal to the source terminal of the reference MOSFET Mr, thereby causing the level shift voltage Vls. Occurs between the drain and source of the reference MOSFET Mr. Accordingly, the non-inverting side input (the gate terminal of the FET M03) of the input differential pair described above is the sum of the detection voltage Vin (the drain-source voltage of the main MOSFET Mm) and the level shift voltage Vls described above (detection). A voltage obtained by shifting the level of the voltage Vin by the level shift voltage Vls) is applied.

  As described above, in the circuit of FIG. 1, the inverting side input of the input differential pair is connected to the ground. Therefore, the comparator 100 compares the voltage obtained by shifting the level of the detection voltage Vin with the level shift voltage Vls with the ground potential (ground potential).

  Here, when Vin + Vls <0, the comparator 100 sets the output voltage Vout to the “L” level. That is, the comparator 100 sets the output voltage Vout to the “L” level when Vin <−Vls. In other words, this indicates a case where the reverse current flowing through the main MOSFET Mm (current flowing in the main MOSFET Mm from the source terminal to the drain terminal), which is a current corresponding to Vin, is larger than a predetermined value.

  The circuit of FIG. 1 operates as described above. Here, for example, the main MOSFET Mm and the reference MOSFET Mr are formed on the same semiconductor substrate, so that the tendency of fluctuations in the electrical characteristics of both of them with respect to the disturbance is made uniform. Then, it is possible to perform overcurrent determination with little dependency on the driving voltage and the ambient temperature. Further, since the circuit of FIG. 1 allows the bias current to the differential amplifier supplied by the constant current source Iref to flow to the reference MOSFET Mr having a function as a reference load, a dedicated circuit for the reference MOSFET Mr is provided. A current source is unnecessary and power consumption is reduced.

Next, FIG. 2 will be described. FIG. 1 shows a part of the configuration of a DC-DC converter 1 that performs output overcurrent detection using an overcurrent detection circuit that implements the present invention.
In the DC-DC converter 1 shown in FIG. 2, the overcurrent is detected in order to detect the bottom value of the inductor current in the synchronous rectification type DC-DC converter from the low-side MOSFET and determine whether the bottom value reaches a predetermined value. A detection circuit is used.

  In FIG. 2, the low-side MOSFET Mn, the reference MOSFET Mr serving as a reference load, the bypass MOSFET Mr ′, and the FETs M11, M12, and M16 are all n-channel MOSFETs. The high side MOSFET Mp and the FETs M13, M14, M15, M17, and M18 are all p-channel MOSFETs.

  First, the comparator (comparator) 10 will be described. The comparator 10 includes FETs M11, M12, M13, M14, M15, M16, M17, and M18, a constant current source Iref ', and an output buffer 19.

  All gate terminals of the FETs M18, M15, and M17 and the drain terminal of the FET M18 are connected to form a current mirror. Here, all the source terminals of the FET M18, FET M15, and FET M17 are connected to the power supply line VDD, and further, the constant current source Iref ′ is connected between the drain terminal of the FET M18 and the ground. Since the drain current Ib is determined by the constant current source Iref ′, both the FETs M15 and M17 can be regarded as constant current sources that allow a constant drain current to flow.

  Further, the FET M11, M12, M13, and M14 constitute a differential amplifier. A drain current of the FET M15, which is a constant current, flows as a bias current through the differential amplifier.

  The FETs M13 and M14 constitute an input differential pair. The gate terminal of the FET M13, which is the non-inverting side input in the input differential pair, is the non-inverting side input of the comparator 10, and the drain terminal of the reference MOSFET Mr is connected thereto. On the other hand, the gate terminal of M14, which is the inverting side input in the input differential pair, is the inverting side input of the comparator 10, to which the output terminal of the inverter INV1 is connected. The constant current from the FET M15 is divided into two and input to the source terminals of the FETs M13 and M14.

  Both gate terminals of the FETs M11 and M12 and the drain terminal of the M11 are combined and connected to the drain terminal of the FET M13. Therefore, the FETs M11 and M12 are current mirrors that match the drain current of the FET M12 with the drain current of the FET M13. The drain terminal of the FET M12 is connected to the drain terminal of the FET M14, and this connection point is the output of this differential amplifier. This output is led to the gate terminal of the FET M16.

The FETs M16 and M17 are intermediate amplification units that amplify the output from the differential amplification unit described above.
The FET M16 receives the output of the differential amplifier described above and inverts this output. Since the drain terminal of the FET M16 is connected to the drain terminal of the FET M16, the drain current of the FET M17 that is a constant current flows through the FET M16 when the FET M16 is in the ON state.

The drain terminal of the FET M16 is also connected to the input of the output buffer 19. The output of the output buffer 19 becomes the output Vout of the comparator 10.
Next, the DC-DC converter 20 will be described.

In the DC-DC converter 20, the high-side MOSFET Mp and the low-side MOSFET Mn in the output stage that drives the load are connected in series, and the high-side MOSFET Mp,
The low-side MOSFET Mn is inserted in this order between the power supply line Vin and the ground.

  The gate terminals of the high-side MOSFET Mp and the low-side MOSFET Mn are connected to the controller 21, respectively. When the controller 21 changes the voltage level of the control signal applied thereto to “H” level or “L” level, the on / off state of the high-side MOSFET Mp and the low-side MOSFET Mn alternately according to the change of this level. Switch.

  In the circuit of FIG. 2, the state of the reverse current (current flowing in the direction from the source terminal to the drain terminal) of the low-side MOSFET Mn is detected. Therefore, the drain potential of the low-side MOSFET Mn becomes a detection voltage (detection voltage Vin in FIG. 1) corresponding to the magnitude of the current that is the target of current detection.

Note that a series connection of LCs connected in parallel between the drain and source of the low-side MOSFET Mn is a filter for smoothing the output of the DC-DC converter 1.
Next, a connection part between the comparator 10 and the DC-DC converter 20 will be described.

  The source terminals of the FETs M11 and M12 and the source terminal of the FET M16 in the comparator 10 are combined and connected to the drain terminal of the reference MOSFET Mr. Therefore, when the FET M16 is in the ON state, the bias currents of the differential amplification unit and the intermediate amplification unit described above are collected and flowed as the drain current in the reference MOSFET Mr. In addition, when the FET M16 is in the OFF state, the bias current of the differential amplifier is passed as the drain current to the reference MOSFET Mr.

  That is, the bias currents flowing through the differential amplification unit and the intermediate amplification unit described above are collected and passed to the reference MOSFET Mr as the reference current Iref, thereby generating the level shift voltage Vls between the drain and source of the reference MOSFET Mr.

  The controller 21 applies the same control signal to the gate terminal of the reference MOSFET Mr as well as the input terminal of the inverter INV1 to the gate terminal of the low-side MOSFET Mn.

  The bypass MOSFET Mr ′ flows out from the comparator 10 and is provided for bypassing the reference current Iref flowing to the reference MOSFET Mr to obtain the level shift voltage Vls during a period in which the reference MOSFET Mr is in an off state, and securing the flow path. Yes.

  The bypass MOSFET Mr ′ has a drain terminal connected to the drain terminal of the reference MOSFET Mr, and a source terminal connected to the ground. The gate terminal of the bypass MOSFET Mr ′ is connected to the output terminal of the inverter INV2, and the input terminal of the inverter INV2 is connected to the gate terminal of the reference MOSFET Mr. Accordingly, since the on / off state of the bypass MOSFET Mr ′ is opposite to the on / off state of the reference MOSFET Mr, a path for the reference current Iref when the reference MOSFET Mr is off is secured.

The DC-DC converter 1 is configured as described above.
Next, the operation of detecting the bottom value of the inductor current in the DC-DC converter 1 will be described.

First, it is assumed that the low-side MOSFET Mn is in an off state, that is, the voltage level of the control signal applied by the controller 21 to the gate terminal of the low-side MOSFET Mn is “L” level. In this case, the output signal of the inverter INV1, that is, the “H” level signal is applied to the inverting input of the comparator 10.

  In this case, the reference MOSFET Mr is in an off state, and the bypass MOSFET Mr 'is in an on state. At this time, the voltage generated in the bypass MOSFET Mr ′ by the reference current Iref flowing out from the comparator 10 (that is, the voltage applied to the non-inverting side input of the comparator 10) is higher than the “H” level output signal from the inverter INV1. A bypass MOSFET Mr ′ is formed so as to be sufficiently small.

  At this time, the output of the differential amplifier in the comparator 10 is at “L” level, so the output of the intermediate amplifier in the comparator 10 is at “H” level. Therefore, the output Vout of the comparator 10 becomes “H” level.

  Here, consider a case where the voltage level of the control signal applied to the gate terminal of the low-side MOSFET Mn by the controller 21 transitions from the “L” level to the “H” level. In this case, an “L” level output signal (ie, ground potential) from the inverter INV1 is applied to the inverting side input of the comparator 10 as a predetermined reference voltage for size comparison.

  At this time, the reference MOSFET Mr is turned on by applying a voltage of “H” level to the gate terminal, and the bypass MOSFET Mr ′ is turned off by the action of the inverter INV2. Then, since the reference current Iref flowing out from the comparator 10 flows through the reference MOSFET Mr and the level shift voltage Vls is generated, the non-inverting side input of the comparator 10 includes the drain-source voltage of the low side MOSFET Mn and the level shift voltage Vls. A sum voltage (a voltage obtained by shifting the level of the drain-source voltage of the low-side MOSFET Mn by the level shift voltage Vls) is applied. Therefore, the comparator 10 compares this sum voltage with the ground potential.

  Here, for example, immediately after the low-side MOSFET Mn transitions to the ON state, if the amount of the drain current Idn flowing in the direction from the source terminal to the drain terminal is large, the above-described sum voltage becomes smaller than the ground potential. The output of the differential amplifier in FIG. At this time, the output of the intermediate amplifying unit in the comparator 10 is at the “H” level, so the output Vout of the comparator 10 is at the “H” level.

  On the other hand, when the above-described sum voltage becomes larger than the ground potential, that is, when the amount of the drain current Idn described above becomes small, the output of the differential amplifier in the comparator 10 is at the “H” level. It becomes. At this time, since the output of the intermediate amplifying unit in the comparator 10 is at the “L” level, the output Vout of the comparator 10 is at the “L” level.

  Therefore, when the output signal Vout of the comparator 10 becomes “H” level when the control signal applied to the low-side MOSFET Mn by the controller 21 is “H” level, the bottom value of the inductor current in the DC-DC converter 1 is predetermined. It can be determined that the value has been exceeded.

In the circuit of FIG. 2, when the above-described sum voltage becomes larger than the ground potential, the output of the differential amplifying unit in the comparator 10 becomes “H” level. Then, since the FET M16 is turned on, the reference current Iref output from the comparator 10 increases. As the reference current Iref increases, the level shift voltage Vls increases, but this further increases the above-described sum voltage. As a result, the output Vout of the comparator 10 switched to the “H” level is maintained. It will contribute to the direction to do. That is, it is possible to realize a hysteresis characteristic and to have a function of preventing malfunction of the circuit.

  The DC-DC converter 1 shown in FIG. 2 operates as described above. In this case, the main MOSFET Mn and the reference MOSFET Mr are formed on the same semiconductor substrate, for example, so that the tendency of fluctuations in both electrical characteristics with respect to disturbance is made uniform. Then, it is possible to perform overcurrent determination with little dependency on the driving voltage and the ambient temperature. Also in the circuit of FIG. 2, since a bias current to the differential amplifier supplied by the FET M15 that can be regarded as a constant current source is supplied to the reference MOSFET Mr, a dedicated current source for the reference MOSFET Mr is provided. It is unnecessary and power consumption is reduced.

As mentioned above, although embodiment of this invention was described, this invention is not limited to each embodiment mentioned above, A various improvement and change are possible within the range which does not deviate from the summary of this invention.
For example, although the MOSFET is used in the above-described embodiment, a similar circuit can be configured using a junction FET or the like.

  In the circuits of FIGS. 1 and 2, all of the reference current Iref flowing out from the comparator 10 or 100 is supplied to the reference MOSFET Mr. However, if the reference MOSFET Mr is a constant current, a part of the reference current Iref is supplied. You may make it flow. That is, in the circuit of FIG. 1, for example, a constant current obtained by diverting a part of the bias current of the operational amplifier unit including FETs M01, M02, M03, and M04 may be supplied to the reference MOSFET Mr. In the circuit of FIG. 2, for example, all or part of the bias current of the operational amplifier unit composed of FETs M11, M12, M13, and M14 and all or part of the bias current of the intermediate amplifier unit composed of FETs M16 and M17 are combined. A constant current obtained by dividing the combined current may be supplied to the reference MOSFET Mr.

It is a figure which shows the structure of the overcurrent detection circuit which implements this invention. It is a figure which shows a part of structure of the DC-DC converter which performs the overcurrent detection of an output using the overcurrent detection circuit which implements this invention. It is a figure which shows the 1st circuit example of the conventional overcurrent detection circuit. It is a figure which shows the 2nd circuit example of the conventional overcurrent detection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC-DC converter 10,100, COMP comparator 19 Output buffer 20 DC-DC conversion part 21 Controller L Inductor C Capacitor INV1, INV2 Inverter Iref, Iref 'Current source M0, M1, M01, M02, M11, M12, M16,
Mm, Mn, Mr, Mr 'n-channel MOSFET
M03, M04, M13, M14, M15,
M17, M18, Mp p-channel MOSFET
ZL drive load

Claims (10)

A differential amplifier for amplifying the potential difference between the two inputs;
A reference load that provides a voltage corresponding to the reference current when a reference current is passed;
Have
Flowing at least a portion of the bias current flowing through the differential amplifier through the reference load;
A voltage obtained by shifting the level of the detection voltage corresponding to the magnitude of the current that is the target of overcurrent detection with a level shift voltage that is a voltage obtained by flowing the current through the reference load, Input to one of the two inputs
A predetermined reference voltage is input to the other of the two inputs of the differential amplifier;
An overcurrent detection circuit characterized by that. The reference load is a first MOSFET having a fixed gate potential when obtaining the level shift voltage,
The current that is the target of overcurrent detection is the drain current of the second MOSFET.
The overcurrent detection circuit according to claim 1.   The overcurrent detection circuit according to claim 2, wherein the drain current that is a target of the overcurrent detection is a current that flows from a source terminal to a drain terminal of the second MOSFET.   The overcurrent detection circuit according to claim 3, wherein the predetermined reference voltage is a ground potential.   The overcurrent detection circuit according to claim 2, wherein the first MOSFET and the second MOSFET are formed on a single semiconductor substrate. An amplifier that amplifies the output from the differential amplifier;
In order to obtain the level shift voltage, at least a part of the bias current that flows to the amplifying unit is used together with at least a part of the bias current that flows to the differential amplifying unit, Shed
The overcurrent detection circuit according to claim 1.   The circuit further comprises bypass means for bypassing a current flowing through the first MOSFET to obtain the level shift voltage from the first MOSFET during a period in which the first MOSFET is off. Item 3. The overcurrent detection circuit according to Item 2.   8. The overcurrent detection circuit according to claim 7, wherein the bypass means is a third MOSFET that is turned on during a period in which the second MOSFET is in an off state. Using the overcurrent detection circuit according to any one of claims 1 to 8,
The target of overcurrent detection by the overcurrent detection circuit is the drain current of the MOSFET of the output stage that drives the load.
The DC-DC converter characterized by the above-mentioned. When a reference current is supplied, at least a part of a bias current that is supplied to a differential amplifier that amplifies a potential difference between two inputs is supplied to a reference load that obtains a voltage corresponding to the reference current.
A voltage obtained by shifting the level of the detection voltage corresponding to the magnitude of the current that is the target of overcurrent detection with a level shift voltage that is a voltage obtained by flowing the current through the reference load, Input to one of the two inputs
A predetermined reference voltage is input to the other of the two inputs of the differential amplifier;
An overcurrent detection method characterized by the above.