JP4983220B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor device excellent in electrostatic discharge resistance and a method for manufacturing the same.

Conventionally, in a method for manufacturing a nitride semiconductor device, after the nitride semiconductor layer is formed, various treatments are performed on the surface of the formed nitride semiconductor layer (for example, Patent Documents 1 to 5). Reference 3).
In the manufacturing method disclosed in Patent Document 1, in order to increase the carrier concentration in the p-type cladding layer, a hydrogen storage layer is formed on the p-type cladding layer before forming the p-side full surface electrode.
In the manufacturing method disclosed in Patent Document 2, a hydrogen storage metal layer is formed on the entire surface of the p-type contact layer in order to reduce the hydrogen concentration.
In the manufacturing method disclosed in Patent Document 3, in order to adsorb hydrogen desorbed from the Mg-doped p-type semiconductor layer, a hydrogen storage metal is formed on the p-type semiconductor layer before the p-side full surface electrode is formed. A hydrogen adsorption film is formed.
Conventionally, the surface of a nitride semiconductor layer is washed with a hydrofluoric acid chemical solution or an ammonia chemical solution before forming an electrode in order to improve the electrostatic discharge (ESD) resistance of the nitride semiconductor device. The method of doing is also known. ESD is a violent discharge that occurs when a charged conductive object (for example, a human body) comes into contact with a nitride semiconductor element or the like, or comes close enough.
JP 2004-47930 A (paragraph 0014, FIG. 3) JP 2000-58919 A (paragraph 0015, FIG. 4) JP 2000-216164 A (paragraph 0031, FIG. 8)

However, in the nitride semiconductor device manufactured by the manufacturing method described in Patent Document 1, the hydrogen storage layer is formed so that the entire surface is in contact with the entire surface of the p-side electrode and the surface of the p-type cladding layer. The p-side full surface electrode and the p-type cladding layer are cut off. As a result, there is a problem that the light emission output is greatly reduced.
Similarly, the nitride semiconductor device manufactured by the manufacturing method described in Patent Document 2 has a hydrogen storage metal layer formed so as to be in contact with the entire surface of the p-type contact layer. It will decline.
Similarly, the nitride semiconductor device manufactured by the manufacturing method described in Patent Document 3 has a hydrogen adsorption film formed so as to be in contact with the entire surface of the p-type semiconductor layer. Resulting in.
In addition, the nitride semiconductor device in which the p-side full surface electrode is formed after the surface of the nitride semiconductor layer is washed with a hydrofluoric acid chemical solution or the like does not have sufficient ESD resistance. Therefore, in order to improve problems such as malfunction and damage of the nitride semiconductor element, a nitride semiconductor element having excellent ESD resistance is desired.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a nitride semiconductor device capable of improving electrostatic discharge resistance and a method for manufacturing the same.

In order to solve the above problems, the nitride semiconductor device according to claim 1 of the present invention, a nitride having a nitride semiconductor layer containing a p-type impurity, and a p-side electrode in contact with the nitride semiconductor layer In the semiconductor element, the nitride semiconductor layer has a p-type impurity concentration of 1.5 × 10 ²⁰ / cm ³ or more and 2 × 10 ²² / cm ³ or less, the nitride semiconductor layer, and the p-side electrode And at least one metal selected from Mg, Pd, Pt, and Co is interspersed therewith.

  According to such a configuration, since the nitride semiconductor element has the metal scattered on the surface between the nitride semiconductor layer and the electrode, on this surface, the region where the nitride semiconductor layer and the electrode are in contact with each other, the metal The region where the intervenes. As a result, the magnitude of the current flowing in the direction perpendicular to the plane between the nitride semiconductor layer and the electrode tends to be uniform in the plane. As a result, in-plane uniformity of the current flowing through the nitride semiconductor element is maintained until the value of the voltage applied from the outside to the nitride semiconductor element becomes relatively large. That is, the electrostatic breakdown voltage of the nitride semiconductor element is higher than when there is no scattered metal. Therefore, the electrostatic discharge resistance of the nitride semiconductor element can be improved.

  The nitride semiconductor device according to claim 2 is the nitride semiconductor device according to claim 1, wherein the metal is preferably Pd.

  According to such a configuration, since the nitride semiconductor element has Pd scattered on the surface between the nitride semiconductor layer and the electrode, the Pd adsorbs hydrogen desorbed from the nitride semiconductor layer, Similarly, recombination of impurities desorbed from the nitride semiconductor layer and hydrogen can be prevented. Therefore, the uniformity of the current flowing through the nitride semiconductor element in the plane is maintained. As a result, it is possible to improve the electrostatic discharge resistance of the nitride semiconductor element.

The nitride semiconductor device according to claim 3 is the nitride semiconductor device according to claim 1 or 2 , wherein the nitride semiconductor layer is made of GaN or InGaN and is in contact with the p-side electrode. A first nitride semiconductor layer having a thickness of 100 angstroms or less; and a second nitride semiconductor layer containing a p-type impurity in contact with the first nitride semiconductor layer, wherein the first nitride semiconductor layer includes n A nitride semiconductor layer containing a p-type impurity, or a nitride semiconductor layer containing neither a p-type impurity nor an n-type impurity, and the second nitride semiconductor layer containing an impurity having the p-type impurity concentration. Is preferred.

  According to such a configuration, since the first nitride semiconductor layer has a layer thickness of 100 angstroms or less in the nitride semiconductor element, the electrode is on the p side even if the first nitride semiconductor layer does not contain p-type impurities. It can function as an electrode. That is, the nitride semiconductor element can improve the electrostatic discharge resistance even when the scattered metal is not in contact with the surface of the nitride semiconductor layer containing the p-type impurity, as in the case of contact. .

The nitride semiconductor device according to claim 4 is the nitride semiconductor device according to any one of claims 1 to 3 , wherein the scattered metal is the nitride semiconductor layer. It is preferable that the surface in contact with the electrode is arranged in the form of dots, stripes or lattices.

  According to such a configuration, the nitride semiconductor element can be easily manufactured when the metal is scattered in the form of dots, and when the metal is scattered in the form of stripes or lattices, the nitride semiconductor element can be manufactured. It becomes easy to control the magnitude of the current flowing in the direction perpendicular to the plane between the layer and the electrode so as to be uniform in the plane.

In order to achieve the above object, a method for manufacturing a nitride semiconductor device according to claim 5 includes a nitride semiconductor layer containing a p-type impurity, and a p-side electrode in contact with the nitride semiconductor layer. In the nitride semiconductor device, the nitride semiconductor layer has a p-type impurity concentration of 1.5 × 10 ²⁰ / cm ³ or more and 2 × 10 ²² / cm ³ or less, the nitride semiconductor layer, A method of manufacturing a nitride semiconductor device, characterized in that at least one metal selected from Mg, Pd, Pt, and Co is interspersed with a side electrode, wherein the concentration of the p-type impurity is 1 select a first step of forming a .5 × 10 ²⁰ / cm ³ to 2 × nitride semiconductor layer is 10 ²² / cm ³ or less, the surface of the nitride compound semiconductor layer, Mg, Pd, Pt, Co, Cleaning with an acid solution containing at least one metal And step, and having a third step of forming a p-side electrode on the nitride semiconductor layer.

  According to this procedure, in the nitride semiconductor device, the metal is scattered on the nitride semiconductor layer containing the p-type impurity, and the electrode is formed so as to cover the metal. Here, the method of dispersing the metal may be a chemical method or a physical method. Examples of the chemical method include cleaning with a solution containing a metal. Moreover, as a physical method, sputtering, vapor deposition, etc. are mentioned, for example. In this nitride semiconductor element, a region where the nitride semiconductor layer and the electrode are in contact with each other and a region where a metal is present are formed on the surface of the nitride semiconductor layer containing the p-type impurity. As a result, the magnitude of the current flowing in the direction perpendicular to the plane between the nitride semiconductor layer and the electrode tends to be uniform in the plane. Therefore, the electrostatic discharge resistance of the nitride semiconductor element can be improved.

  According to such a procedure, in the method for manufacturing a nitride semiconductor device, the surface of the nitride semiconductor layer containing a p-type impurity is washed with an acid solution containing a metal so that the metal contained in the acid solution is scattered. it can. Here, the acid solution is, for example, a metal nitric acid solution or an aqueous solution of the nitric acid solution. Moreover, washing | cleaning includes methods, such as an immersion type, a flowing liquid type, and a shower type, for example.

The method for manufacturing a nitride semiconductor device according to claim 6 is the method for manufacturing a nitride semiconductor device according to claim 5 , wherein the p-type is formed after the second step and before the third step. It is preferable to further include a fourth step of heat-treating the nitride semiconductor layer containing impurities at 400 ° C. or higher and 600 ° C. or lower.

A method of manufacturing a nitride semiconductor device according to claim 7, in the manufacturing method of the nitride semiconductor device according to claim 5, after the third step, the nitride semiconductor layer including the p-type impurity It is preferable to further include a fourth step of heat treatment at 400 ° C. or higher and 600 ° C. or lower.

The method for manufacturing a nitride semiconductor device according to claim 8 is the method for manufacturing a nitride semiconductor device according to claim 6 or 7 , wherein in the fourth step, in an atmosphere containing nitrogen, The nitride semiconductor layer containing the p-type impurity is preferably heat-treated.

  According to such a procedure, in the manufactured nitride semiconductor device, it is possible to effectively improve electrostatic discharge resistance without causing defects in the nitride semiconductor layer.

  According to the present invention, resistance to electrostatic discharge can be improved.

  The best mode for carrying out the nitride semiconductor device and the method for manufacturing the same according to the present invention (hereinafter referred to as “embodiment”) will be described below in detail with reference to the drawings. FIG. 1 is a plan view of a nitride semiconductor device according to an embodiment of the present invention as viewed from the p-side electrode, and FIG. 2 is a cross-sectional view taken along line AA in FIG.

[Configuration of nitride semiconductor device]
As shown in FIGS. 1 and 2, the nitride semiconductor device according to the embodiment of the present invention includes an n-type nitride semiconductor layer 2, an active layer 3, and a p-type nitride semiconductor layer 4 on a substrate 1. Are sequentially formed. A metal 5 is scattered on the p-type nitride semiconductor layer 4, and a p-side full-surface electrode 6 is formed on the p-type nitride semiconductor layer 4 so as to cover the metal 5. Further, a p-side pad electrode 7 is formed on the p-side full surface electrode 6, and an n-side electrode 8 is formed on the n-type nitride semiconductor layer 2. Here, the surface between the p-type nitride semiconductor layer 4 and the p-side full surface electrode 6 includes a region where the p-type nitride semiconductor layer 4 and the p-side full surface electrode 6 are in contact with each other, and a region where the metal 5 is interposed. Is present.

The substrate 1 is made of, for example, sapphire or SiC. The n-type nitride semiconductor layer 2 is made of, for example, GaN containing Si as an n-type impurity. The active layer 3 is made of, for example, InGaN. The p-type nitride semiconductor layer 4 is made of, for example, GaN containing Mg as a p-type impurity. The concentration of the p-type impurity contained in the p-type nitride semiconductor layer 4 is 1 × 10 ¹⁸ / cm ³ or more and 2 × 10 ²² / cm ³ or less. In particular, the higher the Mg concentration, the more remarkable the ESD resistance effect. For example, when the p-side full-surface electrode 6 is made of ITO and the p-type impurity is Mg, the concentration of the p-type impurity is 1.5 × 10 ²⁰ or more and 2 × 10 ²² / cm ³ or less. It is preferable. The metal 5 is composed of at least one metal selected from Mg, Pd, Pt, and Co.

The p-side full surface electrode 6 contains a material having a small contact resistance with the p-type nitride semiconductor layer 4. The material is preferably nickel (Ni), platinum (Pt), palladium (Pd), rhodium (R h ), ruthenium (Ru), osmium (Os), iridium (Ir), titanium (Ti), zirconium. (Zr), hafnium (Hf), panadium (V), niobium (Nb), tantalum (Ta), cobalt (Co), iron (Fe), manganese (Mn), molybdenum (Mo), chromium (Cr), tungsten (W), lanthanum (La), copper (Cu), silver (Ag), yttrium (Y), gold (Au), metals (alloys containing at least one selected from the group consisting of aluminum (Al), alloys, their A laminated structure, further compounds thereof, and other conductive oxide films can be given.

Further, the material of the p-side full-surface electrode 6 is more preferably a metal, an alloy, or a laminated structure thereof including at least one selected from the group consisting of nickel (Ni), gold (Au), and silver (Ag), In addition, a conductive oxide film can be given.
In the case of a metal or alloy layer, translucency can be ensured by forming it with a thin film. Examples of the conductive metal oxide (oxide semiconductor) include a conductive oxide film containing at least one element selected from the group consisting of zinc, indium, tin, gallium, and magnesium. Specifically, indium oxide containing tin (Indium Tin Oxide; ITO), ZnO, In ₂ O _3, SnO ₂ or the like can be given. Particularly for conductive metal oxides, ITO is most preferable from the viewpoints of conductivity and translucency.

  The p-side full surface electrode 6 may include a conductive oxide film on the side in contact with the p-type nitride semiconductor layer 4. Further, the p-side full surface electrode 6 may be made of a metal film made of a material different from the metal 5. The p-side pad electrode 7 and the n-side electrode 8 are made of a plurality of metals, for example.

  FIGS. 3A and 3B are plan views showing a state in which the metal on the p-type nitride semiconductor layer is scattered, in which FIG. 3A is a dot shape, FIG. 3B is a dot inversion, FIG. d) shows a lattice shape. The arrangement of the metal shown in FIG. 3A shows the arrangement of the metal 5 of the present embodiment. The metal 5 is arranged in the form of dots on the surface where the p-type nitride semiconductor layer 4 is in contact with the p-side full surface electrode 6. Here, as an indicator that the metal is scattered, the area that the scattered metal 5 occupies on the surface in contact with the p-side full surface electrode 6 indicates that the p-type nitride semiconductor layer 4 is in the p-side full surface electrode 6. It means 50% or less of the area of the contact surface. By being in such a range, the magnitude of the current in the plane is preferable because uniformity can be easily maintained. When the area of the metal 5 occupying the surface of the p-type nitride semiconductor layer 4 in contact with the p-side full-surface electrode 6 is this ratio, the arrangement of the metal 5 is as shown in FIG. Such a point-like inversion, a stripe shape as shown in FIG. 3C, or a lattice shape as shown in FIG.

[Nitride Semiconductor Device Manufacturing Method]
A method of manufacturing the nitride semiconductor device shown in FIG. 1 will be described with reference to FIG. 4 (see FIGS. 1 to 3 as appropriate). FIG. 4 is a flowchart showing a method for manufacturing the nitride semiconductor device shown in FIG.

  First, a base layer such as a buffer layer is formed on the substrate 1 by epitaxial growth (step S1: substrate forming step). Note that the base layer can be omitted depending on the combination of the substrate and the semiconductor material. Next, a nitride semiconductor layer is formed by metal organic chemical vapor deposition (MOCVD) (step S2: nitride semiconductor formation step). The nitride semiconductor forming step includes a step of laminating the n-type nitride semiconductor layer 2, a step of laminating the active layer 3, and a p-type nitride semiconductor layer via a base layer such as a buffer layer on the substrate 1. 4 (first step). Note that the order of stacking the nitride semiconductor layers is not particularly limited.

  Each nitride semiconductor layer is formed on a heterogeneous substrate, preferably a sapphire substrate, using a c-axis grown nitride semiconductor by MOCVD. The n-type nitride semiconductor layer 2 is formed by growing a crystal made of GaN doped with Si. The n-type nitride semiconductor layer 2 may be formed in a two-layer structure of an n-type contact layer and an n-type cladding layer. The active layer 3 is formed by laminating InGaN or the like on the n-type nitride semiconductor layer 2 by MOCVD. The p-type nitride semiconductor layer 4 is formed on the active layer 3 by growing a crystal made of GaN doped with Mg by MOCVD. The p-type nitride semiconductor layer 4 may also be formed in a two-layer structure of a p-type cladding layer and a p-type contact layer, like the n-type nitride semiconductor layer 2.

Next, the natural oxide film on the surface of the p-type nitride semiconductor layer 4 is removed by, for example, BHF (buffered hydrofluoric acid) or the like (step S3: oxide film removing step). BHF is a mixed liquid of HF (hydrofluoric acid) and NH ₄ F (ammonium fluoride).

  Next, as a step of dispersing the metal 5 on the p-type nitride semiconductor layer 4 (second step), the surface of the p-type nitride semiconductor layer 4 is washed with an acid solution containing the metal 5 (step S4). : Washing process). The cleaning method may be an immersion (Dip) type, a flowing liquid type, or a shower type. In the washing step, the immersion time in the acid solution is preferably 1 minute or longer, and preferably 20 minutes or shorter from the viewpoint of productivity. Further, the washing time after dipping in the acid solution is at least equal to or longer than the dipping time. In particular, it is preferable that the time is not less than 5 times the immersion time. The reason is that the p-side full surface electrode 6 provided on the p-type nitride semiconductor layer 4 can be prevented from floating from the p-type nitride semiconductor layer 4 when the time is five times or more. It is.

  Next, the p-type nitride semiconductor layer 4 is heat-treated (step S5: heat treatment process, fourth process). Here, when the heating temperature is 400 ° C. or higher, good results can be obtained efficiently. Further, no defects are caused in the p-type nitride semiconductor layer 4 at 600 ° C. or lower. Therefore, it is preferable to heat at 400 ° C. or higher and 600 ° C. or lower.

  Next, after the etching process for digging out the n-type nitride semiconductor layer 2, W, Pt, and Au are sequentially stacked on the entire surface from the n-type nitride semiconductor layer 2 side by vapor deposition, sputtering, or the like. The n-side electrode 8 is formed by patterning into a desired shape (step S6: electrode forming step). Other metals and alloys can also be used.

  Further, ITO is formed on the p-type nitride semiconductor layer 4 so as to cover the metal 5 by sputtering, and a mask is formed using a photoresist or the like in a region where the p-side full surface electrode 6 is to be formed. After etching ITO and etching the ITO, the mask is removed by cleaning using an organic solvent or the like, thereby forming the p-side full surface electrode 6 (step S6: electrode forming step, third step).

  Next, W, Pt, and Au are laminated on the entire surface in this order from the p-side full-surface electrode 6 side by vapor deposition, sputtering, or the like. Thereafter, the metal layer is patterned into a desired shape by photolithography, thereby forming the p-side pad electrode 7 on a part of the p-side full surface electrode 6 (step S7: pad electrode forming step). When the same material is used for the p-side pad electrode 7 and the n-side electrode 8, the p-side pad electrode 7 and the n-side electrode 8 can be formed in the same process. In this case, the p-side pad electrode 7 and the n-side electrode 8 can be performed in the same step after the etching step of forming the p-side full surface electrode 6 and digging out the n-type nitride semiconductor layer 2.

[Dispersed state of each process and metal]
Next, the relationship between the cleaning step, the heat treatment step, the electrode formation step, and the metal scattering state will be described with reference to FIG. 5 is a cross-sectional view showing the arrangement of the metal on the p-type nitride semiconductor layer shown in FIG. 2, wherein (a) is after the cleaning step, (b) is after the heat treatment step, and (c) is Each after the electrode forming step is shown.

  As shown in FIG. 5A, in the state where the cleaning process is completed, the metal 5 is scattered in an ionic state on the p-type nitride semiconductor layer 4 (the surface from which an electrode is to be formed). . Further, as shown in FIG. 5B, in the state where the heat treatment step is completed, some of the metals 5 existing on the p-type nitride semiconductor layer 4 are diffused by heat. The diffusion direction includes a direction (vertical direction) diving toward the p-type nitride semiconductor layer 4 and a horizontal direction.

  Further, as shown in FIG. 5C, in the state where the electrode forming process of the p-side full-surface electrode 6 is completed, some of the metal 5 existing on the p-type nitride semiconductor layer 4 is diffused. is doing. The diffusion direction includes a direction of floating toward the p-side full-surface electrode 6 (vertical direction), a direction of diving toward the p-type nitride semiconductor layer 4 (vertical direction), and a horizontal direction.

As shown in FIGS. 5A to 5C, the metal 5 is two-dimensionally in-plane between the p-type nitride semiconductor layer 4 and the p-side full surface electrode 6 due to the diffusion of the metal 5. It is not only simply scattered in the direction, but complicatedly scattered in the three-dimensional direction. In particular, when the p-type impurity concentration of the p-type nitride semiconductor layer 4 in contact with the p-side full-surface electrode 6 is 1.5 × 10 ²⁰ / cm ³ or more, the p-type nitride semiconductor layer 4 tends to have pits. The metal 5 is preferably diffused from the pits toward the p-type nitride semiconductor layer 4 in a diving direction, which is preferable since the forward voltage of the nitride semiconductor element is decreased. The upper limit of the p-type impurity concentration is preferably 2 × 10 ²² / cm ³ or less, and if it is larger than this, the crystallinity of the p-type nitride semiconductor layer 4 is deteriorated, and conversely the forward voltage is high. turn into.

  According to the present embodiment, the magnitude of the current flowing in the direction perpendicular to the plane between the p-type nitride semiconductor layer 4 and the p-side full-surface electrode 6 tends to be uniform in the plane. As a result, the in-plane uniformity of the current flowing through the nitride semiconductor device is maintained until the value of the voltage applied to the nitride semiconductor device of the present embodiment from the outside becomes relatively large. That is, the nitride semiconductor element of the present embodiment has a higher electrostatic breakdown voltage than the case where the metal 5 is not present. Therefore, it is possible to improve the ESD resistance of the nitride semiconductor element.

Although the embodiment has been described above, the present invention is not limited to this, and can be implemented in various ways without changing the gist thereof. For example, in the nitride semiconductor device of this embodiment, the metal 5 is interspersed between the p-type nitride semiconductor layer 4 and the p-side full surface electrode 6, but the electrode only functions as a p-side electrode. For example, the nitride semiconductor layer in contact with the electrode is not limited to the p-type. As described above, examples of the configuration in which the electrode functions as the p-side electrode include the following configurations. In this case, the nitride semiconductor layer is made of GaN or InGaN, and has a first nitride semiconductor layer having a thickness of 100 angstroms or less in contact with the electrode, and a p-type impurity in contact with the first nitride semiconductor layer. It consists of a 2 nitride semiconductor layer. The first nitride semiconductor layer is a nitride semiconductor layer containing n-type impurities, or is a nitride semiconductor layer containing neither p-type impurities nor n-type impurities, and the second nitride semiconductor layer is The p-type impurity concentration is 1 × 10 ¹⁸ / cm ³ or more and 2 × 10 ²² / cm ³ or less. For example, in the former case, an extremely thin n-type nitride semiconductor layer is stacked on the p-type nitride semiconductor layer 4 shown in FIG. It means that the electrode 6 is formed.

In the nitride semiconductor device manufacturing method of the present embodiment, the heat treatment step (fourth step) has been described as being performed before electrode formation, but may be performed after electrode formation. Further, heat treatment may be performed before and after electrode formation. The heat treatment step is preferably performed at atmospheric pressure, but may be performed in a vacuum degree of about 1 × 10 ⁻³ to 1 × 10 ⁻⁴ Pa.

  In this embodiment, as a method for dispersing at least one metal selected from Mg, Pd, Pt, and Co, cleaning is used as a chemical method. However, a physical method such as a vapor deposition method or a sputtering method is used. May be used. In this case, for example, in the vapor deposition film forming apparatus, the film is set so that it can be formed with an extremely thin thickness that cannot be called a normal film, and the incomplete film before the set film is completed. What is necessary is just to make it interrupt and take out a process in the state of a film | membrane.

  In order to confirm the effect of the present invention, a nitride semiconductor device manufacturing method according to this embodiment is used, and a plurality of nitride semiconductor devices in which one kind of metal is scattered are used using a gallium nitride-based semiconductor growth apparatus. Kind manufactured. Specifically, in the oxide film removing step (step S3), the surface of the p-type nitride semiconductor layer 4 was washed with BHF for 10 minutes. In the cleaning step (step S4), the p-type nitride semiconductor layer 4 is added to an acid solution containing Mg (Example 1), Pd (Example 2), Pt (Example 3), and Co (Example 4). The entire wafer formed up to the above was immersed to manufacture nitride semiconductor elements.

  For comparison, a nitride semiconductor device was manufactured (Comparative Example 1) without performing the cleaning process (Step S4) and the heat treatment process (Step S5) in the same manner as in the conventional method. Further, a nitride semiconductor device was manufactured by a manufacturing method that differs only in that it was washed with an acid solution containing a metal different from Mg, Pd, Pt, and Co. At this time, an acid solution containing Ni was used (Comparative Example 2). Here, as each acid solution, a commercially available standard reagent (1000 mg / L water-soluble standard solution) was used. The components of each acid solution are shown in Table 1.

  Table 2 shows various manufacturing conditions in the cleaning process (step S4) and the heat treatment process (step S5). Note that slm is a unit (standard liter / min) in which the flow rate per minute at 0 ° C. and 1 atm is expressed in liters. Table 3 shows the characteristics and evaluation test results of the nitride semiconductor devices manufactured under these conditions.

In the element characteristics shown in Table 3, the light emission output corresponding value V _L is a value (dimensionless) of the intermediate inspection in the state before resin sealing in the nitride semiconductor element, and the p-side pad electrode 7 and the n-side electrode 8. In this state, the lamp output was measured by attaching a terminal directly to each electrode. Also, a dominant wavelength W _D is the most intensity of the emission spectrum is higher wavelength (peak wavelength).

In addition, the evaluation test shown in Table 3 was performed by applying the voltage from the outside while increasing the voltage at a constant speed and at a constant interval to each manufactured nitride semiconductor device, and examining the number of breakdowns at each applied voltage. It is a thing. The evaluation test was performed on each type of nitride semiconductor device using a plurality of testing machines. In Table 3, the result of this evaluation test is indicated by the breakdown voltage V _D.

The breakdown voltage V _D indicates ESD resistance. When a voltage is applied to α (for example, 1000) nitride semiconductor elements from the outside, the number of breakdowns with the applied voltage V _m [V] is calculated. When N _m (m = 0, 1, 2,...), The average value of the applied voltages calculated by the equation (1) is shown. Here, the average value for each tester was further taken. The applied voltage is, for example, V _m = 100 × m [V]. As the value of the breakdown voltage V _D is large, indicating that the ESD tolerance is higher.

From Table 3, it can be seen that the characteristics (forward voltage, light output, etc.) of all types of manufactured nitride semiconductor devices are substantially the same. The breakdown voltage V _D is slightly over 500 [V] in Comparative Example 1 and Comparative Example 2. On the other hand, in Examples 1 to 4, it greatly exceeds 600 [V]. That is, Example 1 to Example 4 had higher ESD resistance than Comparative Example 1 and Comparative Example 2.

In Example 2, the breakdown voltage V _D was “985 (V)”, which was a prominent value. This reason is considered to be due to the hydrogen storage effect of Pd, which is a dispersed metal. In addition, since Mg used in Example 1 also has a hydrogen storage effect, it is considered that the breakdown voltage V _D is increased. However, from the evaluation test results, not only the scattered metal has a hydrogen occlusion effect, but also the nitride semiconductor element in a state where the element types are Mg, Pd, Pt, Co and each element is scattered. This is considered to be a main factor contributing to the improvement of the breakdown voltage V _D. In addition, each element is not only included independently, but at least one element may be included. Further, if the metal is not scattered but has a layered structure, there arises a problem that the light emission output of the manufactured nitride semiconductor element is lowered.

  Next, in order to confirm the metal scattering state, the p-type nitride semiconductor layer 4 is applied to the p-side full-surface electrode 6 in Example 2 using secondary ion mass spectrometry (SIMS). The ratio of the area of Pd in the contact surface was measured. Specifically, a secondary ion mass spectrometer (trade name “PHI TRIFT III”, manufactured by ULVAC-PHI, Inc.) was used. Here, in the secondary ion mass spectrometer, depth direction analysis is possible with a depth resolution on the order of several to several tens of nm, and the size of the analysis region is usually several tens to several hundreds of μm. With this apparatus, the distribution of impurities contained at a depth of about several tens of nm to several μm from the sample surface can be examined. Using the Pd of Example 2, a region where Pd ions having a mass number of 106 exist on the nitride semiconductor element was measured. The measurement results are shown in FIG. According to FIG. 6, Pd ions (the white area in FIG. 6, the metal 5) are present between the p-type nitride semiconductor layer 4 and the p-side full-surface electrode 6 on average at a ratio of about 20%. It was confirmed that the dots were distributed.

It is the top view which looked at the nitride semiconductor device concerning the embodiment of the present invention from the p side electrode. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. It is a top view which shows a mode that the metal on a p-type nitride semiconductor layer is scattered, (a) is dot shape, (b) is dot-like inversion, (c) is stripe shape, (d) is a lattice. Each state is shown. 2 is a flowchart showing a method for manufacturing the nitride semiconductor device shown in FIG. FIG. 3 is a cross-sectional view showing the arrangement of metals on the p-type nitride semiconductor layer shown in FIG. 2, (a) after completion of the cleaning process, (b) after completion of the heat treatment process, and (c) after completion of the electrode formation process. Each is shown later. FIG. 10 is a diagram showing an analysis result of the existence positions of metal ions scattered in the nitride semiconductor element of Example 2.

Explanation of symbols

1 substrate 2 n-type nitride semiconductor layer 3 active layer 4 p-type nitride semiconductor layer 5 metal 6 p-side full surface electrode 7 p-side pad electrode 8 n-side electrode

Claims (8)

and the nitride semiconductor layer comprising a p-type impurity, the nitride semiconductor device having a p-side electrode in contact with the nitride semiconductor layer,
The nitride semiconductor layer has a p-type impurity concentration of 1.5 × 10 ²⁰ / cm ³ or more and 2 × 10 ²² / cm ³ or less,
A nitride semiconductor device, wherein at least one metal selected from Mg, Pd, Pt, and Co is scattered between the nitride semiconductor layer and the p-side electrode.   The nitride semiconductor device according to claim 1, wherein the metal is Pd. The nitride semiconductor layer is made of GaN or InGaN, and includes a first nitride semiconductor layer having a thickness of 100 angstroms or less in contact with the p-side electrode, and a p-type impurity in contact with the first nitride semiconductor layer. A second nitride semiconductor layer,
The first nitride semiconductor layer is a nitride semiconductor layer containing an n-type impurity, or a nitride semiconductor layer containing neither a p-type impurity nor an n-type impurity,
The second nitride semiconductor layer, nitride semiconductor device according to claim 1 or claim 2, characterized in that it comprises an impurity of the p-type impurity concentration. The metal scattered and is the a plane nitride semiconductor layer is in contact with the p-side electrode, punctate, claims 1 to 3, characterized in that arranged in stripes or lattice-like The nitride semiconductor device according to any one of the above. In a nitride semiconductor device having a nitride semiconductor layer containing a p-type impurity and a p-side electrode in contact with the nitride semiconductor layer, the nitride semiconductor layer has a concentration of the p-type impurity of 1.5 × 10 5. ²⁰ / cm ³ or more and 2 × 10 ²² / cm ³ or less, and at least one metal selected from Mg, Pd, Pt, and Co is scattered between the nitride semiconductor layer and the p-side electrode. A method for manufacturing a nitride semiconductor device, comprising:
a first step of forming a nitride semiconductor layer having a p-type impurity concentration of 1.5 × 10 ²⁰ / cm ³ or more and 2 × 10 ²² / cm ³ or less ;
The surface of the nitride compound semiconductor layer, a second step of washing Mg, Pd, Pt, in an acid solution containing at least one metal selected from Co,
A third method of manufacturing a nitride semiconductor device characterized by comprising: a step, the forming the p-side electrode on the nitride semiconductor layer. The method further comprises a fourth step of heat-treating the nitride semiconductor layer containing the p-type impurity at 400 ° C. or more and 600 ° C. or less after the second step and before the third step. 6. A method for producing a nitride semiconductor device according to 5 . 6. The nitride semiconductor device according to claim 5 , further comprising a fourth step of heat-treating the nitride semiconductor layer containing the p-type impurity at 400 ° C. to 600 ° C. after the third step. Manufacturing method. Wherein in the fourth step, in an atmosphere containing nitrogen, method of manufacturing the nitride semiconductor device according to claim 6 or claim 7, characterized in that heat treatment of the nitride semiconductor layer including the p-type impurity .

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