KR101077771B1 - Semiconductor device for emitting light and method for fabricating the same - Google Patents

Abstract

The present invention includes a semiconductor layer having a light emitting structure and an ohmic electrode having a nano dot layer, a contact layer, a reflective layer, a diffusion barrier layer, and a capping layer formed on the semiconductor layer, wherein the nano dot layer is nitrogen of the semiconductor layer. Provided are a semiconductor light emitting device formed on a polar plane and formed of at least one of Ag, Al, and Au, and a method of manufacturing the same.

In such a semiconductor light emitting device, a multi-layered ohmic electrode including a nano dot layer, a contact layer, a reflection layer, an anti-diffusion layer, and a capping layer is formed on the nitrogen polarity surface of the nitride semiconductor and has a low temperature even though it is not subjected to an additional heat treatment process. Ohmic resistance and high light reflectivity can be maintained.

Ohmic electrode, LED, light emitting element, n-type electrode, p-type electrode

Description

Semiconductor light emitting device and method of manufacturing the same {SEMICONDUCTOR DEVICE FOR EMITTING LIGHT AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device and a method of manufacturing the same, and more particularly, to a semiconductor light emitting device having an ohmic electrode formed on a semiconductor layer of a light emitting structure for applying an external driving power source, and a manufacturing method thereof.

A light emitting diode (LED) has a long life, can be miniaturized and light in weight, has a strong light directivity and can be driven at low voltage. In addition, it is resistant to shock and vibration, requires no preheating time and complicated driving circuits, and can be packaged in various forms. In particular, the nitride-based semiconductor light emitting device has a large energy band gap, which enables light output in a wide wavelength band from the ultraviolet region to blue / red, and can achieve high efficiency and high output due to its excellent physical and chemical stability. It is getting a lot of attention. Such nitride semiconductor light emitting devices are capable of emitting white light when combined with existing red and green light emitting devices, and are expected to replace incandescent lamps, fluorescent lamps, mercury lamps and existing white lighting means in the coming years.

However, the nitride semiconductor light emitting devices developed to date are not satisfactory in terms of light output, luminous efficiency, and price, and require further performance improvement. In particular, there is still a need to further increase the low light output compared to the conventional white light source, and thus must overcome the problem of thermal stability.

Meanwhile, a general nitride semiconductor light emitting device is manufactured by forming a nitride based n-type layer, a nitride based active layer, and a nitride based p-type layer on a sapphire substrate, and placing two electrodes horizontally to apply power to the n-type layer and the p-type layer. . Such a light emitting device having a horizontal structure has an advantage of low manufacturing cost due to a relatively simple manufacturing process. However, since a sapphire substrate is used as a non-conductor and has poor thermal conductivity, high power is realized by applying a large current and thermal stability due to heat accumulation. This had the disadvantage of being degraded.

In order to overcome this disadvantage, vertical semiconductor light emitting devices and flip chip type semiconductor light emitting devices have been proposed. In this case, a reflective layer is formed on the p-type electrode so that light generated from the active layer is emitted to the outside through the n-type electrode, and a large-area current can be applied and rapid heat dissipation is possible by using a metal substrate having good thermal conductivity instead of the sapphire substrate. High output and thermal stability can be achieved. The semiconductor light emitting device having a vertical structure can increase the maximum applied current several times more than the semiconductor light emitting device having a horizontal structure, and thus, it is evaluated that high power is possible and can replace the existing white lighting means.

Meanwhile, in order to further improve the light output by injecting a high current, a large area of the semiconductor light emitting device is required. In this case, the area of the electrode, for example, the n-type electrode, is also gradually increased to improve the current diffusion characteristics during the high current injection. However, since the common n-type electrode Cr / Au or Ti / Al uses thick Cr or Ti with low reflectivity, the larger the area of the n-type electrode is, the more the portion absorbs light from the active layer. It can act as an obstacle to output improvement. Therefore, there is an urgent need for the development of an n-type ohmic electrode having low ohmic resistance and high reflectivity.

In the semiconductor light emitting device having a vertical structure, after forming a nitride semiconductor layer on a mother substrate, a p-type electrode is formed on an upper surface of the nitride semiconductor layer, that is, a gallium polarity (Ga-face), and on a p-type electrode. After attaching the auxiliary substrate, the mother substrate is separated to form an n-type electrode on the lower surface of the nitride semiconductor layer, that is, the N-face. However, unlike the Ga-face, the N-face cannot expect good ohmic properties without heat treatment, and the heat treatment itself is due to the difference in the coefficient of thermal expansion between the auxiliary substrate (metal substrate) and the nitride semiconductor layer. Nor is it easy. As described above, the conventional Cr / Au or Ti / Al structure electrode formed on the conventional nitrogen polarity (N-face) has not only poor ohmic characteristics, but also low thermal stability.

The present invention has been made to solve the above problems, and has excellent light reflectivity, and thus has low light loss due to light absorption of the electrode itself, and has excellent ohmic characteristics in terms of nitrogen polarity as well as gallium polarity of the nitride semiconductor layer. It provides a semiconductor light emitting device and a method of manufacturing the same.

A semiconductor light emitting device according to an aspect of the present invention, a semiconductor layer having a light emitting structure; An ohmic electrode having a nano dot layer, a contact layer, a reflective layer, a diffusion barrier layer, and a capping layer formed on the semiconductor layer; The nano dot layer is formed on the nitrogen polarity surface of the semiconductor layer, and formed of at least one material of Ag, Al, Au, the contact layer is Ni, Ni-Ti alloy, Ni-Al alloy , Ti-Al alloy, Mg-Al alloy, Ta, Ti, W, W-Ti alloy is formed of at least one material, the reflective layer is Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag-In Alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, Al-Mg alloy is formed of at least one material, the diffusion barrier layer is Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, At least one metal layer of Nb W and W-Ti alloys or at least one oxide film of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx, and the capping layer is formed of at least one of Au and Al. Is formed.

The nano dot layer is preferably made of nano-size Ag dots formed by depositing Ag and heat treatment in a nitrogen atmosphere. At this time, it is preferable that the nano dot layer is formed to have a thickness of 5 kPa to 50 kPa.

Preferably, the contact layer is formed of Ni, the reflective layer is made of Al, the diffusion barrier layer is made of Ti, and the capping layer is made of Au. At this time, it is preferable that the contact layer is formed to a thickness of 1 kPa to 50 kPa, and the reflective layer is formed to a thickness of 100 kPa to 8000 kPa.

The semiconductor layer includes an n-type layer, an active layer and a p-type layer, and the ohmic electrode is preferably formed on the nitrogen polarity surface of the n-type layer.

The semiconductor layer is preferably formed on the upper surface of the substrate on which a hemispherical pattern is formed.

According to another aspect of the present invention, a method of manufacturing a semiconductor light emitting device includes: forming a semiconductor layer having a light emitting structure; Forming a nano dot layer on the nitrogen polarity surface of the semiconductor layer; And forming a contact layer, a reflective layer, a diffusion barrier layer, and a capping layer on the nano dot layer. The nano dot layer is formed of at least one material of Ag, Al, Au, and the contact layer is Ni, Ni-Ti alloy, Ni-Al alloy, Ti-Al alloy, Mg-Al alloy, Ta , Ti, W, W-Ti alloy is formed of at least one material, the reflective layer is Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag-In alloy, Ag-Mg alloy, Al-Cu alloy, It is formed of at least one material of Al-In alloy, Al-Mg alloy, the diffusion barrier layer is at least one metal layer of Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, Nb W, W-Ti alloy Or at least one oxide film of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx, and the capping layer is formed of at least one of Au and Al.

The nano dot layer is preferably formed by depositing Ag on the nitrogen polarity surface of the semiconductor layer and heat-treating it in a nitrogen atmosphere.

Preferably, the contact layer is formed of Ni, the reflective layer is made of Al, the diffusion barrier layer is made of Ti, and the capping layer is made of Au.

The multi-layered ohmic electrode including the nano dot layer / contact layer / reflective layer / diffusion prevention layer / capping layer according to the present invention has excellent reflectivity to prevent a decrease in light output due to light absorption, and does not require additional heat treatment. Its excellent characteristics make it possible to output high currents with high current.

In particular, the multi-layered ohmic electrode including the nano dot layer / contact layer / reflective layer / diffusion prevention layer / capping layer according to the present invention is formed on the nitrogen polarity surface of the nitride semiconductor, and although not subjected to an additional heat treatment process, Ohmic resistance and high light reflectivity can be maintained. Therefore, the n-type electrode (or n-type pad) is formed on the nitrogen polarity surface of the nitride semiconductor, so that the ohmic characteristics are not good, and due to the difference in thermal expansion coefficient between the metal substrate and the nitride semiconductor, it is difficult to improve the ohmic characteristics even through heat treatment. It can be used more suitably for a semiconductor light emitting element.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art the scope of the invention. It is provided for complete information.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as “above” or “above” another part, each part is not only when the part is “right above” or “just above” the other part, This includes the case where there is another part between other parts.

<First Embodiment>

1 is a cross-sectional view illustrating a semiconductor light emitting device according to a first exemplary embodiment of the present invention.

Referring to FIG. 1, the semiconductor light emitting device includes a semiconductor layer 120 including an n-type layer 121, an active layer 122, and a p-type layer 123, and an n-type electrode formed on an upper surface of the n-type layer 121. 180 and a p-type electrode 130 formed on the bottom surface of the p-type layer 123, and further including a support substrate 170 attached to the bottom surface of the p-type electrode 130 to support the entire structures 120, 130, and 180. do. The n-type electrode 180 may include a nano dot-type layer 181, a contact layer 182, a reflective layer 183, a diffusion barrier layer 184, and a capping layer formed on the semiconductor layer 120. 185 and an ohmic electrode having a multilayer structure in ohmic contact with the semiconductor layer 120.

The semiconductor layer 120 includes an n-type layer 121, an active layer 122, and a p-type layer 123. The n-type layer 121, the active layer 122, and the p-type layer 123 may be a Si film, a GaN film, It may be formed of at least one of an AlN film, an InGaN film, an AlGaN film, an AlInGaN film, and a film containing the same. For example, in this embodiment, the n-type layer 121 and the p-type layer 123 are formed of a GaN film, and the active layer 122 is formed of an InGaN film.

The n-type layer 121 is a layer providing electrons, and may be composed of an n-type semiconductor layer and an n-type cladding layer. The n-type semiconductor layer and the n-type cladding layer may be formed by injecting an n-type dopant, for example, Si, Ge, Se, Te, C, or the like into the semiconductor thin film. The p-type layer 230 is a layer for providing holes, and may be composed of a p-type semiconductor layer and a p-type cladding layer. The p-type semiconductor layer and the p-type cladding layer may be formed by injecting a p-type dopant, for example, Mg, Zn, Be, Ca, Sr, or Ba into the semiconductor thin film.

The active layer 122 is a layer that outputs light having a predetermined wavelength while the electrons provided in the n-type layer 121 and the holes provided in the p-type layer 123 are recombined. A well layer and a barrier layer may be formed. The layers may be alternately stacked to form a multilayer semiconductor thin film having a single or multiple quantum well structure. Since the wavelength of light to be output varies depending on the semiconductor material constituting the active layer 122, it is preferable to select an appropriate semiconductor material according to the target output wavelength. For example, in the present embodiment, after depositing a GaN thin film, an n-type impurity is implanted to form an n-type layer 121, and a multi-well structure is formed by alternately depositing a GaN thin film as a barrier layer and an InGaN thin film as a well layer. The active layer 122 was formed, a GaN thin film was deposited thereon, and then a p-type impurity was implanted to form the p-type layer 123, thereby forming a light emitting semiconductor layer 120.

The n-type electrode 180 is connected to the negative potential of the driving power source to inject electrons into the n-type layer 121 of the semiconductor layer 120, and the p-type electrode 130 is connected to the positive potential of the driving power source. It injects holes into the p-type layer 123 of the semiconductor layer 120. In particular, the n-type electrode 180 and the p-type electrode 130 of the present embodiment are disposed vertically, and the p-type electrode 130 reflects the light generated by the active layer 122 so that most of the light is n-type layer ( 121) it forms a reflective surface to be emitted to the outside through the direction. In addition, the n-type electrode 180 may include a nano dot layer 181, a contact layer 182, a reflective layer 183, and a diffusion barrier layer 184 formed on the N-face of the semiconductor layer 120. And an ohmic electrode having a multilayer structure including a capping layer 185.

In this case, the nano dot layer 181 may be formed by heat-treating at least one material of Ag, Al, and Au in an atmosphere containing nitrogen. In addition, the contact layer 182 may be formed of at least one material of Ni, Ni-Ti alloy, Ni-Al alloy, Ti-Al alloy, Mg-Al alloy, Ta, Ti, W, W-Ti alloy The reflective layer 183 may be formed of at least one of Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag-In alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, and Al-Mg alloy. It can be formed as. Further, the diffusion barrier layer 184 is a metal layer of at least one of Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, Nb W, and W-Ti alloys or RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx , CrOx may be formed of at least one oxide film, and the capping layer 185 may be formed of at least one material of Au and Al. For example, the n-type electrode 180 of the present embodiment has a nano dot layer 181 Ag, a contact layer 182 Ni, a reflective layer 183 Al, a diffusion barrier 184 Ti, a capping layer 185 ) Is formed from Au.

The support substrate 170 supports the entire structures 120, 130, and 180 as the growth substrate of the semiconductor layer 120, that is, the base substrate is removed. The protective layer 160, the bonding layer 150, and the diffusion barrier layer 140 are disposed between the supporting substrate 170 and the p-type electrode 130 so that the supporting substrate 170 is attached to the lower surface of the p-type electrode 130. Can be formed. The diffusion barrier layer 140 is used to prevent diffusion of the forming material 120 of the p-type electrode 130 into the adjacent layer by heat during the bonding process of the p-type electrode 130 and the support substrate 170.

A manufacturing process of a semiconductor light emitting device having such a configuration will be described below with reference to FIGS. 2 to 5. 2 to 5 are cross-sectional views illustrating a process of manufacturing the semiconductor light emitting device according to the first embodiment of the present invention.

Referring to FIG. 2, an n-type layer 121, an active layer 122, and a p-type layer 123 are sequentially stacked on the prepared substrate 110 to form a semiconductor layer 120 having a multilayer structure. The substrate 110 may include a sapphire (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, a gallium arsenide (GaAs) substrate, or a gallium phosphide (GaP) substrate. Etc. can be used, and it is more preferable to use a sapphire substrate.

Referring to FIG. 3, a metal film is deposited on the semiconductor layer 120 to form a p-type electrode 130, and a diffusion barrier layer 140, an adhesive layer 150, and a protective layer on the p-type electrode 130. After forming the 160 in sequence, the support substrate 170 is attached through an adhesion process.

In this embodiment, a heat adhesion process is performed to attach the support substrate 170, and a diffusion barrier layer (p) is formed on the p-type electrode 130 to prevent diffusion of a material of the p-type electrode 130 during the heating process. 140). On the other hand, the p-type electrode 130 is preferably formed of a reflective conductive film having excellent light reflectivity, for example Ag or Au, so that most of the light generated in the active layer 120 is emitted toward the n-type layer 221. The auxiliary substrate 170 is preferably a metal substrate or a semiconductor substrate such as Si or Ge.

Referring to FIG. 4, the mother substrate 110 is separated and removed by performing a lift off process using a laser. Subsequently, as shown in FIG. 5, the support substrate 110 is turned upside down, followed by Mesa etching of the semiconductor layer 120 attached to the upper portion of the support substrate 170, and subsequently formed n-type electrode. Surface treatment of the semiconductor layer 120 is performed to improve the interfacial adhesion with the 180. In the present embodiment, the semiconductor surface, that is, n-type layer 123, is immersed in an aqueous solution of aqua regia (HCl: H ₂ O = 3: 1) for about 10 minutes, washed with deionized water, and dried with nitrogen to form a primary surface. The second surface treatment is performed by soaking for about 2 minutes in a solution mixed with hydrochloric acid (HCl) and deionized water 1: 1 before depositing a subsequent layer, that is, the n-type electrode 180, and then drying. . Of course, such primary and secondary surface treatment can be selectively performed according to a desired purpose, and can also be abbreviate | omitted.

Referring to FIG. 5 again, Ag is formed on the surface of the n-type layer 123 of the exposed semiconductor layer 120 by 5 nm to 50 mm thin and then heat-treated in an atmosphere containing nitrogen. The dot layer 181 is formed. The Ag nano dot layer 181 is formed on the N-face of the n-type layer 123. Subsequently, the Ni contact layer 182, the Al reflective layer 183, the Ti diffusion barrier layer 184, and the Au capping layer 185 are stacked on the Ag nano dot layer 181 and then patterned to form the Ag nano dot layer / Ni. An n-type electrode 180 having a / Al / Ti / Au structure is formed.

In this case, when the Ag nano dot layer 181 is less than 5 mW, the dot size is too small, and current injection efficiency is low. It is preferable. The Ni contact layer 182 may not serve as a contact layer when the thickness is less than 1 GPa. When the Ni contact layer 182 exceeds 50 GPa, the light transmittance is reduced due to light absorption. The Al reflective layer 183 is required to have a thickness of at least 500 kW or more in order to obtain high light reflectivity, but if it exceeds 8000 m, the thermal stability of the electrode may be reduced by Al migration. It is preferable to form. The Ti diffusion barrier layer 184 is difficult to effectively prevent the diffusion of Al particles when the thickness is less than 100Å, the thickness of 100Å to 1000Å because the adhesion may be reduced due to the increase in the stress in the thin film due to the increase in thickness It is desirable to. The Au capping layer 185 is not suitable for wire bonding if the thickness is less than 1000 kPa, and if the Au capping layer 185 exceeds 10000 kPa, the Au capping layer 185 may be formed to have a thickness of 1000 kPa to 10000 kPa. In addition, the total thickness of the n-type electrode 180 is preferably formed to be 1000 kPa to 10000 kPa. For example, in the present embodiment, an Ag nano dot layer, a Ni contact layer, an Al reflective layer, a Ti diffusion barrier layer, and an Au capping layer are sequentially formed on the semiconductor layer 120 using an e-beam evaporator. 20 μs / 10 μs / 2000 μs / 200 A / 5000 μs thick.

Then, after the formation of the n-type electrode 180 and the p-type electrode 130 to improve the adhesion, ohmic characteristics and secure the thermal reliability after the addition of heat treatment in the range of 150 ℃ to 600 ℃ in the atmosphere containing nitrogen and oxygen It can also be carried out.

On the other hand, in order to determine the characteristics of the ohmic electrode 180 in ohmic contact with the semiconductor layer 120 in the semiconductor light emitting device according to the first embodiment will be described with reference to the experimental example and the comparative example. In the experimental example, an Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode according to the first embodiment of the present invention was used, and the comparative example used a conventional general Cr / Au ohmic electrode.

Figure 6 is a graph showing the current-voltage characteristics of the ohmic electrode according to the experimental example and the comparative example of the present invention, line A is the current of the Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode- It is a voltage graph, and B is a current-voltage graph of the Cr / Au ohmic electrode which concerns on this comparative example.

In order to know the electrical characteristics of the ohmic electrode, ohmic resistance is calculated by the TLM method proposed by Professor shottky. The TLM method obtains a resistance R _T at 0V by measuring a current (I) -voltage (V) curve between two metal electrodes whose distances are divided into d ₁ , d ₂ , d ₃ , and d ₄ , respectively. After plotting the measured R _{T according} to the distance and extrapolating, the ohmic resistance can be calculated by the following equation.

Where R _T is the resistance [Ω] between the respective metal electrodes, R _S is the sheet resistance [Ω] of the semiconductor layer, d is the distance between the metal electrodes, Z is the width of the metal electrode, and ρ _C is the ohmic resistance. do.)

When the ohmic resistance of the ohmic electrode is calculated using the current-voltage graph of FIG. 6 and the TLM method, the Cr / Au ohmic electrode of the comparative example has an ohmic resistance of about 8.3 × 10 ⁻⁵ Ωcm ² , but this experimental example Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode has ohmic resistance of 7.4 x 10 ^-5 Ωcm ² to be. As described above, the Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode according to the present experimental example has lower ohmic resistance than the conventional Cr / Au ohmic electrode of the present comparative example without additional heat treatment after deposition, thereby lowering the driving voltage. Can lower the power consumption.

7 is a graph showing the light reflectivity of the ohmic electrode according to the experimental example and the comparative example of the present invention, the light reflectance in the 460nm wavelength band was measured. In the graph of FIG. 7, the A line shows the light reflectivity of the Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode according to the present experimental example, and the B line shows the light reflectance of the Cr / Au ohmic electrode according to the present comparative example. It is shown. In this case, the I line represents the light reflectivity of the Ag mirror as a reference line.

Referring to FIG. 7, the Cr / Au ohmic electrode according to the present comparative example shows a low light reflectivity of approximately 55% (B line), and the Ag nano dot layer / Ni / Al / Ti / Au ohmic according to the present example. The electrode shows high light reflectivity of approximately 88% (line A). Therefore, since the Ag nano dot layer / Ni / Al / Ti / Au ohmic electrode according to the present experimental example can reduce the absorption of light, the light output to the outside can be further improved.

As described above, the ohmic electrode 180 having the Ag nano dot layer / Ni / Al / Ti / Au structure is formed on the nitrogen polarity side of the semiconductor layer 120 and has a low ohmic resistance and high Light reflectance was maintained. This is because the Ag nano dot layer 181 improves charge injection characteristics into the semiconductor layer 120. In addition, these results show that the nano-dot layer is formed of at least one of Al and Au instead of Ag in an ohmic electrode having an Ag nano dot layer / Ni / Al / Ti / Au structure, and a Ni-Ti alloy, Ni, instead of Ni. At least one of Al alloy, Ti-Al alloy, Mg-Al alloy, Ta, Ti, W, W-Ti alloy is used, and instead of Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag- In alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, Al-Mg alloy is used, and instead of Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, Nb W Similar results could be obtained even if at least one metal layer of W-Ti alloy or at least one oxide film of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx was used and Al was used instead of Au. .

&Lt; Embodiment 2 >

Meanwhile, the ohmic electrode of the Ag nano dot layer / Ti / Cr / Au structure applied to the semiconductor light emitting device according to the second embodiment of the present invention may be applied to a semiconductor light emitting device having a horizontal structure. In the following, as an example of such a possibility, a semiconductor light emitting device according to a second embodiment of the present invention in which n-type electrodes and p-type electrodes are horizontally disposed will be described. In this case, a description overlapping with the above-described embodiment will be omitted or briefly described.

8 is a cross-sectional view illustrating a semiconductor light emitting device according to a second exemplary embodiment of the present invention.

Referring to FIG. 8, the semiconductor light emitting device includes a semiconductor layer 220 including an n-type layer 221, an active layer 222, and a p-type layer 223 sequentially formed on a substrate 210, and the n-type layer ( N-type electrode 230 formed in the exposed region of 121 and p-type electrode 240 formed on the p-type layer 223. Here, at least one of the n-type electrode 230 and the p-type electrode 240 is a nano dot layer 231/241, a contact layer 232/242, a reflective layer 233/243 formed on the semiconductor layer 220. And a diffusion barrier layer 234/244 and a capping layer 235/245, and are ohmic electrodes having a multilayer structure in ohmic contact with the semiconductor layer 220.

A manufacturing process of a semiconductor light emitting device having such a configuration will be described below with reference to FIGS. 9 to 11. 9 to 11 are cross-sectional views illustrating a manufacturing process of a semiconductor light emitting device according to a second exemplary embodiment of the present invention.

9, an n-type layer 221, an active layer 222, and a p-type layer 223 are stacked on the prepared substrate 210 to form a semiconductor layer 220 having a multilayer structure.

As the substrate 210, a sapphire substrate, a silicon carbide substrate, a silicon substrate, a zinc oxide substrate, a gallium arsenide substrate, a gallium phosphide substrate, or the like may be used, and a sapphire substrate is particularly preferable.

As the semiconductor layer 220, it is preferable to use one of a Si film, a GaN film, an AlN film, an InGaN film, an AlGaN film, an AlInGaN film, and a film containing the same. In this embodiment, after depositing a GaN film, an n-type impurity is implanted to form an n-type layer 221, and a GaN film as a barrier layer and an InGaN film as a well layer are alternately deposited to form an active layer 222 having a multi-well structure. After the GaN film was deposited thereon, p-type impurities were implanted to form the p-type layer 223. Although not shown, a buffer layer may be additionally formed between the substrate 210 and the n-type layer 221, and the buffer layer may relieve stress due to lattice mismatch between the substrate 210 and the n-type layer 221. Helps the smooth growth of the n-type layer 221 to be formed.

Referring to FIG. 10, some regions of the p-type layer 223 and the active layer 222 are mesa-etched to expose some regions of the n-type layer 230 on which the n-type electrode 240 is to be formed. Subsequently, in order to improve the interfacial properties with the subsequent layer, it is preferable to perform surface treatment on the semiconductor layer 220. For example, in the present embodiment, the semiconductor layer 220, that is, the surface of the n-type layer 221 and the surface of the p-type layer 223 exposed to the aqueous solution of aqua regia (HCl: H ₂ O = 3: 1) are approximately After soaking for 10 minutes, washing with deionized water, drying with nitrogen, and performing a first surface treatment, and before depositing a subsequent layer, that is, n-type electrode 230 and p-type electrode 240, with hydrochloric acid (HCl); Second surface treatment is performed by immersing in a 1: 1 mixture of deionized water for about 2 minutes and then drying. Of course, such primary and secondary surface treatments can be selectively performed or omitted depending on the desired purpose.

Referring to FIG. 11, Ag nanoparticles made of nano-sized dots are formed by forming Ag thinly on the exposed n-type layer 221 and p-type layer 223 by about 5 μm to 50 μm and then heat-treating in an atmosphere containing nitrogen. The dot layer 231/241 is formed. At this time, the Ag nano dot layer 231/241 is formed on the gallium polarity (Ga-face) of the n-type layer 221 and the p-type layer 223. Subsequently, a Ni contact layer 232/242, an Al reflective layer 233/243, a Ti diffusion barrier layer 234/244, and an Au capping layer 235/245 are stacked on the Ag nano dot layer 231/241. After this, it is patterned to form an n-type electrode 130 and a p-type electrode 140 having an Ag nano dot layer / Ni / Al / Ti / Au structure. In this case, the nano dot layer may be formed of at least one of Al and Au instead of Ag. Instead of Ni, at least one of Ni-Ti alloys, Ni-Al alloys, Ti-Al alloys, Mg-Al alloys, Ta, Ti, W, and W-Ti alloys is used, and Ag, Ag instead of Al. At least one of -Al alloy, Ag-Cu alloy, Ag-In alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, Al-Mg alloy is used, and Cr, Ru, Pt instead of Ti At least one metal layer of Ni, Pd, Ir, Rh, Nb W, and W-Ti alloys or an oxide film of at least one of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx, and Al instead of Au Can be used.

After the formation of the n-type electrode 230 and the p-type electrode 240 in order to improve adhesion, ohmic characteristics and secure thermal reliability, the heat treatment is performed in a range of 150 ° C to 600 ° C in an atmosphere containing nitrogen and oxygen. It is preferable to carry out.

Since the semiconductor light emitting device having the horizontal structure manufactured as described above, as the light generated in the active layer 222 is not absorbed by the n-type electrode 230 having high light reflectivity as shown in FIG. 11, most of the semiconductor light emitting device may be reflected and emitted to the outside. The light output can be further improved.

12 is a cross-sectional view illustrating a semiconductor light emitting device according to a first modified example of the present invention.

Referring to FIG. 12, in the semiconductor light emitting device, a semiconductor layer 220 is formed on a substrate 210 on which a diffuse reflection pattern 211 is formed. The diffuse reflection pattern 211 is preferably formed in a hemispherical structure, and because the hemispherical pattern 211 induces diffuse reflection of light generated in the active layer 222, the light output to the outside can be further improved.

In the horizontal semiconductor light emitting device manufactured as described above, the light generated in the active layer 220 is not absorbed by the n-type electrode 230 having high reflectivity, as in the horizontal structure, as shown in FIG. Since it can be emitted, the light output can be further improved.

As mentioned above, although this invention was demonstrated with reference to the above-mentioned Example and an accompanying drawing, this invention is not limited to this, It is limited by the following claims. Therefore, one of ordinary skill in the art will appreciate that the present invention can be variously modified and modified without departing from the technical spirit of the following claims.

1 is a cross-sectional view showing a semiconductor light emitting device according to a second embodiment of the present invention.

2 to 5 are cross-sectional views illustrating a process of manufacturing a semiconductor light emitting device according to a first embodiment of the present invention.

Figure 6 is a graph showing the current-voltage characteristics of the ohmic electrode according to the experimental example and the comparative example of the present invention.

7 is a graph showing the light reflectivity of the ohmic electrode according to the experimental example and the comparative example of the present invention.

8 is a cross-sectional view showing a semiconductor light emitting device according to a second embodiment of the present invention.

9 to 11 are cross-sectional views illustrating a process of manufacturing a semiconductor light emitting device according to a second embodiment of the present invention.

12 is a cross-sectional view of a semiconductor light emitting device according to a first modification of the present invention.

<Explanation of symbols for the main parts of the drawings>

110, 210: base material substrate 170: support substrate

120 and 220: semiconductor layers 121 and 221: n-type layers

122, 222: active layer 123, 223: p-type layer

130, 240 p-type electrode 180, 230: n-type electrode

Claims (11)

A semiconductor layer having a light emitting structure; An ohmic electrode having a nano dot layer, a contact layer, a reflective layer, a diffusion barrier layer, and a capping layer formed on the semiconductor layer; Including, The nano dot layer is formed on the nitrogen polar surface of the semiconductor layer, and formed of at least one material of Ag, Al, Au, The contact layer is formed of at least one of Ni, Ni-Ti alloys, Ni-Al alloys, Ti-Al alloys, Mg-Al alloys, Ta, Ti, W, W-Ti alloys, The reflective layer is formed of at least one material of Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag-In alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, Al-Mg alloy, The diffusion barrier layer is at least one metal layer of Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, Nb W, W-Ti alloys or at least one of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx Formed of one oxide film, The capping layer is a semiconductor light emitting device formed of at least one material of Au, Al. The method according to claim 1, The nano dot layer is a semiconductor light emitting device consisting of nano-size Ag dots formed by depositing Ag and heat treatment in a nitrogen atmosphere. The method according to claim 1, The nano dot layer is a semiconductor light emitting device formed to a thickness of 5 ~ 50Å. The method according to claim 1, The contact layer is formed of Ni, the reflective layer is made of Al, the diffusion barrier layer is made of Ti, and the capping layer is made of Au. The method according to claim 1, The contact layer is a semiconductor light emitting device formed to a thickness of 1Å to 50Å. The method according to claim 1, The reflective layer is a semiconductor light emitting device formed to a thickness of 500 kPa to 8000 kPa. The method according to any one of claims 1 to 5, The semiconductor layer includes an n-type layer, an active layer and a p-type layer, And the ohmic electrode is formed on the nitrogen polarity surface of the n-type layer. The method according to claim 1, The semiconductor layer is a semiconductor light emitting device is formed on the upper surface of the substrate having a hemispherical pattern formed on one surface. Forming a semiconductor layer having a light emitting structure; Forming a nano dot layer on the nitrogen polarity surface of the semiconductor layer; And Forming a contact layer, a reflective layer, a diffusion barrier layer, and a capping layer on the nano dot layer; Including, The nano dot layer is formed of at least one material of Ag, Al, Au, The contact layer is formed of at least one material of Ni, Ni-Ti alloy, Ni-Al alloy, Ti-Al alloy, Mg-Al alloy, Ta, Ti, W, W-Ti alloy, The reflective layer is formed of at least one material of Al, Ag, Ag-Al alloy, Ag-Cu alloy, Ag-In alloy, Ag-Mg alloy, Al-Cu alloy, Al-In alloy, Al-Mg alloy, The diffusion barrier layer is at least one metal layer of Ti, Cr, Ru, Pt, Ni, Pd, Ir, Rh, Nb W, and W-Ti alloys or at least one of RuOx, NiOx, IrOx, RhOx, NbOx, TiOx, TaOx, CrOx Formed by one oxide film, The capping layer is a method of manufacturing a semiconductor light emitting device formed of at least one material of Au, Al. The method according to claim 9, The nano dot layer is a method of manufacturing a semiconductor light emitting device is formed by depositing Ag on the nitrogen polar surface of the semiconductor layer and then heat-treating it in a nitrogen atmosphere. The method according to claim 9, And wherein the contact layer is formed of Ni, the reflective layer is made of Al, the diffusion barrier layer is made of Ti, and the capping layer is made of Au.

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