JP4982830B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a voltage amplification function that reduces the influence of power supply noise while reducing current consumption.

  In a digital integrated circuit of CMOS (complementary metal-insulating film-semiconductor) process, an analog / digital mixed integrated circuit that also integrates an analog circuit is generally used. An analog / digital converter (ADC) is used as an interface unit for connecting the analog circuit and the digital circuit, and the importance of the ADC is increasing.

  There are various ADCs such as successive approximation type, pipeline type, flash type, ΔΣ type and double integration type. However, in any system, a comparator that performs voltage comparison is required. Further, in such a semiconductor integrated circuit, a low current consumption operation is required for a comparator or the like due to factors such as operation using a battery as a power source and reduction of heat generation for stable operation.

  Such semiconductor integrated circuits are also widely used in in-vehicle devices, and there is a large power supply noise in the operating environment of these in-vehicle devices. Therefore, components such as a comparator having a high resistance to power supply noise are extremely important in order to accurately operate such an in-vehicle device.

  An example of a comparator intended to realize a low current consumption operation is disclosed in a patent document (Japanese Patent Laid-Open No. 2001-94425). The comparator disclosed in Patent Document 1 is a chopper type comparator that compares an input signal and a reference signal, and has the following configuration. That is, the comparator of Patent Document 1 includes a linear amplifier configured by a P-channel MOS transistor (insulated gate field effect transistor) and an N-channel MOS transistor connected in series between first and second power supplies. Different gate bias voltages are applied to the gates (control electrodes) of the P-channel MOS transistor and the N-channel MOS transistor of this linear amplifier. First and second capacitive elements are arranged between the gates and the input terminals of the P and N channel MOS transistors of these linear amplifiers, respectively. In a state where a bias voltage is applied to the gate of the transistor, a reference voltage is applied to the capacitor element, and the capacitor element is precharged from the reference voltage. Thereafter, after the supply of the gate bias voltage and the reference voltage is stopped, the input signal is transmitted to the first and second capacitive elements. The gate potentials of the P and N channel MOS transistors of the linear amplifier are at a voltage level corresponding to the difference between the input voltage and the reference voltage, and an output voltage of the linear amplifier is generated according to the difference voltage.

  In this Patent Document 1, the gate potential of the linear amplifier transistor is set by different bias voltages, and the amount of through current flowing through the P and N channel MOS transistors of the linear amplifier when the first and second capacitive elements are precharged. To reduce current consumption. Further, during the amplification operation, an output signal is generated according to the difference between the input signal and the reference voltage, and the output voltage amplitude of the one-stage chopper type comparator becomes small. This Patent Document 1 shows a configuration in which a second chopper type comparator for amplifying the output voltage of the chopper type comparator by capacitive coupling is provided to compensate for the small output voltage amplitude. The second chopper type comparator is short-circuited at the input and output during precharging, and amplifies by receiving the output voltage of the first chopper type comparator via the capacitive element at the input stage during amplification operation.

  Further, another configuration of a comparator for realizing low current consumption operation is disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 10-107600). The comparator disclosed in Patent Document 2 receives a differential input voltage and a differential input reference voltage, and compares and compares the voltage levels of these input voltages with a fully differential chopper type comparison means and a fully differential chopper type comparison. And a fully differential amplification means for receiving the differential output from the means via capacitive coupling. The comparator has a reset operation period and a comparison operation period, and the fully differential amplification unit operates as an output latch unit that is offset-compensated in the comparison operation period, and generates and outputs a differential digital voltage. .

  Patent Document 2 reduces the number of elements of the comparator circuit by connecting the positive phase input terminal and the negative phase input terminal of the fully differential chopper type comparator to the positive phase output terminal and the negative phase output terminal, respectively. The amount of through current in the fully differential amplification means is suppressed during the comparison operation period to reduce the power consumption of the entire comparator circuit.

JP 2001-94425 A JP-A-10-107600

  In the configuration of the comparator disclosed in Patent Document 1 described above, an input signal and a reference voltage are each transmitted to the gate of the MOS transistor of the linear amplifier in the output stage via a capacitive element. A differential signal is generated by this capacitive coupling. However, it is different from the configuration that receives the input signal and the reference voltage in the differential stage composed of the transistors that operate in a complementary manner, and the input signal is detected with high accuracy due to the influence of the parasitic capacitance in the reference voltage and the input signal propagation path. There arises a problem that the reference voltage cannot be compared. Further, during the amplification operation, the differential signal between the input signal and the reference voltage is given to the gate of the MOS transistor of the linear amplifier, which is conducted together with the MOS transistor, and the through current flows from the high-side power supply node to the low-side power supply node. Flows and current consumption increases.

  In addition, the difference signal between the same input voltage and reference voltage is given to the transistor of this linear amplifier, which is equivalent to driving the linear amplifier with a single-phase (single ent) signal. When power supply noise occurs in the high-side power supply node and the low-side power supply node, this power supply noise cannot be canceled out, and there is a problem that the influence of the power supply noise appears on the output voltage.

  Further, in the configuration shown in Patent Document 2, the differential input voltage and the differential input reference voltage are given to the fully differential chopper type comparison means of the input unit, and the input unit has a differential configuration. Yes. Therefore, this differential pair can reduce the influence of power supply noise. However, since amplification is performed using the voltage between the high-side power supply and the low-side power supply, the degree of influence of the power supply noise depends on the power supply noise removal capability of the differential pair of transistors. However, there are actually manufacturing variations in MOS transistors, offset voltages in differential transistors, and it is difficult to expect high power supply noise removal capability for differential pairs. The problem arises that it cannot be removed.

  In the configuration shown in Patent Document 2, in the fully differential type amplifying means of the output stage, current is always supplied in the differential stage, and the output of the fully differential chopper type comparing means is diode-connected. The current always flows in this path, and the current is consumed quantitatively, and it is difficult to reduce the current consumption.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit that performs an amplifying operation with a low current consumption and excellent power source noise resistance.

  The semiconductor integrated circuit according to the present invention includes at least one amplifier circuit that receives the first and second input voltages, and differentially amplifies and outputs them. The amplifier circuit includes a pair of differential transistors that receive first and second input voltages at their respective control electrodes, and a constant current stage coupled between the pair of differential transistors and a first power supply. Including. The constant current stage is turned on in response to the first control signal and allows a constant current to flow between the pair of differential transistors and the first power supply.

The amplifier circuit further includes a pair of capacitive elements electrically connected to each of the pair of differential transistors, and a pair of pre-couples coupled between the pair of capacitive elements and the second power source. And a charge transistor. Each of the pair of capacitive elements is charged or discharged according to the amount of current flowing through the corresponding transistor of the pair of differential transistors. The pair of precharge transistors electrically couples an electrode electrically coupled to the differential transistor of the pair of capacitive elements to the second power supply in response to the second control signal.
In one aspect of the invention, the constant current stage includes first and second transistors connected in series between a pair of differential transistors and a first power supply. The first transistor is coupled to a pair of differential transistors and selectively conducts in response to a first control signal, and the second transistor is coupled to the first power source to provide a constant current. Shed.
In another aspect of the invention, the constant current stage is coupled between a first power supply and the pair of differential transistors and is non-conductive when the voltage level of its control electrode is the voltage level of the first power supply. A first transistor that enters a state; a first control transistor that sets a control electrode of the first transistor to one of a voltage level of the first power supply and a constant current bias voltage level according to a first control signal; The first transistor control electrode and the reference current source are selectively coupled according to the control signal 1, and the first transistor is turned on when the voltage level of the control electrode is the voltage level of the first power supply. A second control transistor having a polarity opposite to that of the first control transistor and a control electrode of the second control transistor coupled to the control electrode of the first transistor. The voltage of the control electrode of the first transistor is coupled to set the constant current bias voltage level to the current sources, and a third control transistor of the same polarity as the first control transistor.

  The amplification operation is performed using the voltage of the first power source to which the constant current stage is coupled, and the voltage of the second power source is not used. Therefore, only one of the voltages of the first and second power supplies is used, and even if noise occurs between the first and second power supplies, the influence of the noise can be suppressed. Noise resistance can be increased.

  Further, the precharge voltage of the first and second capacitive elements is merely discharged by the constant current stage using the first and second power supply voltages, and the current consumption is sufficiently suppressed.

1 is a diagram showing a configuration of a charge discharge amplifier according to a first embodiment of the present invention. FIG. 2 is a timing diagram illustrating an operation of the amplifier illustrated in FIG. 1. It is a figure which shows the structure of the charge discharge type amplifier according to Embodiment 2 of this invention. FIG. 4 is a timing diagram illustrating an operation of the amplifier illustrated in FIG. 3. It is a figure which shows the structure of the amplifier according to Embodiment 3 of this invention. It is a figure which shows the structure of the amplifier of the example of a change of Embodiment 3 of this invention. It is a figure which shows roughly the structure of the semiconductor integrated circuit according to Embodiment 4 of this invention. FIG. 8 is a timing chart showing an operation of the semiconductor integrated circuit (comparator) shown in FIG. 7. It is a figure which shows an example of a structure of the latch shown in FIG. It is a figure which shows roughly the structure of the semiconductor integrated circuit (comparator) according to Embodiment 5 of this invention. FIG. 11 is a timing diagram illustrating an operation of the comparator illustrated in FIG. 10. It is a figure which shows roughly the structure of the semiconductor integrated circuit (successive approximation ADC) according to Embodiment 6 of this invention. It is a flowchart which shows the conversion operation | movement of ADC shown in FIG. FIG. 13 is a timing chart showing a conversion operation of the ADC shown in FIG. 12. It is a figure which shows roughly the connection aspect of the capacitive element of the capacity | capacitance array of ADC of the modification of Embodiment 6 of this invention.

[Embodiment 1]
FIG. 1 shows a configuration of an amplifier included in the semiconductor integrated circuit according to the first embodiment of the present invention. The amplifier shown in FIG. 1 has a configuration of a charge discharge amplifier, and generates an amplification result of a differential input signal by charging and discharging a capacitive element.

  In FIG. 1, the amplifier is in accordance with P-channel MOS transistors (insulated gate field effect transistors) MP1 and MP2 receiving input signals VIP and VIN at their gates (control electrodes), and a control signal (first control signal) ZVP0. A constant current stage 4 for supplying a constant current Ib to the common source node 2 of these MOS transistors MP1 and MP2, and a current / voltage conversion capacitor in which each first electrode is coupled to the high-side power supply node (VDD). Elements CL1 and CL2 and N channel MOS transistors MN1 and MN2 for charging capacitive elements CL1 and CL2 according to a precharge control signal (second control signal) VP1 are included.

  The constant current stage 4 includes P-channel MOS transistors MPC1 and MPC2 connected in series between a high-side power supply node (hereinafter simply referred to as a power supply node) VDD and a common source node 2, and a MOS transistor MPC1 and a current mirror stage. A P-channel MOS transistor MPC3 is included. Comparison control signal ZVP0 is applied to the gate of MOS transistor MPC2. MOS transistor MPC3 has its gate and drain interconnected and operates as a master of the current mirror stage. During operation, mirror current Ib1 of current Ib flowing through MOS transistor MPC3 flows through MOS transistor MPC1. When MOS transistors MPC1 and MPC3 have the same size (ratio of channel width W to channel length L, W / L), currents Ib having the same magnitude flow through MOS transistors MPC1 and MPC3. The drain node of MOS transistor MPC3 is coupled to a constant current drive unit (not shown). The configuration of the constant current driving unit is arbitrary as long as it is a circuit that absorbs the constant current Ib. In order to reduce current consumption, a configuration in which the constant current driving unit supplies the constant current Ib only during the comparison operation may be used.

  Capacitance elements CL1 and CL2 have respective first electrodes coupled to power supply node VDD, and respective second electrodes coupled to output nodes 1a and 1b, respectively. The drain nodes of MOS transistors MP1 and MP2 are electrically connected to output nodes 1a and 1b, respectively, and supply current in accordance with input signals VIP and VIN.

  MOS transistors MN1 and MN2 are respectively connected between output nodes 1a and 1b and a low-side power supply node (hereinafter referred to as a ground node) VSS, and electrically connect output nodes 1a and 1b to the ground node according to precharge control signal VP1. And precharges the output nodes 1a and 1b to the low-side power supply voltage (hereinafter referred to as the ground voltage) VSS.

  Output voltages VOP and VON are generated at output nodes 1a and 1b, respectively.

  FIG. 2 is a timing chart showing the operation of the amplifier shown in FIG. The operation of the amplifier shown in FIG. 1 will be described below with reference to FIG.

  When precharge control signal VP1 becomes H level at time t0, MOS transistors MN1 and MN2 are turned on. At this time, the comparison amplification control signal ZVP0 is at the H level, the MOS transistor MPC2 is non-conductive, and the constant current stage 4 is in the output high impedance state.

  Therefore, output nodes 1a and 1b are driven to the level of ground voltage VSS, and the first electrode and the second electrode (counter electrode) of capacitive elements CL1 and CL2 are set to power supply voltage VDD and ground voltage VSS, respectively.

  In a period PR1 between time t0 and time t1, the precharge control signal VP1 is at the H level, and current is supplied from the power supply node VDD (the power supply node and its voltage are indicated by the same symbol) to the capacitive elements CL1 and CL2. Current is consumed. In precharge period PR1, voltages VOP and VON of output nodes 1a and 1b in the previous amplification cycle are precharged to the level of ground voltage VSS, respectively.

  When precharge control signal VP1 attains L level and MOS transistors MN1 and MN2 are both rendered non-conductive, comparison amplification control signal ZVP0 falls to L level at time t1. Accordingly, MOS transistor MPC2 in constant current stage 4 is turned on, and mirror current Ib1 of constant current Ib is applied to common source node 2 of MOS transistors MP1 and MP2.

  These MOS transistors MP1 and MP2 receive input signals VIP and VIN at their gates, respectively, and after current Ib1 supplied from constant current stage 4 is distributed to MOS transistors MP1 and MP2, output nodes 1a and 1b And the voltage levels of output voltages VOP and VON at output nodes 1a and 1b rise.

  The amount of current supplied from each of MOS transistors MP1 and MP2 varies depending on the voltage levels of input signals VIP and VIN. When the input signal VIP is lower than the input signal VIN, the amount of current flowing through the MOS transistor MP1 is larger than the amount of current flowing through the MOS transistor MP2, and the voltage level of the output voltage VOP is the voltage of the output voltage VON. Be higher than level. On the contrary, when the input signal VIP is higher than the input signal VIN, the current flowing through the MOS transistor MP2 becomes larger than the current flowing through the MOS transistor MP1, and the voltage level of the output voltage VON becomes the output voltage VOP. Higher than. By MOS transistors MP1 and MP2, a current flows through output nodes 1a and 1b in accordance with the difference in voltage level between input signals VIP and VIN, and is converted into a voltage signal by the accumulated charges of capacitive elements CL1 and CL2. In this case, output nodes 1a and 1b are charged with positive charges (negative charges are discharged).

  When the voltage difference between output voltages VOP and VON is sufficiently increased, comparison amplification control signal ZVP0 attains H level at time t2, MOS transistor MPC2 is turned off in constant current stage 4, and supply of constant current Ib1 is stopped. Is done. Necessary processing is performed on the differential output voltage signals of the output voltages VOP and VON in a next stage circuit (not shown), and final output voltages corresponding to the input signals VIP and VIN are generated.

  The precharge, comparison (charging) periods PR1 and PR2 and the subsequent holding period from time t0 to time t3 are one amplification operation cycle.

From the relationship between the capacitance C and the stored charge Q, Q = C · V, the output voltages VOP and VON are expressed by the following equations:
VOP = (amount of positive charge charged in CL1) / C1,
VON = (positive charge amount charged to CL2) / C2
Here, C1 and C2 indicate capacitance values of the capacitive elements CL1 and CL2, and the charge charge is a positive charge. If the amount of current supplied to the output nodes 1a and 1b is large, the charge amount of the positive charge is large. And the voltage level becomes higher.

  In the configuration of the amplifier shown in FIG. 1, in the period PR2, the current Ib1 is distributed and supplied to the output nodes 1a and 1b via the constant current stage 4, and the ground voltage VSS is not used during this period (MOS transistor MN1). And MN2 are non-conductive). Therefore, even if noise occurs between the power supplies VDD and VSS, only the power supply voltage VDD on one side is used. Therefore, the influence of the power supply noise affects the amplification operation of the voltages VOP and VON of the output nodes 1a and 1b. The power supply noise resistance can be increased.

  In the precharge period PR1, the counter electrodes (first and second electrodes) of the capacitive elements CL1 and CL2 are only charged and discharged to the power supply voltage VDD level and the ground voltage VSS level, respectively. Even if the power supply noise is generated, the influence of the same power supply noise appears on the voltages VOP and VON of the output nodes 1a and 1b, and the influence of the noise is canceled in the amplification operation period PR2. This power supply noise has no effect.

  In the precharge period PR1, the positive charge amount discharged from the output nodes 1a and 1b is substantially the same as the charge amount supplied by the current Ib1 supplied from the constant current stage 4 in the comparison amplification period PR2. In this comparative amplification period PR2, mirror current Ib1 (= Ib) of constant current Ib is supplied to output nodes 1a and 1b separately from power supply node VDD of constant current stage 4 according to input signals VIP and VIN. . Therefore, in the comparative amplification period PR2, the current Ib1 is maintained at a substantially constant value as shown in FIG. Here, positive charges are discharged from the first electrodes of the capacitive elements CL1 and CL2 to the power supply node VDD in accordance with the increase in the levels of the voltages VOP and VON of the output nodes 1a and 1b. The voltage VDD is maintained.

  The range of the input voltages VIP and VIN is 0V (volt) to (VDD−Odv + Vthp) V. Here, Odv is an overdrive voltage, which is the minimum value of the drain-source voltage required for normal operation of the MOS transistors MP1 and MP2. Vthp indicates the threshold voltage of the MOS transistors MP1 and MP2, and is a negative value.

  In the constant current stage 4, MOS transistors MPC1-MPC3 are used. However, the constant current stage 4 is not a current mirror stage configuration, and any configuration can be used as long as the constant current Ib1 is supplied to the MOS transistors MP1 and MP2 at a predetermined timing. . Further, as the MOS transistor MPC2 for controlling the current, other elements such as a complementary switch may be used. An element such as a complementary switch (CMOS transmission gate) may be used for MOS transistors MN1 and MN2.

  As described above, according to the first embodiment of the present invention, the first and second input signals are received by the differential transistor, and the precharge node of the capacitive element is set according to the voltage difference of the differential input signal. Current is supplied from the first power supply, and current / voltage conversion is performed using a capacitive element to generate an output voltage. Therefore, only one power supply (high-side power supply voltage) is used during the amplification operation, and the power supply noise resistance can be improved. In addition, during the precharge operation, only positive charges are discharged to the low-side power supply node, and the discharge charge amount is the same as the supply current amount during the comparison amplification operation, and the consumption current can be sufficiently suppressed. it can. Further, during the comparison amplification operation, positive charges are discharged to the power supply node in accordance with the increase in the voltage levels of the output voltages VOP and VON, and the electrodes (first electrodes) connected to the power supply nodes of the capacitive elements CL1 and CL2 The voltage level is maintained at the power supply voltage VDD. The amount of positive charge supplied from the constant current stage 4 from the power supply node is compensated by the amount of positive charge discharged to the power supply node VDD via the capacitive elements CL1 and CL2, and current consumption can be reduced.

[Embodiment 2]
FIG. 3 shows a structure of the charge discharge amplifier according to the second embodiment of the present invention. The amplifier shown in FIG. 3 is equivalent to a configuration in which the P channel MOS transistor and the N channel MOS transistor of the charge discharge amplifier according to the first embodiment shown in FIG. 1 are replaced with an N channel MOS transistor and a P channel MOS transistor, respectively. is there.

  In FIG. 3, the amplifier operates in accordance with a precharge control signal VP 0 between N-channel MOS transistors MN 3 and MN 4 that receive input signals VIP and VIN at their gates, and a common source node 14 of MOS transistors MN 3 and MN 4 and a ground node Constant current stage 10 for supplying a constant current, capacitive elements CL3 and CL4 for converting the discharge currents of MOS transistors MN3 and MN4 into voltage, and second electrode nodes (output nodes) of capacitive elements CL3 and CL4 according to comparison amplification control signal ZVP1 1a, 1b) includes P-channel MOS transistors MP3 and MP4 for precharging power supply voltage VDD level. MOS transistors MN3 and MN4 discharge output nodes 1b and 1a according to input signals VIP and VIN, respectively.

  Constant current stage 10 includes N channel MOS transistors MNC2 and MNC1 connected in series between a common source node 14 and a ground node, and an N channel MOS transistor MNC3 for supplying a constant current Ib. Comparative amplification control signal VP0 is applied to the gate of N channel MOS transistor MNC2. MOS transistors MNC1 and MNC3 have their gates connected to each other, and MOS transistor MNC3 has its gate and drain connected to each other. Therefore, the MOS transistors MNC3 and MNC1 constitute a current mirror stage, and in operation, the mirror current Ib1 of the constant current Ib flowing through the MNC3 flows through the MOS transistor MNC1. The constant current Ib is given from a constant current supply unit (not shown).

  FIG. 4 is a timing chart showing the operation of the amplifier shown in FIG. The operation of the amplifier shown in FIG. 3 will be described below with reference to FIG.

  When one cycle starts at time t10, precharge control signal ZVP1 falls to the L level, and MOS transistors MP3 and MP4 are turned on. At this time, the comparison amplification control signal VP0 is at L level, the MOS transistor MNC2 is non-conductive, and the discharge paths of the MOS transistors MN3 and MN4 are cut off. Therefore, the second electrodes (output nodes 1a and 1b) of capacitive elements CL3 and CL4 are charged to power supply voltage VDD level via MOS transistors MP3 and MP4. When the precharge operation is completed, precharge control signal ZVP1 becomes H level, MOS transistors MP3 and MP4 are turned off, and the precharge operation of capacitive elements CL3 and CL4 is stopped via output nodes 1a and 1b. Output nodes 1a and 1b are maintained at the power supply voltage level.

  Next, at time t11, the comparison amplification control signal VP0 rises to H level, the MOS transistor MNC2 becomes conductive, and a constant current Ib1 (= Ib) flows between the common source node 14 and the ground node. This constant current Ib1 is distributed to MOS transistors MN3 and MN4 according to the voltage levels of input signals VIP and VIN. These MOS transistors MN3 and MN4 discharge the charge of capacitive elements CL4 and CL3, and the voltage levels of output nodes 1b and 1a decrease according to input signals VIP and VIN. In FIG. 4, as an example, the input signal VIN is at a higher voltage level than the input signal VIP, and the discharge amount of the output voltage VOP of the output node 1a is smaller than the discharge amount of the output voltage VON of the output node 1b. Indicated.

  When voltage levels of output voltages VON and VOP are determined according to input signals VIP and VIN, comparison amplification control signal VP0 attains L level at time t12, MOS transistor MNC2 is turned off, and constant current driving operation of constant current stage 10 Is stopped. Thereby, output voltages VOP and VON of output nodes 1a and 1b are set to voltage levels corresponding to input signals VIN and VIP, respectively. In this case, output voltages VOP and VON are represented by the following equations when the capacitance values of capacitive elements CL3 and CL4 are represented as C3 and C4.

VOP = VDD− (positive charge discharged from CL3) / C3,
VON = VDD− (positive charge discharged from CL4) / C4
The voltage range of the input signals VIP and VIN is (Odvn + Vthn) V to VDD. Here, Odvn represents the overdrive voltage of the MOS transistors MN3 and MN4, and Vthn represents the threshold voltage of the MOS transistors MN3 and MN4.

  Also in the amplifier shown in FIG. 3, the amount of charge supplied from the power supply node VDD to the capacitive elements CL3 and CL4 during the precharge period PR1 is equal to the current Ib via the constant current stage 10 to the ground node during the comparison amplification period PR2. It is almost the same as the amount of charge discharged by flowing (the precharge period only charges the voltage of the output node in the previous cycle to the power supply voltage level). In the comparative amplification period PR2, a constant current Ib1 is discharged according to the accumulated charges of the capacitive elements CL3 and CL4.

  In the amplifier shown in FIG. 3, in the comparative amplification period PR2, the ground node VSS is discharged while being separated from the power supply node to perform amplification and output voltage generation. Therefore, it is difficult to be affected by the voltage change of the power supply voltage VDD, and resistance to power supply noise can be increased.

  In the amplifier shown in FIG. 3, any structure can be used as the constant current stage 10 as long as the constant current Ib1 can flow through the MOS transistors MN3 and MN4 during the comparison amplification operation. The MOS transistors MP3, MP4, and MNC2 may be configured using complementary switches.

  Since the amplifier shown in FIG. 3 generates the output voltage mainly using the ground voltage VSS during the comparison amplification operation, it is not easily affected by the voltage change of the power supply voltage VDD. Therefore, the amplifier according to the first embodiment shown in FIG. 1 and the amplifier shown in FIG. 3 are selectively used as follows as an example. That is, when the fluctuation of the power supply voltage VDD is small, there is a high possibility that noise is generated in the ground voltage. When the fluctuation of the ground voltage VSS is small using the amplifier shown in the first embodiment, the power supply voltage The amplifier according to the second embodiment shown in FIG. 3 is used. By using this properly, the influence of power supply noise can be reduced.

  As described above, according to the second embodiment of the present invention, after the capacitor element is precharged, the charge of the capacitor element is discharged. Therefore, at the time of the comparative amplification operation, that is, at the time of discharging the precharge charge of the capacitive element, only the low-side power supply voltage (ground voltage) is used, and the influence of the voltage change of the power supply voltage VDD is small and the power supply noise Resistance can be increased. Further, at the time of precharging, only a current for compensating the amount of electric charge discharged in the previous cycle is supplied from the power supply node, so that current consumption can be reduced.

[Embodiment 3]
FIG. 5 shows a structure of the amplifier according to the third embodiment of the present invention. The amplifier shown in FIG. 5 includes an amplifier body 20 and a bias circuit 25 that controls the charging current during the comparative amplification operation of the amplifier body 20. The configuration of the amplifier body 20 is the same as that of the amplifier shown in FIG. 1 except for the P-channel MOS transistor MPC1, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The P channel MOS transistor MPC1 and the bias circuit 25 constitute a constant current stage. P-channel MOS transistor MPC1 is connected between common source node 2 of MOS transistors MP1 and MP2 and power supply node VDD.

  Bias circuit 25 is connected between MOS transistor MPC1 and P-channel MOS transistor PMC3 forming a current mirror stage, and between the gates of MOS transistors MPC1 and MPC3 and power supply node VDD, and has a P-channel receiving comparison amplification control signal ZVP0 at the gate. MOS transistor MPC4 includes an N-channel MOS transistor MNC4 connected between P-channel MOS transistor MPC3 and a constant current driver (not shown) and receiving comparison amplification control signal ZVP0 at its gate.

  In the configuration of the bias circuit 25 shown in FIG. 5, in the precharge period PR1, the comparison amplification control signal VP0 is at the L level, the MOS transistor MPC4 is in a conductive state, and the MOS transistor MNC4 is in a nonconductive state. Therefore, the gate of MOS transistor MPC3 is coupled to the power supply node, MOS transistors MPC1 and MPC3 are maintained in a non-conductive state, and the constant current supply to MOS transistors MP1 and MP2 is stopped.

  On the other hand, when the comparison amplification control signal VP0 is set to H level during the comparison amplification period, the MOS transistor MPC4 is turned off and the MOS transistor MNC4 is turned on. Therefore, constant current Ib flows through MOS transistors MPC3 and MNC4, and a mirror current of constant current Ib flows through MOS transistor MPC1.

  The amplification operation of amplifier body 20 is similar to the operation of the amplifier of the first embodiment, and detailed description thereof will not be repeated.

  In the configuration of the third embodiment, the comparison amplification current is supplied from power supply node VDD via MOS transistor MPC1 only during the comparison amplification operation period. Only one MOS transistor MPC1 is connected between common source node 2 of MOS transistors MP1 and MP2 and the power supply node, and MOS transistors connected in series between power supply node VDD and common source node 2 Can be reduced. Thereby, the voltage drop in MOS transistor MPC2 in the amplifier circuit according to the first embodiment shown in FIG. 1 can be reduced, and even if power supply voltage VDD decreases, MOS transistor MPC1 is reliably maintained in a conductive state. A constant current can be supplied to the common source node 2, and a stable amplification operation can be performed even under a low power supply voltage.

  In the amplifier shown in FIG. 5, the input signals VIP and VIN have a voltage range from 0V to (VDD−Odv + Vthp) V.

[Example of change]
FIG. 6 is a diagram showing a configuration of a modification of the third embodiment of the present invention. In FIG. 6, the amplifier includes an amplifier body 30 and a bias circuit 35 that controls a current during the comparative amplification operation of the amplifier body 30. The configuration of the amplifier main body 30 excluding the MOS transistor MNC1 is the same as the configuration of the amplifier shown in FIG. 3, and the corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. MOS transistor MNC1 is connected between common source node 14 of MOS transistors MN3 and MN4 and ground node VSS.

  The bias circuit 35 is compared with the N-channel MOS transistor MNC5 constituting the current mirror stage with the MOS transistor MNC1, and the P-channel MOS transistor MPC4 connected in series between the MOS transistor MNC5 and a constant current supply unit (not shown). N channel MOS transistor MNC6 coupling the gates of MOS transistors MNC1 and MNC5 to the ground node according to amplification control signal ZVP0.

  MOS transistor MNC5 has its gate and drain interconnected, and in operation, a mirror current of the current flowing through MOS transistor MNC5 flows through MOS transistor MNC1.

  During the precharge operation period, the comparison amplification control signal ZVP0 is at the H level, the MOS transistor MNC6 is conductive, and the MOS transistor MPC4 is nonconductive. Accordingly, the MOS transistors MPC4, MNC5, and MNC6 are all turned off and the constant current driving operation is stopped. At this time, in amplifier body 30, precharge control signal ZVP1 of MOS transistors MP3 and MP4 is at L level, and output nodes 1a and 1b are precharged to the power supply voltage level.

  During the comparative amplification operation, the comparative amplification control signal ZVP0 is at L level and the precharge control signal ZVP1 is at H level. In this state, a mirror current of constant current Ib flows between common source node 14 and ground node by MOS transistors MPC4, MNC5 and MNC6, output nodes 1a and 1b are discharged, and output voltages of output nodes 1a and 1b are discharged. VOP and VON are set to voltage levels corresponding to input signals VIP and VIN.

  The configuration of the amplifier shown in FIG. 6 is the same as that in which the conductivity type of the MOS transistor of the amplifier shown in FIG. 5 is reversed and the voltage polarity of the power supply node is reversed, and is the same as the amplifier shown in FIG. An effect can be obtained. In this case, the voltage range of the input signals VIP and VIN can be set from (Odvn + Vthn) V to VDD.

  As described above, according to the third embodiment of the present invention, the transistor that supplies the constant current during the comparison amplification operation of the amplifier is configured by the current mirror stage, and the current mirror operation is selectively performed according to the comparison amplification control signal. It is activated. Therefore, the number of transistors between the common source node and the power supply node or the ground node can be reduced, and the comparison and amplification operation can be reliably performed even under a low power supply voltage. Further, the same effects as those of the first and second embodiments can be obtained.

[Embodiment 4]
FIG. 7 schematically shows a structure of a semiconductor integrated circuit according to the fourth embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 7 includes an amplifier 50 and a latch 60 that latches output voltages VOP and VON of the amplifier 50 in accordance with a latch control signal VLT. As the amplifier 50, any of the amplifiers shown in FIGS. 1, 3, 5, and 6 may be used. The amplifier 50 differentially amplifies the input signals VIP and VIN by a charge discharging operation to generate output voltages VOP and VON. The latch 60 latches the output signal of the amplifier 50 according to the latch control signal VLT and generates the output signal DOUT. The output signal of the latch 60 may be complementary signals VOUTP and VOUTN.

  The output signal DOUT (or VOUTPVOUTVOUTN) of the latch 60 can indicate the magnitude comparison result of the input signals VIP and VIN, and the amplifier 50 and the latch 60 can constitute a comparator for comparing the input signals.

  FIG. 8 is a diagram showing the operation timing of the comparator shown in FIG. 7 and 8 show the precharge control signal VPC1 and the comparative amplification control signal VPC0. These control signals VPC1 and VPC0 correspond to the control signals shown in the first to third embodiments, respectively.

  As shown in FIG. 8, the precharge control signal VPC1 is activated in the period PR1, and the amplifier 50 precharges the internal node. Next, after completion of precharge, the comparative amplification control signal VPC0 is activated in a period PR2 starting from time t21, and the internal charge is discharged (charged) in accordance with the input signals VIP and VIN in the amplifier 50, thereby generating output voltage signals VOP and VON. To do.

  After completion of the comparison and amplification operation in the amplifier 50, the latch control signal VLT is activated at time t22. In the period PR3, the latch 60 latches the output voltage signals VOP and VON of the amplifier 50, and the signal DOUT (VOUTP) indicating the determination result is displayed. , VOUTN).

  That is, by driving the latch control signal VLT to the active state after the comparison amplification operation in the amplifier 50 is completed, the amplification signal of the amplifier 50 can be reliably latched and an accurate voltage comparison result can be obtained as a CMS level signal. .

  FIG. 9 is a diagram showing an example of the configuration of the latch 60 shown in FIG. In FIG. 9, a latch 60 amplifies and latches the output signals VOP and VON of the amplifier 50, a buffer circuit 75 for buffering the output signal of the latch type sense amplifier 70, and a buffer circuit 75. And a set / reset flip-flop (RS flip-flop) 80 that generates complementary output signals VOUTP and VOUTN as the determination result signal DOUT.

  Latch type sense amplifier 70 includes input N-channel MOS transistors MN11 and MN12, positive feedback N-channel MOS transistors MN13 and MN14 connected in parallel to each of these MOS transistors MN11 and MN12, and latch operation control N-channel. MOS transistors MN15 and MN16, P channel MOS transistors MP11 and MP12 for precharge control of the internal node, and P channel MOS transistors MP13 and MP14 for positive feedback connected in parallel with these MOS transistors MP11 and MP12, respectively. Including.

  MOS transistors MN11 and MN13 are connected in parallel between internal node 72a and ground node, and MOS transistors MN12 and MN14 are connected in parallel between internal node 72b and ground node. MOS transistors MN11 and MN12 receive output signals VOP and VON of amplifier 50 at their gates, and MOS transistors MN13 and MN14 have their gates electrically connected to internal nodes 72b and 72a.

  MOS transistors MP11 and MP13 are connected in parallel to each other between the power supply node and internal node 74a, and MOS transistors MP12 and MP14 are connected in parallel to each other between the power supply node and internal node 74b. MOS transistors MP11 and MP12 receive latch control signal VLT at their gates, and MOS transistors MP13 and MP14 have their gates connected to internal nodes 74b and 74a.

  Connected between MOS transistor MN15 and internal nodes 72a and 74a, and receives a latch control signal VLT at its gate. MOS transistor MN16 is connected between internal nodes 72b and 74b and receives a latch control signal VLT at its gate.

  Buffer circuit 75 receives a plurality of stages (three stages in this embodiment) of cascaded inverter buffers IV1-IV3 that receive a signal on internal node 74a of latch type sense amplifier 70, and a signal on internal node 74b. A plurality of stages (three stages in this embodiment) of cascaded inverter buffers IV4-IV6 are included.

  RS flip-flop 80 includes NAND gates G1 and G2 receiving output signals of inverter buffers IV3 and IV6 at their first inputs, respectively. The output node of NAND gate G1 is coupled to the second input of NAND gate G2, and the output node of NAND gate G2 is coupled to the second input node of NAND gate G1. Output signals VOUTP and VOUTN are output from NAND gates G1 and G2 as determination result data DOUT.

  Next, the operation of the latch circuit shown in FIG. 9 will be described. When latch control signal VLT is at the inactive L level, MOS transistors MP11 and MP12 are conductive, and MOS transistors MN15 and MN16 are nonconductive. Therefore, internal nodes 74a and 74b are maintained at power supply voltage VDD level by MOS transistors MP11 and MP12. On the other hand, internal nodes 72a and 72b are isolated from internal nodes 74a and 74b, and at internal nodes 72a and 72b, which are outputs of MOS transistors MN13 and MN14, are at the L level.

  Internal nodes 74a and 74b are at the power supply voltage level, output signals of inverter buffers IV3 and IV6 of buffer circuit 75 are at L level, and output signals VOUTP and VOUTN of RS flip-flop 80 are both at H level (power supply voltage VDD level). Maintained.

  Next, when the comparison amplification operation in the previous stage amplifier 50 is completed, the latch control signal VLT is set to H level (activated). Accordingly, MOS transistors MP11 and MP12 are turned off, MOS transistors MN15 and MN16 are turned on, internal nodes 74a and 72a are electrically connected, and internal nodes 74b and 72b are electrically connected. At this time, output voltage signals VOP and VON of amplifier 50 are in a definite state, and conductances of MOS transistors MN11 and MN12 are set to values corresponding to these output voltage signals VOP and VON.

  Consider a state where the voltage signal VOP is higher than the voltage signal VON. In this state, the conductance of MOS transistor MN11 is larger than the conductance of MOS transistor MN12, and the potentials of internal nodes 72a and 74a drop earlier than the potentials of internal nodes 72b and 74b. When the potential of the internal node 72a decreases, the conductance of the MOS transistor MN14 decreases, and the potential decrease rate of the internal node 72b is further reduced. On the other hand, the MOS transistor MN13 discharges the internal node 72a according to the potential of the internal node 72b. .

  The potentials of internal nodes 72a and 72b are reflected in the potentials of internal nodes 74a and 74b, and the conductance of MOS transistor MP14 increases as the potential of internal node 74a decreases, increasing the potential of internal node 74b. As the potential of 74b increases, the conductance of the MOS transistor MP13 decreases. Therefore, the positive feedback of MOS transistors MN13 and MN14 causes internal node 72a and 72b having the lower potential, that is, internal node 72a to be discharged to the ground voltage level, while internal nodes 74a and 74b Internal node 74b having the higher potential is driven to power supply voltage VDD level by the positive feedback operation of MOS transistors MP13 and MP14. Finally, internal nodes 74a and 74b are driven and latched to the ground voltage level and the power supply voltage level, respectively.

  The high level and low level of internal nodes 74a and 74b are amplified and inverted by buffer circuit 75, L level and H level signals are generated, latched by RS flip-flop 80, and output signals VOUTP and VOUTN are respectively H Driven and maintained at level and L level.

  When this latch operation period is completed, latch control signal VLT again attains L level, and internal nodes 74a and 74b are precharged to power supply voltage VDD level by MOS transistors MP13 and MP14. On the other hand, internal nodes 72a and 72b are in an indefinite state according to the ground voltage level or the states of voltage signals VOP and VON.

  Therefore, as shown in FIG. 7, the amplifier 50 and the latch 60 are used to form a comparator that compares the voltage levels of the input signals VIP and VIN, so that the amplifier 50 performs a comparative amplification operation having a high power supply noise resistance. A signal indicating the comparison result between the input signals VIP and VIN can be generated. Also in the latch 60, the latch-type sense amplifier 70 performs differential amplification, and can cancel the power supply noise, and the influence of the power supply noise is sufficiently suppressed. The current flows in the latch 60 only during the amplification latch operation period (period PR3) in which the latch control signal VLT is in the active state (H level), and the positive feedback MOS transistors MN13 and MN14, MP13 and Since the amplification / latch operation is performed at high speed by the MP 14, the period during which current flows from the power supply node to the ground node is short, and the current consumption is sufficiently suppressed.

[Embodiment 5]
FIG. 10 schematically shows a structure of a semiconductor integrated circuit according to the fifth embodiment of the present invention. 10, this semiconductor integrated circuit includes charge discharge amplifiers 50A and 50B connected in cascade in a plurality of stages (two stages in FIG. 10), and a latch 60 that latches an output signal of charge discharge amplifier 50B. .

  The semiconductor integrated circuit shown in FIG. 10 is a comparator that compares the voltage levels of the input signals VIP and VIN and generates a signal DOUT (VOUTP, VOUTN) indicating the comparison result. Charge-discharge amplifiers 50A and 50B have any of the amplifier configurations described in the first to third embodiments. Therefore, comparison amplification control signals VPC01 and VPC02 are individually applied to amplifiers 50A and 50B, respectively, and precharge control signal VPC1 is applied in common. Latch 60 has a configuration similar to that shown in FIG. 9, and performs a latch operation in accordance with latch control signal VLT.

  FIG. 11 is a diagram showing the operation timing of the comparator shown in FIG. As shown in FIG. 11, in period PR1 starting from time t30, precharge control signal VPC1 is activated (indicated by H level in FIG. 11), and amplifiers 50A and 50B commonly perform internal precharge operations. . After the precharge period PR1, the comparative amplification control signal VPC01 is activated (indicated by L level in FIG. 11) in the period PR2A starting from time t31, and the amplifier 50A performs the amplification operation of the input signals VIP and VIN. In parallel with the end of comparison amplification period PR2A of amplifier 50A, comparison amplification control signal VPC02 is activated (set to L level in FIG. 11) in period PR2B starting from time t32, and amplifier 50B is connected to amplifier 50A. Amplifies and latches the output signal.

  In parallel with the end of the comparison amplification period PR2B of the amplifier 50B, the latch control signal VLT is activated at time t33, and the latch 60 latches the output signal of the amplifier 50B to generate the comparison result signal DOUT.

  In the comparator shown in FIG. 10, the period from time t30 to time t34 is one cycle of the operation period in which the input signals VIP and VIN are compared.

  In FIG. 11, control signals VPC01, VPC02 and VLT indicate that activation and deactivation timing are performed at the same timing, respectively. However, control signals VPC01, VPC02 and VLT may be activated after completion of the previous circuit operation. These control signals VPC01, VPC02 and VPC1 may use any combination of control signals of the amplifiers shown in the first to third embodiments.

  As shown in FIGS. 10 and 11, by connecting a plurality of stages of charge discharge amplifiers according to any one of the first to third embodiments of the present invention, gain in amplification is improved and voltage comparison accuracy is improved. . Further, the same effects as those of the first to fourth embodiments can be obtained.

[Embodiment 6]
FIG. 12 schematically shows a structure of a semiconductor integrated circuit according to the sixth embodiment of the present invention. The semiconductor integrated circuit shown in FIG. 12 is a successive approximation ADC (analog / digital converter) using a capacitor array. In FIG. 12, the successive approximation ADC generates a comparator 90 that compares the comparison reference voltage VCOMM and the reference voltage VREF1, an operation that generates the comparison reference voltage according to the output signal DOUT of the comparator 90, and data that indicates the comparison result. The successive approximation register / logic 95, the switch array 100 for switching the connection path in accordance with the output data signal from the successive approximation register / logic 95, and adjusting the voltage level of the comparison reference voltage VCOMM by capacitive coupling in accordance with the connection path of the switch array 100 The capacitor array 110 is included.

  Comparator 90 has the configuration of the comparator (comparator) shown in FIG. 10, receives comparison reference voltage VCOMM and reference voltage VREF1 as input signals VIP and VIN, respectively, and uses a plurality of cascaded internal amplifiers. Are amplified by an internal latch to generate an output signal DOUT.

  The successive approximation register / logic 95 sets internal conversion result data bits and comparison target bits for the output nodes D00 and D0 to D11 in accordance with the output signal DOUT of the comparator 90. In the ADC shown in FIG. 12, the output data is 12 bits, and a configuration having output bits D0 to D11 and dummy output bits D00 is shown as an example. However, the ADC may be an ADC of other bits instead of the 12-bit ADC.

  Switch array 100 includes switches Sb0 and Sa0 to Sa11 provided for output nodes D00 and D0 to D11 of successive approximation register / logic 95, respectively. These switches Sb0, Sa0-Sa11 have three input terminals, and any one of the ground voltage VSS, the conversion target input voltage VIP and the reference voltage VRF2 is a control signal from the corresponding output node of the successive approximation register / logic 95. Select according to.

  The capacitive array 110 includes capacitive elements C00 and C0 to C11 provided corresponding to the switches Sb0 and Sa0 to Sa11, respectively, and a coupling capacitive element Cc connected between the comparison target voltage lines 112a and 112b. The comparison target voltage lines 112a and 112b are provided with switches S2 and S1, respectively. The comparison target voltage lines 112a and 112b are precharged to the reference voltage VREF0 during precharging.

  Capacitance elements C6-C11 are coupled to comparison target voltage line 112a, and capacitance elements C00 and C0-C5 are coupled to comparison target voltage line 112b. The comparison target voltage lines 112a and 112b are divided, and the coupling capacitor element Cc is arranged therebetween.

  In general, the capacitance values of the capacitive elements C11 to C0 are weighted according to the corresponding bit positions. The capacitive element Cn (n = 0-11) has a capacitance value of 2 ^ n · C0, but if it has a resolution of 10 bits or more, the capacitive array becomes huge. Therefore, the total capacity of the capacitive elements C0 to C11 is reduced using the capacitive element Cc. The capacitive elements can have capacitance values of Cn (n = 0-5) = C2n + 1 = 2 ^ n · C0. Here, the symbol “^” indicates a power. By setting Cc = 64/63 · C0, the capacitive array divided by the capacitive element Cc has the same function as the capacitive array in which the capacitive element Cn (n = 0-11) has a capacitance value of 2 ^ n · C0. Have Therefore, in the following description, Cn (n = 0-11) = 2 ^ n · C0 will be described for the sake of simplicity. The capacitive element C00 provided for the dummy output bit D00 is a dummy capacitance and has the same capacitance value as the capacitive element C0. A comparison reference voltage based on the binary search method can be generated by C00 using this dummy capacitor.

  FIG. 13 is a flowchart showing an analog / digital conversion operation for one conversion target input voltage VIP of the successive approximation ADC shown in FIG. Hereinafter, the A / D conversion operation of the successive approximation ADC shown in FIG. 12 will be described with reference to FIG. Here, the reference voltages VREF0, VREF1, and VREF2 are all at the same voltage level.

  When the conversion cycle for the analog input voltage VIP starts, the successive approximation register / logic 95 sets n to 11 in order to designate the most significant bit of the converted digital data (step ST1).

  Next, the successive approximation register / logic 95 sets the switches S1 and S2 to the ON state, and charges the comparison target voltage lines 112a and 112b to the reference voltage VREF0. At this time, the successive approximation register / logic 95 sets the states of the output data bits dd0 and d0 to d11 from the output nodes D00 and D0 to D11, and applies the analog input voltage VIP to the switches Sb0 and Sa0 to Sa11. Select (step ST2). As a result, charges corresponding to the voltage level of the analog input voltage VIP are accumulated in the capacitive elements C00 and C0 to C11. As described above, the capacitive elements C0 to C11 correspond to the bit positions, the capacitance values have a weight corresponding to the bit positions, and the dummy capacitive element C00 corresponds to 1LSB. The capacitance element C0 has the same capacitance value as the capacitance element C0. When the capacitance values of these capacitance elements C00 and C0 are C, the capacitance element Ci has a capacitance value C · 2 ^ i.

  Next, the successive approximation register / logic 95 sets the switches S1 and S2 to the non-conduction state (OFF state), and stops the charging of the comparison target voltage lines 112a and 112b from the reference voltage VREF0. Further, the switch Sb0 is maintained in a state where the corresponding bit dd0 is set to “0” and the ground voltage VSS is selected (step ST3). By this step ST1-ST3, the precharge of the comparison target voltage lines 112a-112b is completed. Since the switch Sb0 selects the ground voltage VSS, the voltage VCOM to the comparison target voltage lines 112a and 112b is lowered by the voltage level corresponding to LSB / 2 due to capacitive coupling of the dummy capacitive element C00. . This state is actually included in the first sequence of the comparison operation of the capacitive element C11.

  Next, in a DAC (digital / analog converter) composed of the switch array 100, the capacitor array 110, and the successive approximation register / logic, the switch San is set to a state for selecting the reference voltage VREF2 (the bit dn is set to “1”). The remaining switches Sa (n-1) -Sa0 are set to a state of selecting the ground voltage VSS by setting the bits d (n-1) -d0 to "0" (step ST4).

By setting the connection path of this switch, the voltage level of the comparison reference voltage lines 112a and 112b is lowered by the capacitive element coupled to the ground node, and the comparison reference voltage line 112a and the capacitance level connected to the reference voltage source VREF2 are reduced. The voltage level of 112b rises and charges are redistributed among these capacitive elements. Since n is 11 indicating the most significant bit, the capacitive element C11 is connected in series with the combined capacitance of the capacitive elements C00 and C0-C10 between the reference voltage source VREF2 and the ground node, and charge redistribution Is done. In this case, the capacitance value of the capacitive element C11 is (2 ^ 11) · C, which is equal to the sum of the capacitance values of the remaining capacitive elements C00 and C0-C10, and the voltage VCOMM of the comparison target voltage lines 112a and 112b is It is represented by the following formula:
VCOMM = VREF0−VIP + (VREF2 / 2).
The third term on the right side of the above equation indicates the voltage to be compared when the switches Sb0 and Sa0-Sa11 are all set to the ground voltage selection state by the first and second terms on the right side of the above equation. The comparison reference voltage VCOMM when Sa11 is set to select the reference voltage VREF2 is shown.

  Next, the comparator 90 compares the comparison target voltage VCOMM with the reference voltage VREF1, and generates a signal DOUT indicating the comparison result. The logic included in the successive approximation register / logic 95 is configured such that the comparison target voltage VCOMM is higher than the reference voltage VREF1 based on whether the output signal DOUT of the comparator 90 is “0” or “1”. It is determined whether it is high (step ST5). When the comparison target voltage VCOMM is higher than the reference voltage VREF1, the state of the switch San is maintained to select the reference voltage VREF2, that is, the corresponding output data bit dn is maintained at “0”. On the other hand, when the comparison reference voltage VCOMM is lower than the reference voltage VREF1, the switch San is set to a state in which the corresponding data bit dn is set to “1” and the ground voltage VSS is selected (step ST6). ).

  Next, n is replaced with (n−1) in order to shift the bit to be converted to the lower side by 1 bit (step ST7). Next, it is determined whether the bit position n is 0 or more (step ST8). When the value n indicating the bit position is 0 or more, since the conversion operation of the least significant bit has not been performed yet, the process returns to step ST4, and the conversion and comparison operations of the comparison reference voltage VCOMM are performed.

  On the other hand, in step ST8, when the value n indicating the bit position is a non-positive value, since the conversion of the least significant bit is completed, the state of the switches Sa0-San (= Sa11) is output (step ST9). ). That is, the latch data d0 to d11 of the successive approximation register included in the successive approximation register / logic 95 is output as a digital conversion value of the analog input voltage VIP.

  FIG. 14 is a diagram illustrating an example of a change sequence of the comparison target voltage VCOMM during the conversion of the successive approximation ADC illustrated in FIG.

  Also in FIG. 14, the reference voltages VREF0, VREF1, and VREF2 are all set to the same voltage level.

  First, at the time of initialization, the comparison reference voltage VCOMM is precharged to the reference voltage VREF0 by the switches S1 and S2 shown in FIG. Next, the switches Sb0 and Sa0 to Sa11 shown in FIG. 12 are all set from the state in which the analog input voltage VIP is selected to the state in which the ground voltage VSS is selected. Accordingly, comparison reference voltage VCOMM decreases from precharge voltage VREF0 by the voltage level of analog input voltage VIP.

  Here, in the initialization sequence as shown in FIG. 13, only the switch Sb0 is set to a state for selecting the ground voltage VSS. In this case, the comparison target voltage VCOMM is shown by a one-dot chain line in FIG. Further, it is only slightly reduced from the precharge voltage VREF0. This state is included in the comparison sequence of the capacitive element C12 in actual operation, and is not actually output.

  Next, at the start of the comparison operation, all the switches Sa0-Sa (n-1) are set to a state for selecting the ground voltage, and the switch San is set to a state for selecting the reference voltage VREF2 (= VREF0). The comparison target voltage VCOMM at this time is VREF0−VIP + VREF0 / 2. In the first comparison operation, the comparison target voltage VCOMM and the reference voltage VREF1 (= VREF0) are compared in magnitude. During this comparison operation, VCOMM-VREF0 = VREF0-VIP, the reference voltage is compared with the analog input voltage, and it is identified whether the most significant bit after conversion is "1".

  In FIG. 14, since the voltage level of the comparison target voltage VCOMM is lower than the reference voltage VREF1 (= VREF0), the next bit d10 is set to “1” while the most significant bit d11 is maintained at “1”. The remaining bits d9-d0 and dd0 are all maintained at “0”.

  Next, in the second comparison operation, both the upper bits d11 and d10 are “1”, and the remaining bits d9 to d0 are “0”. In this state, the capacitive elements C11 and C10 are connected in parallel between the reference voltage source VREF0 (= VREF2; the voltage corresponding to the power supply node is indicated by the same reference symbol) and the comparison target voltage line. The remaining capacitive elements C9-C0 and C00 are connected in parallel between the line and the ground node. By this capacitive coupling and charge redistribution of the capacitive element C10, the comparison reference voltage VCOMM rises by the voltage VREF0 / 4, and the comparison operation with the reference voltage VREF1 is performed.

  In the comparison sequence shown in FIG. 14, in the second comparison operation, since the comparison target voltage VCOMM is higher than the reference voltage VREF1, the bit d10 is set to “0”, and then the bit d9 is set to “1”. The comparison operation is performed by setting to “”. In the third comparison operation (third bit conversion operation), the capacitive element C10 for the bit d10 is coupled to the ground node, and the next capacitive element C9 is connected between the comparison target voltage line and the comparison target voltage line. Therefore, the comparison target voltage VCOMM is decreased to the voltage VREF0 / 4 and increased to the voltage VREF0 / 8. Therefore, the comparison target voltage VCOMM is set to a voltage level that is decreased by the voltage VREF0 / 8 from the comparison target voltage VCOMM in the second comparison operation. The In this state, the third comparison operation is performed, the bit d9 is set to "0" according to the comparison result, the next bit d8 is set to "1", and the fourth comparison operation is performed. At this time, a voltage change of the voltage −VREF0 / 8 + VREF0 / 16 occurs in the comparison target voltage VCOMM, and the voltage level of the comparison reference voltage VCOMM is decreased by VREF0 / 16 than in the third comparison operation.

  Next, the next bit d7 is set to "1" while the bit d8 is maintained at "1" according to the fourth comparison result, and the fifth comparison operation is performed.

  Therefore, during this comparison operation, the comparison target voltage VCOMM has a voltage level represented by the following equation.

  The comparison operation shown in FIG. 14 is repeatedly performed for the necessary resolution (for this example, 12 bits).

  Finally, when the conversion operation with the necessary resolution is completed, that is, when the least significant bit conversion operation is completed, the state of each switch corresponds to the value obtained by digitally converting the analog input voltage VIN, and the successive approximation register / Data bits d0 to d11 stored in a register included in the logic 95 are output as digitally converted values.

[Example of change]
FIG. 15 schematically shows a modification of the conversion sequence of the successive approximation ADC according to the sixth embodiment of the present invention. FIG. 15 shows how the capacitive element is connected to the voltage line to be compared during the initialization sequence in the A / D conversion sequence. When reference voltage VREF0 is precharged for voltage line 112 to be compared, capacitive element Ca receives analog input voltage VIP, while capacitive element Cb is coupled to the ground node. Here, the capacitors Ca and Cb indicate the combined capacitance of the capacitor elements of the capacitor array shown in FIG. After the comparison target voltage line 112 is precharged, the switch corresponding to the capacitive element Ca is set to a state in which the ground voltage VSS (= 0 V) is selected from the analog input voltage VIP by the switching array (100). In this case, the voltage level of the comparison target voltage VCOMM of the comparison target voltage line 112 decreases by Ca · VIP / (Ca + Cb) due to charge redistribution of the capacitive elements Ca and Cb. The comparison reference voltage VCOMM at this time is expressed by the following equation:
VREF0-Ca · VIP / (Ca + Cb)
In order to maintain the comparison reference voltage VCOMM at a positive voltage level, the maximum voltage VIP_MAX of the analog input voltage VIP is expressed by the following equation.

VIP_MAX = VREF0 · (Ca + Cb) / Ca
Therefore, the switch control information at the time of sampling of the capacitive elements Ca and Cb is represented by a0-a11. When the bit ai is “1”, the corresponding switch Sai selects the analog input voltage VIP, and the bit ai is “0”. When the corresponding switch Sai selects the ground voltage VSS, the maximum voltage VIP_MAX of the analog input voltage VIP is expressed by the following equation:

  Therefore, in this state, the voltage range of the analog input voltage that can be sampled can be increased.

  In the A / D conversion sequence described above, the reference voltages VREF0, VREF1, and VREF2 are all set to the same voltage level. However, reference voltages VREF0 to VREF2 that satisfy the following relationship may be used as the reference voltage.

VREF0 = VREF1 = VDD / 2,
VREF2 = VDD
As described above, according to the sixth embodiment of the present invention, a comparator is configured using the amplifiers shown in the first to third embodiments of the present invention, and the analog input voltage is converted into a digital signal using this comparator. ing. Therefore, it is possible to realize a successive approximation ADC capable of accurately performing digital conversion with excellent noise resistance against power supply noise (power supply voltage superimposed on VDDS-VSS).

  The amplifier according to the present invention can realize a semiconductor integrated circuit having an amplification function with excellent resistance to power supply noise simply by being applied to an amplifier in a semiconductor integrated circuit. As a result, a semiconductor integrated circuit that operates stably can be realized.

  Also, by applying the amplifier according to the present invention to the comparator of the successive approximation ADC, it is possible to realize a successive approximation ADC having excellent power supply noise resistance. By applying this successive approximation ADC to an analog / digital interface section of an integrated circuit in which an analog circuit and a digital circuit are mixedly mounted, an analog / digital mixed integrated circuit having excellent power supply noise resistance can be realized.

  The amplifier and successive approximation ADC used in the present invention may be used as individual components.

  In the successive approximation ADC shown in the sixth embodiment of the present invention, a charge redistribution type ADC using a capacitor array is used. However, since the comparator (80) is used even in the successive approximation type ADC using another resistive element array, the amplifier and / or the comparator according to the first to fifth embodiments of the present invention is applied to this comparator. May be.

  1a, 1b Input node, 4 constant current stage, MP1, MP2 P channel MOS transistor (differential transistor pair), MPC1-MPC3 P channel MOS transistor (current control transistor), MN1, MN2 N channel MOS transistor (precharge transistor) 10 constant current stage, AP3, AP4 P-channel MOS transistor (precharge transistor), CL3, CL4 capacitive element, NM3, NM4 N-channel MOS transistor (differential transistor pair), NMC1-NMC3 N-channel MOS transistor (heat transfer control) Transistor), 20 amplifier body, 25 bias circuit, APC3, APC4 P-channel MOS transistor, NMC4 N-channel MOS transistor, NPC4 P-channel MOS transistor , 50 amplifier, 60 a latch, 50A, 50B charge discharging amplifier, 70 a latch type amplifier, 75 a buffer circuit, 80 RS flip-flop, 90 a comparator, 95 successive approximation register / logic 100 switch array, 110 capacitor array.

Claims (5)

An amplifying circuit that receives the first and second input voltages, complementarily amplifies and outputs the at least one stage;
The amplifier circuit is
A pair of differential transistors that receive the first and second input voltages at their respective control electrodes;
A current is coupled between the pair of differential transistors and a first power supply, and conducts in response to a first control signal to provide a constant current between the pair of differential transistors and the first power supply. A constant current stage for
A pair of capacitive elements electrically connected to each of the pair of differential transistors, each charged or discharged according to an amount of current flowing through a corresponding transistor of the pair of differential transistors;
An electrode coupled between the pair of capacitive elements and a second power source and electrically coupled to the differential transistor of the pair of capacitive elements in response to a second control signal. A pair of precharge transistors electrically coupled to the two power sources ;
The constant current stage is:
Comprising first and second transistors connected in series between the pair of differential transistors and the first power supply;
The first transistor is coupled to the pair of differential transistors and selectively conducts in response to the first control signal, and the second transistor is coupled to the first power source. flowing the constant current, semi-conductor integrated circuit. An amplifying circuit that receives the first and second input voltages, complementarily amplifies and outputs the at least one stage;
The amplifier circuit is
A pair of differential transistors that receive the first and second input voltages at their respective control electrodes;
A current is coupled between the pair of differential transistors and a first power supply, and conducts in response to a first control signal to provide a constant current between the pair of differential transistors and the first power supply. A constant current stage for
A pair of capacitive elements electrically connected to each of the pair of differential transistors, each charged or discharged according to an amount of current flowing through a corresponding transistor of the pair of differential transistors;
An electrode coupled between the pair of capacitive elements and a second power source and electrically coupled to the differential transistor of the pair of capacitive elements in response to a second control signal. A pair of precharge transistors electrically coupled to the two power sources ;
The constant current stage is:
A first transistor coupled between the first power supply and the pair of differential transistors, wherein the first transistor is nonconductive when the voltage level of its control electrode is the voltage level of the first power supply;
A first control transistor that sets a control electrode of the first transistor to one of a voltage level of the first power supply and a constant current bias voltage level in accordance with the first control signal;
The control electrode of the first transistor and the reference current source are selectively coupled according to the first control signal, and the conductive state is established when the voltage level of the control electrode of the first transistor is the voltage level of the first power source. A second control transistor having a polarity opposite to that of the first control transistor,
The control electrode of the first transistor is coupled to the control electrode of the first transistor, and the control electrode of the first transistor is coupled to the reference current source when the second control transistor is turned on so that the voltage of the control electrode of the first transistor is the constant current bias voltage. set level, and a third control transistor having the same polarity as the first control transistor, the semi-conductor integrated circuit. An electrode coupled to the precharge transistor of the pair of capacitive elements is coupled to an output node of the amplifier circuit;
The semiconductor integrated circuit further includes:
Further comprising a latch circuit for latching the voltage at the output node of the amplifier circuit, the semiconductor integrated circuit according to claim 1 or 2 wherein. The amplifier circuits are arranged in a plurality of stages, and the amplifier circuits in the plurality of stages are connected in cascade with each other,
The semiconductor integrated circuit further includes:
3. The semiconductor integrated circuit according to claim 1, further comprising a latch circuit that latches a voltage signal from an output node of the final stage amplifier circuit of the plurality of stages of amplifier circuits. A successive approximation register circuit that outputs at least one bit of data;
A digital / analog converter that generates a comparison target voltage based on the analog input voltage and the output data of the successive approximation register circuit;
The amplifier circuit is
The comparison target voltage and the reference voltage are respectively received as the first and second input voltages at the control electrodes of the pair of differential transistors,
5. The semiconductor integrated circuit according to claim 4 , wherein the successive approximation register circuit generates the data based on a signal supplied from the latch circuit, and generates data indicating a digital conversion result of the analog input voltage.

Images