JP7239968B2 - Voltage/time converter and analog/digital converter - Google Patents

Description

The present invention relates to voltage/time converters and analog/digital converters.

Along with the miniaturization of CMOS (Complementary Metal Oxide Semiconductor), the performance of digital circuits has been remarkably improved, and smaller areas, higher speeds, and lower power consumption are progressing. In analog circuits as well, LSIs (Large-Scale Integration) capable of operating in the millimeter wave and terahertz regions have appeared due to improvements in cutoff frequencies due to miniaturization. However, on the other hand, the negative aspects of miniaturization, such as a decrease in intrinsic gain, an increase in element variation, and a deterioration in the SN ratio due to a decrease in power supply voltage, are becoming apparent, and various techniques are being investigated to solve these problems. .

Among them, time-domain analog technology, which expresses and processes signals in the time domain, has recently attracted attention. If signals are expressed in the time domain, it becomes possible to express signals that are not limited by the power supply voltage, and it is possible to construct circuits centered on digital circuits, so that the benefits of miniaturization can be easily enjoyed.

Against this background, research on analog-to-digital converters (ADCs) using time-domain analog technology is also actively being conducted. For example, Non-Patent Document 1 reports an analog-to-digital converter that combines a voltage-to-time converter (VTC) and a time-to-digital converter (TDC). there is In this analog/digital converter, an input differential voltage signal is converted into a time output by the voltage/time converter, and then the time output is converted into a digital signal by the time/digital converter.

As the time-to-digital converter, a parallel type suitable for high speed operation is adopted. It is realized with a low energy of -step. An attempt to combine a conventional voltage-domain analog-to-digital converter and a time-domain analog-to-digital converter has also been reported (see Non-Patent Document 2). In this combination, after coarse conversion is performed by a successive approximation register (SAR) analog-to-digital converter, the residual signal between the input differential voltage signal and the coarse conversion result is the analog/digital signal in the time domain. It is converted into a digital signal by a digital converter. As a result, although the operating speed is as low as 250 kHz, it is 2.02 fJ/conv. An analog-to-digital converter capable of extremely low-energy operation called -step has been realized.

Yongsheng Xu, et al., “5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no .12, pp.3513-3525, Dec.2016. Yan-Jiun Chen, et al., “A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90nm CMOS,” IEEE Journal of Solid-State Circuits, vol.51, no. 2, pp.357-364, Feb. 2016.

The analog-to-digital converter of Non-Patent Document 1 uses a voltage-time converter to convert the input differential voltage signal into a time output, and then uses the time-to-digital converter to convert the time output to a digital signal. Convert. However, due to the limited linearity of this voltage-time converter, the conversion accuracy remains at 5 bits. Also, even if the linearity problem of the voltage/time converter could be solved, since the time/digital converter is of parallel type, increasing the conversion accuracy would exponentially increase the circuit scale and conversion time. As a result, we face the problems of increased power consumption and reduced operating speed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage/time converter capable of obtaining good linearity. Another object of the present invention is to provide an analog-to-digital converter capable of suppressing an increase in power consumption and a decrease in operating speed even if conversion accuracy is increased.

A voltage/time converter according to a first aspect of the present invention comprises:
a conversion circuit comprising a first MOS differential circuit for inputting a differential voltage signal as a gate voltage and converting it into a pair of pulse voltage signals indicating a time output corresponding to the magnitude of the differential voltage signal;
The first current corresponding to the pair of pulse voltage signals is based on the differential voltage signal so that the conversion from the differential voltage signal to the pair of pulse voltage signals in the conversion circuit maintains linearity. a correction circuit that corrects a pair of currents output from the MOS differential circuits of
Prepare.

In this case, the correction circuit
A distortion correction circuit comprising a second MOS differential circuit that removes high-order components of the differential voltage signal contained in the pair of pulse voltage signals by adding correction currents to the pair of currents, respectively.
You can do it.

Further, the polarities of the input differential voltage signals are opposite between the first MOS differential circuit and the second MOS differential circuit,
Relation between a gain coefficient β of a CMOS inputting the differential voltage signal in the first MOS differential circuit and a gain coefficient _βc of the CMOS inputting the differential voltage signal in the second MOS differential circuit but,
β _c =(3−2√2)β
satisfy the
You can do it.

Further, the two gate voltages input to the second MOS differential circuit are set to constant voltages,
a CMOS gain coefficient β for inputting the differential voltage signal in the first MOS differential circuit;
The relationship between the gain coefficient _βc of the CMOS to which the two gate voltages are input in the second MOS differential circuit is
_βc = β
The filling,
a common level V _com of the differential voltage signal input to the first MOS differential circuit;
The relationship between the two gate voltages input to the second MOS differential circuit and the common level _Vc is
_Vcom = _Vc
satisfy the
You can do it.

providing an offset between the positive side voltage and the negative side voltage of the two gate voltages input to the second MOS differential circuit to cancel offset components contained in the pair of pulse voltage signals;
You can do it.

The conversion circuit is
inserting a pair of resistors into the first MOS differential circuit to output the pair of currents that increase in proportion to the differential voltage signal;
The correction circuit is
By adding a correction current to each of the pair of currents, the transfer function between the differential voltage signal and the current corresponding to the pair of pulse voltage signals is linearly approximated to an ideal transfer function.
You can do it.

The correction circuit is
at least one third MOS differential circuit that receives the differential voltage signal as a gate voltage, has a pair of resistors inserted therein, and outputs the correction current that increases in proportion to the differential voltage signal;
You can do it.

The correction circuit is
A fourth MOS differential circuit that inputs a constant voltage as a gate voltage and outputs a constant current as the correction current,
You can do it.

A pair of CMOS source terminals for inputting a gate voltage are separated, and another CMOS controlled by a clock signal is connected to each source terminal.
You can do it.

The analog-to-digital converter according to the second aspect of the present invention comprises
an upper AD converter that converts an input differential voltage signal into an upper m (m is a natural number smaller than n) bit digital signal of an n (n is a natural number) bit digital signal;
a residual generating circuit for generating a residual signal of the differential voltage signal based on the differential voltage signal and the high-order digital signal output from the high-order AD converter;
a low-order AD converter that converts the residual signal into a low-order n−m-bit low-order digital signal of the n-bit digital signal;
a synthesizer that synthesizes the high-order digital signal and the low-order digital signal and outputs an n-bit digital signal;
with
At least one of the high-order AD converter and the low-order AD converter includes the voltage/time converter according to the first aspect of the present invention.

According to the present invention, when a differential voltage signal is converted into a time output, the pair of currents corresponding to the pair of pulse voltage signals are corrected in order to maintain the linearity, so good linearity can be obtained. can. Moreover, according to the present invention, since the number of bits of a digital signal to be converted at one time can be reduced, an increase in power consumption and a decrease in operating speed can be suppressed even if the conversion accuracy is increased.

1 is a circuit diagram of a voltage/time converter according to Embodiment 1 of the present invention; FIG. 2 is a timing chart showing the operation of the voltage/time converter of FIG. 1; 2 is an equivalent circuit diagram of the voltage-time converter of FIG. 1; FIG. 4 is a circuit diagram showing the configuration of a distortion correction circuit; FIG. It is a circuit diagram of a voltage-time converter according to Embodiment 2 of the present invention. FIG. 4 is a circuit diagram of a voltage/time converter according to Embodiment 3 of the present invention; 1 is a circuit diagram of a conventional voltage/time converter; FIG. FIG. 3 is a diagram showing a transfer function between differential voltage and current in a conventional voltage/time converter; It is a figure which shows a polygonal line-like approximate transfer function. It is a circuit diagram of a voltage-time converter according to Embodiment 4 of the present invention. FIG. 10 is a diagram showing a transfer function between differential voltage and current in the voltage-time converter according to Embodiment 4 of the present invention; FIG. 10 is a circuit diagram of a voltage/time converter according to Embodiment 5 of the present invention; FIG. 10 is a diagram showing a transfer function between differential voltage and current in the voltage-time converter according to Embodiment 5 of the present invention; FIG. 9 is a circuit diagram of an analog-to-digital converter according to Embodiment 6 of the present invention; It is a circuit diagram which shows an example of the circuit configuration of a time-digital converter. 4 is a circuit diagram showing another example of the circuit configuration of the time/digital converter; FIG. 2 is a circuit diagram showing an example of a circuit configuration of a residual generating circuit; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1.
First, Embodiment 1 of the present invention will be described.

A voltage/time converter 1A (see FIG. 1) according to the present embodiment linearly converts a differential voltage signal into a time output corresponding to its magnitude. In the present embodiment, as shown in FIG. 2, the positive voltage signal of the input differential voltage signal is V _inp , the negative voltage signal is V _inn , and the differential voltage signal is (V _inp , V _inn ). Represented by The differential voltage _becomes Vin. A pair of pulse voltage signals output from the voltage/time converter 1A, ie, timing signals, are assumed to be (START signal, STOP signal). The time difference between the rises of the START signal and the STOP signal is assumed to be a time output to- _out .

The time output t _out indicates the time between when the START signal transitions from low level to high level and when the STOP signal transitions from low level to high level. In the following description, the lower level of the binary signal, that is, the low level, is represented as "L", and the upper level, that is, the high level is represented as "H".

As shown in FIG. 1, this voltage/time converter 1A includes a conversion circuit 20 and a distortion correction circuit 30 as a correction circuit. The conversion circuit 20 inputs the differential voltage signals (V _inp , V _{inn )} , converts the differential voltage signals (V _inp , V _inn ) to a timing signal (START signal, STOP signal).

The first MOS differential circuit includes MOS transistors (CMOS) MP1 and MN1 for outputting a START signal, MOS transistors MP2 and MN2 for outputting a STOP signal, and a MOS transistor MN3 common to both signals. It includes power supply voltage terminals 2P and 2N, nodes DP and DN, and capacitors 3P and 3N. In addition, the conversion circuit 20 includes inverters 4P and 4N.

The first MOS differential circuit is mainly composed of a MOS transistor MN1 for inputting a positive voltage signal _Vinp and a MOS transistor MN2 for inputting a negative voltage signal _Vinn . Let μ be the electron mobility of the MOS transistors MN1 and MN2, Cox be the gate capacitance per unit area, w be the gate width of the MOS, and L be the gate length. The coefficient β is represented by the following formula.
β=μ・Cox・(w/L) (1)

The MOS transistor MN1 is inserted between the power supply voltage terminal 2P that supplies the power supply voltage VDD and the ground. The MOS transistor MN1 receives the positive voltage signal _Vinp as a gate voltage (control voltage). A MOS transistor (switch) MN3 for inputting the clock signal CK as a gate voltage is inserted between the MOS transistor MN1 and the ground.

A MOS transistor (switch) MP1 for inputting an inverted signal of the clock signal CK as a gate voltage is inserted between the MOS transistor MN1 and the power supply voltage terminal 2P. A node DP is formed between the MOS transistor MP1 and the MOS transistor MN1. Node DP is grounded via capacitor 3P. Also, the node DP is connected to the inverter 4P. The output of the inverter 4P becomes the START signal.

On the other hand, the MOS transistor MN2 is inserted between the power supply voltage terminal 2N that supplies the power supply voltage VDD and the ground. The MOS transistor MN2 receives the negative voltage signal V _inn as a gate voltage (control voltage). A MOS transistor (switch) MN3 for inputting the clock signal CK as a gate voltage is inserted between the MOS transistor MN2 and the ground.

A MOS transistor MP2 (switch) is inserted between the MOS transistor MN2 and the power supply voltage terminal 2N to input an inverted signal of the clock signal CK as a gate voltage. A node DN is formed between the MOS transistor MP2 and the MOS transistor MN2. Node DN is grounded via capacitor 3N. Also, the node DN is connected to the inverter 4N. The output of the inverter 4N becomes the STOP signal.

This voltage/time converter 1A operates according to the clock signal CK. The clock signal CK is a signal that repeats "L" and "H" at a constant cycle. A period during which the clock signal CK is "L" is defined as a precharge period, and a period during which the clock signal CK is "H" is defined as a conversion period.

As shown in FIG. 2, since the clock signal CK is "L" during the precharge period, the MOS transistor MN3 is turned off and the MOS transistors MP1 and MP2 are turned on. Therefore, the capacitors 3P and 3N are charged, and the voltages of the nodes DP and DN become the power supply voltage VDD.

After that, when the precharge period shifts to the conversion period, the clock signal CK switches to "H", so that the MOS transistor MN3 is turned on and the MOS transistors MP1 and MP2 are turned off. Therefore, currents (I _p , I _n ) depending on the differential voltage signals (V _inp , V _inn ) flow through the MOS transistors MN1, MN2 to discharge the nodes DP, DN.

When the potentials of the nodes DP and DN fall below the threshold voltage Vtinv of the inverters 4P and 4N, the START signal and STOP signal rise at that time. The time difference between the rises of the START signal and the STOP signal is the time output t- _out . The discharge time of the nodes DP and DN varies depending on the differential voltage signals (V _inp , V _inn ), and is defined by the START signal and STOP signal in the range where the differential voltage signals (V _inp , V _inn ) are small. Since the time output t _out is proportional to the differential voltage _Vin , this circuit functions as a voltage-time conversion circuit.

As shown in FIG. 3, the voltage/time converter 1A comprising the MOS transistors MN1 and MN2 is modeled by a constant current (I _p , I _n ) current source circuit that discharges the charge stored in the capacitor C. . Here, as shown in FIG. 2, the common level of the differential voltage signals (V _inp , V _inn ) is V _com , and the constant current (signal current) (I _p , _In ) is given by the following equation (2): approximate what can be expressed.

ここで、Ｖ_THは、ＭＯＳトランジスタＭＮ１，ＭＮ２のしきい値電圧である。ノードＤＰ，ＤＮがインバータ４Ｐ，４Ｎのしきい値Ｖｔｉｎｖを下回るまでの時間ｔ_ｐ，ｔ_ｎは、以下の式（３）で表せる。

Here, V _TH is the threshold voltage of the MOS transistors MN1 and MN2. The times t _p and t _n until the nodes DP and DN fall below the threshold Vtinv of the inverters 4P and 4N can be expressed by the following equation (3).

ただし、ここで、Ｖｔｉｎｖ＝ＶＤＤ／２とした。式（２）、式（３）から時間出力ｔ_ｏｕｔを求めると、以下の式のようになる。

However, here, Vtinv=VDD/2. When the time output t _out is obtained from the equations (2) and (3), the following equation is obtained.

ここで、Ｇは電圧・時間変換器の利得である。この式（４）からわかるように、変換回路２０は、（Ｖ_ｃｏｍ－Ｖ_ＴＨ）^３に反比例する３次成分の歪（３次歪）を発生する。

where G is the gain of the voltage-to-time converter. As can be seen from this equation (4), the conversion circuit 20 generates third-order component distortion (third-order distortion) that is inversely proportional to (V _com -V _TH ) ³ .

The distortion correction circuit 30 as a correction circuit adds correction currents (I _pc , I _nc ) to the signal currents (I _p , I _n ) to cancel out the third-order distortion described above and improve the linearity of the time output t _out . Improve. The distortion correction circuit 30 converts the timing signals (START signal, STOP signal) so that the linear conversion from the differential voltage signals (V _inp , V _inn ) to the timing signals (START signal, STOP signal) in the conversion circuit 20 maintains linearity. A pair of currents (I _P , I _N ) output from the first MOS differential circuit as currents corresponding to the signal) are corrected.

As shown in FIG. 4, the distortion correction circuit 30 adds the correction currents to the pair of currents (I _P , I _N ), respectively, so that the differential voltage signal (V _inp ) included in the timing signals (START signal, STOP signal) , V _inn ) is provided. The second MOS differential circuit comprises MOS transistors MN1c, MN2c and MN4. The MOS transistor MN1c is inserted between the node DP and the MOS transistor MN4, and receives the negative voltage signal V _inn of the differential voltage signals (V _inp , V _inn ) as a gate voltage. The MOS transistor MN2c is inserted between the node DN and the MOS transistor MN4, and receives the positive voltage signal V _inp of the differential voltage signals (V _inp , V _inn ) as a gate voltage. The MOS transistor MN4 is inserted between the MOS transistors MN1c, MN2c and the ground. Thus, in this embodiment, the polarities of the input differential voltage signals (V _inp , V _inn ) are opposite between the first MOS differential circuit and the second MOS differential circuit.

Correction currents (I _pc , I _nc ) are represented by the following equation (5). In the distortion correction circuit 30, the connection of the input signal is interchanged with the conversion circuit ₂₀ as described above (the polarity is reversed). The sign is reversed.

この回路の時間出力ｔ_ｏｕｔを求めると、以下の式（６）のようになる。β_ｃは、ＭＯＳトランジスタＭＮ１ｃ，ＭＮ２ｃの利得係数である。

The time output t _out of this circuit is obtained by the following equation (6). _βc is the gain coefficient of the MOS transistors MN1c and MN2c.

ここで、利得Ｇを以下の式（７）のように定義する。

Here, gain G is defined as in the following equation (7).

時間出力ｔ_ｏｕｔは、以下の式（８）のようになる。

The time output t _out is given by Equation (8) below.

上記式（８）では、第２項が、３次歪に対応する。この式（８）からわかるように、第２項において、（Ｖ_ｃｏｍ－Ｖ_ＴＨ）^２に反比例する３次歪みが発生する。

In the above equation (8), the second term corresponds to third-order distortion. As can be seen from this equation (8), third-order distortion that is inversely proportional to (V _com -V _TH ) ² occurs in the second term.

Here, the gain coefficient β of the MOS transistors MN1 and MN2 for inputting the differential voltage signals (V _inp , V _inn ) in the first MOS differential circuit and the differential voltage signal (V _inp , V _inn ) and the gain coefficient β _c of the MOS transistors MN1c and MN2c to which MOS transistors MN1c and MN2c are input satisfies β _c =(3−2√2)β, the second term of equation (8) becomes 0. Third order distortion can be canceled. The time output t _out in this case is as follows.

３次歪がキャンセルされることで、従来の電圧・時間変換器と比較した場合、線形性を大きく改善することができる。

By canceling the third-order distortion, the linearity can be greatly improved when compared with the conventional voltage-time converter.

Embodiment 2.
Next, Embodiment 2 of the present invention will be described.

A voltage/time converter 1B according to the present embodiment is the same as the voltage/time converter 1A according to the first embodiment in that it includes a conversion circuit 20 and a distortion correction circuit 30. FIG. In the voltage-time converter 1B according to the present embodiment, in the distortion correction circuit 30, the gate voltage (control voltage) input to the MOS transistors MN1c and MN2c forming the second MOS differential circuit is Different from form 1.

As shown in FIG. 5, in this embodiment, the gate voltages input to the MOS transistors MN1c and MN2c are constant voltages (V _pc , V _nc ). Correction currents (I _pc , I _nc ) are generated by a second MOS differential circuit to which control voltages V _pc , V _nc are applied. In this case, the correction currents I _pc and I _nc can be expressed by the following equations.

ここから、時間出力ｔ_ｏｕｔを求めると、以下の式となる。ただし、Ｖ_ｐｃ＝Ｖ_ｎｃ＝Ｖ_ｃとしている。

From this, the time output t _out is obtained by the following equation. However, V _pc =V _nc =V _c .

ここで、利得Ｇを以下のように定義すると、

Here, if the gain G is defined as follows,

時間出力ｔ_ｏｕｔは、以下のように表せる。

The time output t _out can be expressed as follows.

ここで、第１のＭＯＳ差動回路において差動電圧信号（Ｖ_ｉｎｐ，Ｖ_ｉｎｎ）を入力するＭＯＳトランジスタＭＮ１，ＭＮ２の利得係数βと、第２のＭＯＳ差動回路において２つのゲート電圧（Ｖ_ｐｃ，Ｖ_ｎｃ）を入力するＭＯＳトランジスタＭＮ１ｃ，ＭＮ２ｃの利得係数β_ｃとの関係が、β_ｃ＝βを満たすものとする。さらに、第１のＭＯＳ差動回路に入力される差動電圧信号（Ｖ_ｉｎｐ，Ｖ_ｉｎｎ）のコモンレベルＶ_ｃｏｍと、第２のＭＯＳ差動回路に入力される２つのゲート電圧のコモンレベルＶ_ｃとの関係が、Ｖ_ｃｏｍ＝Ｖ_ｃを満たすものとする。この場合、第２項は０となり、３次歪みをキャンセルすることができる。この場合、時間出力ｔ_ｏｕｔは、以下の式（１４）のようになる。

Here, the gain coefficient β of the MOS transistors MN1 and MN2 for inputting the differential voltage signals (V _inp , V _inn ) in the first MOS differential circuit and the two gate voltages (V _pc , V _nc ) and the gain coefficient β _c of the MOS transistors MN1c and MN2c to which pc , V nc are input satisfies β _c =β. Furthermore, the common level V _com of the differential voltage signals (V _inp , V _inn ) input to the first MOS differential circuit and the common level V com of the two gate voltages input to the second MOS differential circuit _c satisfies V _com =V _c . In this case, the second term becomes 0, and the third-order distortion can be canceled. In this case, the time output t _out is given by Equation (14) below.

上記式（１４）からわかるように、上記実施の形態１よりも、５次歪の大きさを１／４に低減することができる。

As can be seen from the above equation (14), the fifth-order distortion can be reduced to 1/4 of that in the first embodiment.

Also, it can be seen from equation (12) that the gain G can be changed by changing _Vc . Therefore, even if the gain changes due to manufacturing variations or temperature fluctuations, the gain can be kept constant by appropriately adjusting _Vc . In the above analysis, the calculation was performed with V _pc =V _nc =V _c , but if V _pc and V _nc are adjusted independently (that is, if V _pc ≠V _nc ), the voltage-time converter The 1B offset component can also be canceled. Thus, the offset component included in the timing signals (START signal, STOP signal) is canceled between the positive voltage _Vpc and the negative voltage _Vnc of the differential voltage signal to the second MOS differential circuit. An offset may be given.

Embodiment 3.
Next, Embodiment 3 of the present invention will be described.

A voltage/time converter 1C according to the present embodiment differs from the voltage/time converters 1A and 1B according to the first and second embodiments in the configuration of the differential circuits of the conversion circuit 20 and the distortion correction circuit 30 .

As shown in FIG. 6, in the voltage/time converter 1C according to the present embodiment, the source terminals of the MOS transistors MN1 and MN2 as a pair of CMOS are separated and controlled by the clock signal CK to each source terminal. Another MOS transistors (CMOS switches) MN3A and MN3B are connected. Similarly, in the distortion correction circuit 30, the source terminals of the MOS transistors MN1c and MN2c are separated, and separate MOS transistors (switches) MN4A and MN4B controlled by the clock signal CK are connected to the respective source terminals. By doing so, interference through the source terminals of the MOS transistors MN1, MN2 and MOS transistors MN1c, MN2c can be avoided, and the linearity can be further improved.

Although not shown here, the circuit configuration according to this embodiment can be similarly applied to the configuration of the voltage/time converter 1B of the second embodiment. The linearity of the time converter 1B can be further improved. In other embodiments, the source terminals of a pair of CMOS to which the gate voltage is input may be separated, and another CMOS controlled by the clock signal CK may be connected to each source terminal. .

Embodiment 4.
Next, Embodiment 4 of the present invention will be described.

In order to understand the configuration and operation of the voltage/time converter 1D (see FIG. 10) according to this embodiment, first, characteristics of an ideal voltage/time converter will be described. A voltage/time converter 1A' shown in FIG. 7 is a converter having a conventional circuit configuration. As shown in FIG. 7, the voltage/time converter 1A' includes capacitors 3P and 3N having a capacitance C, MOS transistors (switches) MP1 and MP2 for precharging the capacitors 3P and 3N, and input signals (V _inp , V _inn ) into current signals (I _p , I _n ) in synchronization with the clock signal CK, and inverters 4P and 4N. The VI converter 25 is a collection of circuits composed of MOS transistors MN1, MN2 and MN3 shown in FIG.

Here, let us consider what transfer characteristics the VI converter 25 should have in order to bring the characteristics of the voltage/time converter 1A' closer to the ideal linear characteristics. The time (t _p , t _n ) until the voltage of the nodes DP, DN falls below the threshold Vtinv of the inverters 4P, 4N is inversely proportional to the current (I _P , I _N ) as shown in the above equation (3). Therefore, if the current (I _P , I _N ) is a function of the differential voltage V _in as shown in equation (15) below, then the time output t _out will be linear with respect to the differential voltage V _in .

ここで、ａは任意の定数であり、ｂは、以下の式（１６）を満足する定数である。

Here, a is an arbitrary constant and b is a constant that satisfies the following equation (16).

ここで、Ｇは、電圧・時間変換器１Ａ’の利得である。

Here, G is the gain of the voltage/time converter 1A'.

As shown in FIG. 8, the transfer function (solid line) of the VI converter 25 in the voltage/time converter 1A' is compared with the ideal transfer function (dotted line). Since the VI converter 25 is composed of MOS transistors MN1, MN2, and MN3, the ideal transfer function between the differential voltage V _in and the current (I _P , I _N ) in the VI converter 25 is the difference It is a quadratic function of the dynamic voltage V _in (see formula (2) above). If the transfer function between the current (I _P , I _N ) and the differential voltage V _in is ideal as indicated by the dotted line, the relationship between the differential voltage V _in and the time output t _out is linear. . However, since the transfer function of the VI converter 25 in the voltage/time converter 1A' is linear, it is far from the ideal transfer function. This causes the nonlinearity of the voltage/time converter 1A'.

Therefore, as shown in FIG. 9, the voltage/time converter 1D according to the present embodiment operates according to a transfer function obtained by polygonal approximation of an ideal transfer function using two straight lines. Thereby, the linearity can be improved more than the voltage/time converter 1A' shown in FIG.

As shown in FIG. 10, the voltage/time converter 1D includes a conversion circuit 21 and a correction circuit 31.

The conversion circuit 21 differs from the conversion circuit 20 according to each of the above-described embodiments (for example, see FIG. 1) in that it includes a pair of resistors RI1 and RI2. The resistor RI1 is inserted between the MOS transistors MN1 and MN3, and the resistor RI2 is inserted between the MOS transistors MN2 and MN3. The conversion circuit 21 converts the differential voltage signals (V _inp , V _inn ) into a pair of currents ( _{IP1, IN1} ), and the voltage corresponding to the converted pair of currents ( _{IP1, IN1} ) is Input to inverters 4P and 4N. A change in the output voltages of inverters 4P and 4N is converted into a time output t _out . Here, the pair of currents (I _{P1 ,} I _N1 ) is defined as a first current set.

The transfer function of the first current _IP1 with respect to the differential voltage _Vin is a straight line that increases in proportion to the differential voltage _Vin , as shown in FIG. The slope of this increasing straight line can be adjusted by the values of resistors RI1 and RI2. The same applies to the first current _IN1 . In this way, the conversion circuit 21 inserts the pair of resistors RI1 and RI2 into the first MOS differential circuit to generate a first current that increases in proportion to the differential voltage signals (V _inp , V _inn ). Output the pair (I _{P1 ,} I _N1 ) as a pair of currents.

The correction circuit 31 adds a second current set ( _IP2 , _IN2 ) and a third current set ( _IP3 , _IN3 ) as correction currents to the first current set ₍ IP1, _IN1 ). .

As shown in FIG. 10, the correction circuit 31 includes a MOS differential circuit 31A as a third MOS differential circuit and a MOS differential circuit 31B as a fourth MOS differential circuit.

The MOS differential circuit 31A includes MOS transistors MNI4, MNI5, MNI6 and resistors RI3, RI4. A resistor RI3 is inserted between the MOS transistors MNI4 and MNI6, and a resistor RI4 is inserted between the MOS transistors MNI5 and MNI6. The MOS transistor MNI4 is inserted between the node DP and the MOS transistor MNI6, and receives the positive voltage signal V _inp of the differential voltage signals (V _inp , V _inn ) as a gate voltage. The MOS transistor MNI5 is inserted between the node DN and the MOS transistor MNI6, and receives the negative voltage signal V _inn of the differential voltage signals (V _inp , V _inn ) as the gate voltage. The MOS transistor MNI6 receives the clock signal CK and is inserted between the MOS transistors MNI4 and MNI5 and the terminal to which the voltage _Vs1 is applied.

The MOS differential circuit 31A outputs a second current set (I _P2 , I _N2 ). The transfer function of the second current _IP2 with respect to the differential voltage _Vin is a straight line that increases in proportion to the differential voltage _Vin , as shown in FIG. The slope of this increasing straight line can be adjusted by the values of resistors RI3 and RI4. The second current I _P2 does not flow in the range V _in <V _s1 +V _TH . _Vs1 is the offset voltage of MOS transistor MNI6, and voltage _VTH is the threshold voltage of MOS transistors MNI4 and MNI5. The differential voltage V _in from which the second current I _P2 flows can be adjusted by the value of the voltage V _s1 . The same applies to the second current _IN2 . Thus, the MOS differential circuit 31A receives the differential voltage signals (V _inp , V _inn ) as gate voltages, inserts a pair of resistors RI3 and RI4, and receives the differential voltage signals (V _inp , V _inn ). A second current set (I _P2 , I _N2 ) that increases in proportion to is output as a correction current.

Further, as shown in FIG. 10, the MOS differential circuit 31B includes MOS transistors MNI7, MNI8 and MNI9. MOS transistor MNI7 is inserted between node DP and MOS transistor MNI9, and MOS transistor MNI8 is inserted between node DN and MOS transistor MNI9. The MOS transistor MNI9 receives the clock signal CK and is inserted between the MOS transistors MNI7 and MNI8 and the ground. Gate voltages input to the MOS transistors MNI7 and MNI8 are constant voltages (V _pc , V _nc ).

The MOS differential circuit 31B outputs a third current set (I _P3 , I _N3 ). Since constant voltages (V _pc , V _nc ) are applied as gate voltages of the MOS transistors MNI7, MNI8, the transfer function of the third current I _P3 with respect to the differential voltage V _{in is} , as shown in FIG. It is constant regardless of the dynamic voltage _Vin . The magnitude of the third current I _P3 can be adjusted by the values of the gate voltages (V _pc , V _nc ). The same applies to the third current _IN3 . The MOS differential circuit 31B receives constant voltages (V _pc , V _nc ) as gate voltages, and outputs constant electric sets (I _P3 , I _N3 ) as correction currents.

These first current I _P1 , second current I _P2 , and third current I _P3 are added at node DP to become current I _p . Also, the first current I _N1 , the second current I _N2 , and the third current I _N3 are added to form a current I _N . Therefore, the transfer function of the pair of currents (I _P , I _N ) input to the inverters 4P, 4N is as shown in FIG. 11, which is an ideal transfer function approximated by a polygonal line. As a result, the linearity of the time output t _out with respect to the differential voltage V _in is improved.

Embodiment 5.
Next, Embodiment 5 of the present invention will be described.

As shown in FIG. 12, the voltage/time converter 1E according to the present embodiment includes a conversion circuit 21 and a correction circuit 32. As shown in FIG. In other words, the voltage/time converter 1E differs from the voltage/time converter 1D in that the correction circuit 32 is provided instead of the correction circuit 31 .

The conversion circuit 21 converts the differential voltage signals (V _inp , V _inn ) into a pair of currents ( _{IP1, IN1} ). This (I _{P1 ,} I _N1 ) is set as the first current set.

As shown in FIG. 12, the correction circuit 32 includes a MOS differential circuit 31A as a third MOS differential circuit and a MOS differential circuit 31B as a fourth MOS differential circuit. Same as 31. The correction circuit 32 further includes a MOS differential circuit 31C as a third MOS differential circuit.

The MOS differential circuit 31C includes MOS transistors MNI10, MNI11, MNI12 and resistors RI5, RI6. A resistor RI5 is inserted between the MOS transistors MNI10 and MNI11, and a resistor RI6 is inserted between the MOS transistors MNI11 and MNI12. The MOS transistor MNI10 is inserted between the node DP and the MOS transistor MNI12, and receives the positive voltage signal V _inp of the differential voltage signals (V _inp , V _inn ) as a gate voltage. The MOS transistor MNI11 is inserted between the node DN and the MOS transistor MNI12, and receives the negative voltage signal V _inn of the differential voltage signals (V _inp , V _inn ) as the gate voltage. The MOS transistor MNI12 receives the clock signal CK and is inserted between the MOS transistors MNI10 and MNI11 and the terminal to which the voltage _Vs2 is applied.

The MOS differential circuit 31C outputs a fourth current set (I _P4 , I _N4 ). The transfer function of the fourth current _IP4 with respect to the differential voltage _Vin is a straight line that increases in proportion to the differential voltage _Vin , as shown in FIG. The slope of this increasing straight line can be adjusted by the values of resistors RI5 and RI6. The fourth current I _P4 does not flow in the range V _in <V _s2 +V _TH . V _TH is the threshold voltage of the MOS transistors MNI10 and MNI11. The voltage from which the fourth current _IP4 flows can be adjusted by the value of the voltage _Vs2 . The same applies to the fourth current _IN4 . That is, the MOS differential circuit 31C receives differential voltage signals (V _inp , V _inn ) as gate voltages, has a pair of resistors RI3 and RI4 inserted therein, and is proportional to the differential voltage signals (V _inp , V _inn ). A fourth set of currents (I _P4 , I _N4 ) that increases as a correction current is output.

These first current I _P1 , second current I _P2 , third current I _P3 , and fourth current I _P4 are added at node DP to become current I _p . Also, the first current I _N1 , the second current I _N2 , the third current I _N3 , and the fourth current I _N4 are added at the node DN to become the current I _N . Therefore, the transfer function of the pair of currents (I _P , I _N ) with respect to the differential voltage _Vin input to the inverters 4P, 4N is as shown in FIG. . As a result, the linearity of the time output t _out with respect to the differential voltage V _in is improved.

As described above, in the present embodiment, as shown in FIG. 13, the ideal transfer function is approximated by a polygonal line with three straight lines. By further increasing the number of the third MOS differential circuits of the correction circuit 32, it is possible to approximate the ideal transfer function with four or more straight lines.

Embodiment 6.
Next, Embodiment 6 of the present invention will be described.

In the above first, second, third, fourth and fifth embodiments, the voltage/time converters 1A, 1B, 1C, 1D and 1E that linearly convert a differential voltage signal to a time output have been described. According to these voltage-time converters 1A, 1B, 1C, 1D, and 1E, the linearity from the differential voltage signals (V _inp , V _inn ) to the time output t _out is improved, and the conversion accuracy is improved. can be done.

In order to construct an analog/digital converter using the voltage/time converters 1A, 1B, 1C, 1D, and 1E, time output is provided after the voltage/time converters 1A, 1B, 1C, 1D, and 1E. A parallel time-to-digital converter must be installed to convert to a digital data signal. However, if a parallel type time-to-digital converter is used, increasing the conversion accuracy exponentially increases the circuit scale and the conversion time, increasing the power consumption and reducing the operating speed.

Therefore, in the present embodiment, an analog-to-digital converter in the time domain that does not cause an increase in power consumption and a decrease in operating speed even if the conversion accuracy is increased will be described. A subranging method is used in the analog-to-digital converter according to the present embodiment. The subranging method divides the analog-to-digital conversion into coarse conversion and fine conversion to reduce the required circuit scale.

As shown in FIG. 14, in the analog-to-digital converter 100 according to the present embodiment, the voltage-to-time converter 1B and the time-to-digital converter 10 are combined to form an analog-to-digital converter CADC as a high-order AD converter. , and an analog/digital converter FADC as a lower AD converter. The analog-to-digital converter 100 includes the analog-to-digital converters CADC and FADC, a residual error generating circuit 50, and an encoder 60 as a synthesizer.

The analog-to-digital converter CADC converts the input differential voltage signals (V _inp , V _inn ) into high-order m (m is a natural number less than n) bits of the digital signal of n (n is a natural number) bits. Convert to data signal DOUT<m−1:0>.

The residual generating circuit 50 generates a differential voltage based on the differential voltage signals (V _inp , V _inn ) and the high-order digital data signal DOUT<m−1:0> output from the analog-to-digital converter CADC. Generate a residual signal of the signals (V _inp , V _inn ).

The analog-to-digital converter FADC receives the residual signal and converts the residual signal into the lower nm-bit lower digital data signal DOUT<(nm)-1:0> of the n-bit digital signal. Convert.

The encoder 60 synthesizes the upper digital data signal DOUT<m−1:0> and the lower digital data signal DOUT<(n−m)−1:0> to generate an n-bit digital signal DOUT<n−1. : Output as 0>.

Since the analog-to-digital converters CADC and FADC use the voltage/time converter 1B, the linearity of the linear conversion from the differential voltage signals (V _inp , V _inn ) to the time output t _out is improved. . In this embodiment, instead of the voltage/time converter 1B, voltage/time converters 1A, 1C, 1D, and 1E having improved linearity may be used.

FIG. 15 shows an example of the circuit configuration of the time/digital converter 10. As shown in FIG. The time-to-digital converter 10 converts the time difference between the rising edges of the START signal and the STOP signal (time output t _out ) into a digital signal of k (k is m or nm) bits. The time/digital converter 10 includes delay circuits D1 to D2 ^k , flip-flops FF1 to FF2 ^k , and an encoder 11 .

When the START signal rises, the rising signal is propagated while being delayed by the delay circuits D1 to ^D2k . After that, when the STOP signal rises, the outputs of the delay circuits D1- ^D2k are latched by the flip-flops FF1- ^FF2k , respectively. By checking the outputs of the flip-flops FF1 to FF2 ^k , the encoder 11 detects to which stage of the delay circuit the rise of the START signal propagates at the time when the STOP signal rises. The encoder 11 converts the input timing signals (START signal, STOP signal) into digital signals DOUT<k-1:0> and outputs them. One LSB (time resolution) at this time is equal to the delay time _tpd of one delay circuit.

Another example of the circuit configuration of the time/digital converter 10 is shown in FIG. In this time/digital converter 10, interpolation circuits IP1 to IP2 ^k−1 are provided between delay circuits D1 to D2 ^k . Two rising signals with a time lag of t _pd are input to the interpolation circuits IP1 to IP2 ^k−1 . The interpolators IP1 to IP2 ^k-1 output pulse signals that rise at times between the two signals. This results in a pulse train that rises at intervals of t _pd /2. By latching this pulse train at the rising edge of the STOP signal, time-to-digital conversion can be performed with a time resolution of t _pd /2.

In the time-to-digital converter 10, the higher the time resolution, the shorter the conversion time. By adopting the configuration shown in FIG. 16, the conversion speed of analog-to-digital converter 100 can be improved. In addition, although FIG. 16 shows a configuration in which interpolation is performed once, the time resolution may be further increased by performing interpolation multiple times.

The differential voltage signals (V _inp , V _inn ) are converted into a time output t _out by the voltage/time converter 1B of the analog/digital converter CADC that performs high-order AD conversion, and the time output t _out is time/digital converted. Digital conversion is performed by the unit 10 to obtain a conversion result of the upper m bits.

FIG. 17 shows the circuit configuration of the residual generating circuit 50 corresponding to the case where the output of the analog/digital converter CADC is 2 bits (m=2). As shown in FIG. 17, the residual generating circuit 50 includes capacitors C0-C2 and switches S0-S3. The capacitance values of the capacitors C0 to C2 are set to C0=C1=C and C2=2C. VT is the upper limit voltage of the input voltage signal, VB is the lower limit voltage of the input voltage signal, and defines the input range of the voltage signal which is an analog signal.

_Vcom is a voltage that defines the common level of the output terminals OUTP and OUTN. During the track period in which the positive voltage signal V _inp is input, the switches S0 to S2 are connected to the input terminal INP to which the positive voltage signal V _inp is input, and the switch S3 is connected to the terminal to which V _com is input. there is

When the track period ends, the switches S0-S4 are turned off, and the positive voltage signal _Vinp at the end of the track period is sampled in the capacitors C0-C2.

After that, the residual generating circuit 50 switches the switches S0 to S2 according to the conversion result DOUT[1:0] of the analog-to-digital converter CADC. That is, if DOUT[0] is 1, the residual generator circuit 50 connects the switch S1 to VT, and if it is 0, connects it to VB. Residual error generating circuit 50 similarly connects switch S2 to VT if DOUT[1] is 1, and to VB if it is 0. FIG. In this way, the electric charges stored in the capacitors C0 to C2 are redistributed, and the conversion result of the parallel analog-to-digital converter CADC from the residual voltage signals (V _inp , V _inn ) is output to the output terminal OUTP. is output from the output terminal OUTP. The circuit configuration of the block to which the input terminal INN and the output terminal OUTN of the residual generator circuit 50 are connected is the same as the circuit configuration described above.

Since the capacitive residual generating circuit 50 can be configured only with the capacitors C0 to C2 and the switches S0 to S4, it has advantages of small area and small power consumption.

Returning to FIG. 14, the overall operation of the analog/digital converter 100 will be described. The analog-to-digital converter 100 subtracts the rough conversion result (upper-order digital signal) obtained by the analog-to-digital converter CADC from the differential voltage signals (V _inp , V _inn ) by the residual generating circuit 50 to generate a residual signal occurs. An analog-to-digital converter FADC, which performs fine conversion, receives the residual signal and converts it into a time _{output tout} by the voltage/time converters 1A and 1B.・Digital conversion is performed by the digital converter 10 to obtain a lower bit conversion result (lower digital signal). The rough conversion result and the fine conversion result are combined by an encoder 60 as a combiner and output as an n-bit digital data signal DOUT<n-1:0>.

Also, if 8-bit analog-to-digital conversion is configured without using the subranging method, an 8-bit parallel time-to-digital converter is required. In this case, 2 ⁸ (256) delay circuits and time comparators are required. On the other hand, if a subranging configuration of 4-bit coarse conversion and 4-bit fine conversion is used as in the present embodiment, two sets of 4-bit time-to-digital converters 10 are required, and 32 delay circuits and time comparators are required. One is enough. Therefore, it is possible to significantly reduce power consumption. Moreover, since the conversion time of the time-to-digital converter 10 is proportional to the number of delay circuits, the conversion time can be greatly shortened.

When the input differential voltage signals (V _inp , V _inn ) are large, the highly linear voltage/time converters 1A and 1B are required to obtain a highly accurate digital signal D<n-1:0>. Especially useful.

As described in detail above, according to this embodiment, the differential voltage signals (V _inp , V _inn ) are input, and the differential voltage signals (V _inp , V _inn ) are linearly adjusted to the time output t _out . When converting, the third-order component of the differential voltage signal (V _inp , V _inn ) included in the time output t _out can be removed, so good linearity can be obtained.

Further, according to the present embodiment, when the differential voltage signals (V _inp , V _inn ) are input and the differential voltage signals (V _inp , V _inn ) are linearly converted to the time output t _out , the voltage Since the transfer function between and the current can be brought close to the ideal transfer function, good linearity can be obtained. That is, according to the present embodiment, when a differential voltage signal is converted into a time output, a pair of currents corresponding to a pair of pulse voltage signals are corrected in order to maintain the linearity. can be obtained.

The configuration of the voltage/time converters 1A to 1C and the configuration of the voltage/time converters 1D to 1E may be combined to form a voltage/time converter.

Thus, according to each of the above-described embodiments, highly linear voltage/time converters 1A, 1B, 1C, 1D and 1E can be provided. Further, by using the voltage/time converters 1A, 1B, 1C, 1D, and 1E to configure time domain analog/digital converters CADC and FADC with a subranging configuration, power consumption increases even if the conversion accuracy is increased. , it is possible to provide the analog-to-digital converter 100 in which the operation speed does not decrease.

The present invention is capable of various embodiments and modifications without departing from the broader spirit and scope of the invention. Moreover, the embodiment described above is for explaining the present invention, and does not limit the scope of the present invention. That is, the scope of the present invention is indicated by the claims rather than the embodiments. Various modifications made within the scope of the claims and within the meaning of equivalent inventions are considered to be within the scope of the present invention.

The present invention can be applied to analog/digital converters and the like.

1A, 1B, 1C, 1D, 1E, 1A' voltage/time converter, 2P, 2N power supply voltage terminal, 3P, 3N capacitor, 4P, 4N inverter, 10 time/digital converter, 11 encoder, 20, 21 conversion circuit , 25 VI converter, 30 distortion correction circuit, 31, 32 correction circuit, 31A, 31B, 31C MOS differential circuit, 50 residual generation circuit, 60 encoder, 100 analog/digital converter, DP, DN nodes, D1- D2 ^k delay circuits, FF1-FF2 ^k flip-flops, MP1, MP2, MN1, MN2, MN3, MN1c, MN2c, MN4, MN3A, MN3B, MN4A, MN4B, MNI4, MNI5, MNI6, MNI7, MNI8, MNI9, MNI10, MNI11, MNI12 MOS transistors, RI1, RI2, RI3, RI4, RI5, RI6 resistors, IP1 to IP2 ^k-1 interpolation circuits

Claims (10)

a conversion circuit comprising a first MOS differential circuit for inputting a differential voltage signal as a gate voltage and converting it into a pair of pulse voltage signals indicating a time output corresponding to the magnitude of the differential voltage signal;
The first current corresponding to the pair of pulse voltage signals is based on the differential voltage signal so that the conversion from the differential voltage signal to the pair of pulse voltage signals in the conversion circuit maintains linearity. a correction circuit that corrects a pair of currents output from the MOS differential circuits of
A voltage-to-time converter with The correction circuit is
A distortion correction circuit comprising a second MOS differential circuit that removes high-order components of the differential voltage signal contained in the pair of pulse voltage signals by adding correction currents to the pair of currents, respectively.
Voltage-time converter according to claim 1. polarities of the input differential voltage signals are opposite between the first MOS differential circuit and the second MOS differential circuit;
The relationship between the gain coefficient β of the CMOS inputting the differential voltage signal in the first MOS differential circuit and the gain coefficient βc of the CMOS inputting the differential voltage signal in the second MOS differential circuit is ,
βc=(3−2√2)β
satisfy the
3. Voltage-time converter according to claim 2. Two gate voltages input to the second MOS differential circuit are constant voltages,
a CMOS gain coefficient β for inputting the differential voltage signal in the first MOS differential circuit;
The relationship between the gain coefficient βc of the CMOS to which the two gate voltages are input in the second MOS differential circuit is
βc = β
The filling,
a common level Vcom of the differential voltage signal input to the first MOS differential circuit;
The relationship between the two gate voltages input to the second MOS differential circuit and the common level Vc is
Vcom = Vc
satisfy the
3. Voltage-time converter according to claim 2. providing an offset between the positive side voltage and the negative side voltage of the two gate voltages input to the second MOS differential circuit to cancel offset components contained in the pair of pulse voltage signals;
5. Voltage-time converter according to claim 4. The conversion circuit is
inserting a pair of resistors into the first MOS differential circuit to output the pair of currents that increase in proportion to the differential voltage signal;
The correction circuit is
By adding a correction current to each of the pair of currents, the transfer function between the differential voltage signal and the current corresponding to the pair of pulse voltage signals is linearly approximated to an ideal transfer function.
Voltage-time converter according to claim 1. The correction circuit is
at least one third MOS differential circuit that receives the differential voltage signal as a gate voltage, has a pair of resistors inserted therein, and outputs the correction current that increases in proportion to the differential voltage signal;
Voltage-time converter according to claim 6. The correction circuit is
A fourth MOS differential circuit that inputs a constant voltage as a gate voltage and outputs a constant current as the correction current,
Voltage-time converter according to claim 6. A pair of CMOS source terminals for inputting a gate voltage are separated, and another CMOS controlled by a clock signal is connected to each source terminal.
Voltage-time converter according to any one of claims 1 to 8. an upper AD converter that converts an input differential voltage signal into an upper m (m is a natural number smaller than n) bit digital signal of an n (n is a natural number) bit digital signal;
a residual generating circuit for generating a residual signal of the differential voltage signal based on the differential voltage signal and the high-order digital signal output from the high-order AD converter;
a low-order AD converter that converts the residual signal into a low-order n−m-bit low-order digital signal of the n-bit digital signal;
a synthesizer that synthesizes the high-order digital signal and the low-order digital signal and outputs an n-bit digital signal;
with
At least one of the high-order AD converter and the low-order AD converter comprises the voltage/time converter according to any one of claims 1 to 9,
Analog-to-digital converter.

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