JP4978181B2 - Memory device - Google Patents

Description

  The present invention relates to a memory device having a write protect function for protecting data stored in a nonvolatile memory.

  A nonvolatile memory unit equipped with a nonvolatile memory mounted on a computer, or a nonvolatile memory and its memory control module, etc. is usually provided with a write protection function that prohibits data writing and deletion, and various stored settings It is configured to protect important data such as data and user data.

  For example, when a processor such as a CPU (Central Processing Unit) or MPU (Micro Processing Unit) writes data to a non-volatile memory or memory unit, the protection is set / released by a write protect signal output from the processor, and the data The write prohibition / permission of is switched. Then, data can be written only while the protection is released, and data cannot be written while the protection is set, so that the already stored data is protected.

In such a non-volatile memory or memory unit, if the power is shut off due to a power failure or the like during a data write operation performed by canceling the write protection, the data being written may be destroyed. Therefore, the operation memory area and the backup memory area are provided in the non-volatile memory, and the same data as the data written in the backup memory area is transferred to the operation memory at the timing when the flag is reset after the data is written to the backup memory area. By writing to the area, normal data exists in either the backup memory area or the operation memory area, and which is valid is indicated by a flag to prevent data writing failure at power shutdown A writing method has been proposed (for example, see Patent Document 1).
JP-A-7-84894

  Like user data, the power is cut off during the writing of a series of data that has a certain size and the correlation (continuity) of each contained information to the non-volatile memory, and the writing cannot be continued. In this case, the data is usually updated halfway and the process ends. Then, at the next start-up, the correlation of individual information included in a series of data is broken, so that it is treated as illegal data, and the data has to be initialized. However, it is desirable that user data including important information cannot be updated from the previous data rather than being initialized.

  Although it is possible to cope with such a malfunction by the data writing method of Patent Document 1 described above, a redundant nonvolatile memory is provided by providing a memory area for operation and a memory area for backup in the nonvolatile memory. Memory is required, which increases the cost and is not realistic.

  An object of the present invention is to solve the above-described problem, and to provide a memory device that can realize prevention of illegal data generation by a power shutdown during writing of a series of data with a simple configuration. It is said.

  The gist of the present invention for achieving the object lies in the inventions of the following items.

[1] A memory device that operates by receiving power supply from a power supply unit capable of continuing power supply for a predetermined time after power-off,
Non-volatile memory in which data is stored;
A volatile buffer memory that temporarily holds data stored in the nonvolatile memory;
Control means for controlling the writing of data to the nonvolatile memory and the buffer memory;
With
The capacity of the buffer memory allocated for holding during one release of protection is set to a capacity capable of transferring all the held data to the nonvolatile memory within the predetermined time.
The control means writes the data requested to be written to the nonvolatile memory into the buffer memory and temporarily holds the data while the input write protect signal indicates that the protection is released, and the write protect When the signal indicates a protection setting, the data is read from the buffer memory and written to the non-volatile memory on condition that a power interruption is not detected during the protection release .

In the above invention, the power supply unit continues to supply power for a predetermined time after the power is shut off. The control means writes the data requested to be written to the nonvolatile memory into the buffer memory and temporarily holds the data while the input write protect signal indicates that the protection is cancelled. This buffer memory is a volatile memory, and the capacity of the buffer memory allocated for holding during one release of protection is set such that all the held data can be transferred to the nonvolatile memory within a predetermined time. Then, when the write protect signal is switched to indicate the protection setting, data is read from the buffer memory and written to the nonvolatile memory on the condition that the power shutoff is not detected during the protection release .

In this way, data written to the non-volatile memory is temporarily held in the buffer memory during the release of write protection, and if the write protection is switched to the setting, it is a condition that no power shutoff was detected during the release of protection. By reading from the buffer memory and writing to the non-volatile memory, for example, the processor repeats the process of reading, decoding, executing, and writing back instructions to write a series of data to the non-volatile memory. By directly transferring data from the buffer memory to the non-volatile memory without any problem, processing can be performed in a short time. As a result, even if the power is shut off during data transfer from the buffer memory to the nonvolatile memory, all data can be written to the nonvolatile memory while the memory device is operable.

Further, even when the power is cut off during the data writing to the buffer memory, the data held in the buffer memory only disappears, and incomplete data is not written to the nonvolatile memory. As a result, even when a series of data having correlation (continuity) between individual pieces of information is written to the nonvolatile memory, incomplete update of the data due to termination in the middle of the data writing due to the power interruption occurs. Therefore, it is possible to avoid the problem that the data is treated as invalid data and must be initialized at the next startup. Therefore, it is possible to prevent illegal data from being generated due to power interruption in the middle of writing a series of data in the nonvolatile memory with a simple configuration without requiring a redundant nonvolatile memory.

  In addition, by executing the above control using the write protect function of the memory device, that is, when the write protect signal switches from release to setting, writing of all data requested to be written during release of protection is completed. This indicates that the data has been retained by the buffer memory. By using this write protect signal as a trigger signal for the control operation, for example, a dedicated trigger signal is generated and controlled. Thus, the configuration (control method) can be simplified.

[2] The memory device according to [1], wherein the control unit continuously writes the data to the nonvolatile memory.

  In the above invention, the data held in the buffer memory is continuously written to the non-volatile memory, so that the data can be transferred from the buffer memory to the non-volatile memory at a high speed. Can be transferred.

  According to the memory device of the present invention, it is possible to prevent illegal data from being generated due to power interruption during the writing of a series of data with a simple configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a main configuration of a data processing apparatus 11 including a nonvolatile memory unit 10 according to an embodiment of the present invention. The data processing device 11 is a device mounted on, for example, a personal computer that handles various data, or a laser printer or digital multi-function peripheral that mainly handles image data, and is the above-described (non-volatile) that is the memory device of the present invention. ) A memory unit 10 and a CPU 12 are provided.

  The CPU 12 has an arithmetic processing function and controls the operation of the entire apparatus including the memory unit 10. In writing and reading data to and from the memory unit 10, a specific data area is accessed by specifying a memory address.

  The memory unit 10 includes a nonvolatile memory 13 in which various data handled by the data processing device 11 is stored, and a (nonvolatile) memory control module 14 that controls writing and reading of data to and from the nonvolatile memory 13. Further, it has a write protect function for prohibiting data writing or deletion to the memory unit 10 itself.

  The non-volatile memory 13 is a memory that retains stored contents even when the power is turned off. The non-volatile memory 13 should store various parameters, setting data, user data, etc. unique to the apparatus even after the power is turned off. Predetermined data is stored. The non-volatile memory 13 also has a write protect function that prohibits writing and deleting of data to and from the non-volatile memory 13 itself.

  A buffer memory 15 (internal buffer memory) that temporarily holds data stored in the nonvolatile memory 13 is provided in the memory control module 14. The memory control module 14 also controls writing and reading of data with respect to the built-in buffer memory 15, and when storing the data held in the buffer memory 15 in the nonvolatile memory 13, the DMA ( Data is directly transferred from the buffer memory 15 to the nonvolatile memory 13 by direct memory access). Further, the memory control module 14 performs control to write data next requested to be written from the CPU 12 to the buffer memory 15 while transferring the data at the time of data transfer from the buffer memory 15 to the nonvolatile memory 13. .

  Even if the power supply (AC input) is cut off during operation, the data processing apparatus 11 can operate for several tens to several hundreds of milliseconds depending on the power stored in the power supply circuit and the internal circuit. Thus, the operable time when the power is shut off is determined. The capacity of the buffer memory 15 is set based on the operable time of the data processing apparatus 11 when the power is shut off. For example, when the operable time at the time of power-off is 50 ms (or 100 ms), the capacity is set such that all stored data can be transferred to the nonvolatile memory 13 within 50 ms (or 100 ms). Further, when the memory control module 14 transfers data to the non-volatile memory 13, the buffer memory 15 transfers the data held in a specific area to the non-volatile memory 13 and at the same time, the next data sent from the CPU 12 The memory area is divided so that can be received and held in another area.

  Regarding the write protect function of the memory unit 10, when the CPU 12 writes data to the memory unit 10, the memory control module 14 sets (validates) / cancels (invalidates) the write protection and switches the data write prohibition / permission. . Further, in writing continuous data, control is performed so that the memory unit 10 is held in the unprotected state during writing of the continuous data, and is returned to the protected state after the writing of all data is completed.

  Specifically, the CPU 12 outputs the write protect signal PS1 and the write request signal WS1 to the memory control module 14 of the memory unit 10, and when writing the data DT to the memory unit 10 (nonvolatile memory 13), the write protect signal The signal level of PS1 is switched from High to Low (see FIG. 2). The memory control module 14 that has detected the decrease in the write protect signal PS1 cancels the protection of the memory unit 10 and permits the writing of the data DT. The CPU 12 switches the signal level of the write request signal WS1 from High to Low after releasing the protection of the memory unit 10 or simultaneously with releasing the protection, and requests writing of the data DT, and the memory control module 14 receives the data DT sent from the CPU 12 Is written into the buffer memory 15. After completing the writing of the data DT, the CPU 12 switches the signal level of the write protect signal PS1 from Low to High, and the memory control module 14 that detects the rise of the write protect signal PS1 changes the memory unit 10 from the unprotected state to the set state. Switch to prohibit writing of data DT.

  Regarding the write protect function of the nonvolatile memory 13, when the memory control module 14 writes data to the nonvolatile memory 13, the nonvolatile memory 13 sets / cancels write protection and switches between prohibition / permission of data writing. Further, in writing continuous data, control is performed to hold the nonvolatile memory 13 in the unprotected state during the continuous data writing and to return to the protected state after the writing of all data is completed.

  Specifically, the memory control module 14 outputs the write protect signal PS2 and the write request signal WS2 to the nonvolatile memory 13, and when storing the data DT held in the buffer memory 15 in the nonvolatile memory 13, The signal level of the protect signal PS2 is switched from High to Low (see FIG. 2). The nonvolatile memory 13 that has detected the decrease in the write protect signal PS2 releases the protection and permits the writing of the data DT. The memory control module 14 requests the writing of data DT by switching the signal level of the write request signal WS2 from High to Low after releasing the protection of the nonvolatile memory 13 or simultaneously with releasing the protection, and reads the data from the buffer memory 15 Transfer and write to the non-volatile memory 13 (DMA transfer). After completing the writing of the data DT, the memory control module 14 switches the signal level of the write protect signal PS2 from Low to High, and the nonvolatile memory 13 that has detected the rise of the write protect signal PS2 switches from the protected state to the set state. Thus, writing of data DT is prohibited.

  Next, the operation of the data processing apparatus 11 including the memory unit 10 having the above configuration will be described.

  FIG. 2 illustrates the timing of the data writing operation to the memory unit 10 (nonvolatile memory 13) by the CPU 12, and the timing of the data writing operation to the nonvolatile memory 13 by the memory control module 14 in the memory unit 10. FIG. In the timing chart shown in FIG. 2, the operation between the CPU 12 and the memory control module 14 over time (change in the output level of the write protect signal PS1 / change in the output level of the write request signal WS1 / writing to the buffer memory 15). Data DT) and operation between the memory control module 14 and the nonvolatile memory 13 (change in output level of the write protect signal PS2 / change in output level of the write request signal WS2 / data DT to be written in the nonvolatile memory 13) ).

  As shown in FIG. 2, when writing data DT into the memory unit 10 (nonvolatile memory 13), the CPU 12 switches the signal level of the write protect signal PS1 output to the memory control module 14 of the memory unit 10 from High to Low. Then, the write protection of the memory unit 10 is canceled (invalidated) (T1).

  After the protection of the memory unit 10 is released, the CPU 12 switches the signal level of the write request signal WS1 from High to Low and requests writing of data DT. For example, when three data 0, data 1, and data 2 are written in that order, a data 0 write request (T2), a data 1 write request (T3), and a data 2 write request (T4) Are sequentially performed at a predetermined timing (time interval).

  The memory control module 14 writes and holds the data DT sent from the CPU 12 after the above write request in the buffer memory 15. In the example of the data 0 to 2 described above, the data 0 sent from the CPU 12 is written into the buffer memory 15 after the first data 0 write request (T2). When the writing of the data 0 is completed, the data 1 sent from the CPU 12 is written into the buffer memory 15 after the second data 1 writing request (T3). When the writing of the data 1 is completed, the data 2 sent from the CPU 12 is written into the buffer memory 15 after the last data 2 write request (T4). The data DT (data 0 to 2) is written and held in a specific area of the buffer memory 15, for example.

  When the writing of the data DT to the buffer memory 15 is completed, the CPU 12 switches the signal level of the write protect signal PS1 from Low to High and sets (enables) the write protect of the memory unit 10 (T5).

  When the memory control module 14 detects an increase in the write protect signal PS1, the signal level of the write protect signal PS2 output to the nonvolatile memory 13 is switched from High to Low, and the write protection of the nonvolatile memory 13 is canceled. Simultaneously with the cancellation of protection of the nonvolatile memory 13, the signal level of the write request signal WS2 is switched from High to Low to request writing of data DT from the buffer memory 15 to the nonvolatile memory 13 (T5). Then, the data DT held in the buffer memory 15 is written in the nonvolatile memory 13 by DMA transfer. In the example of the data 0 to 2 described above, the data 0 to 2 held in the buffer memory 15 are continuously written to the nonvolatile memory 13.

  When the writing of the data DT to the nonvolatile memory 13 is completed, the memory control module 14 switches the signal level of the write protect signal PS2 from Low to High and sets the write protection of the nonvolatile memory 13 (T8).

  When the next data DT is written to the memory unit 10 while the data DT of the buffer memory 15 is being written to the nonvolatile memory 13, the CPU 12 similarly changes the signal level of the write protect signal PS1 from High. By switching to Low, the write protection of the memory unit 10 is released (T6). After releasing the protection, the signal level of the write request signal WS1 is switched from High to Low to request writing of the next data DT (T7).

  Upon receiving this write request, the memory control module 14 writes and holds the next data DT sent from the CPU 12 after the write request in the buffer memory 15. For example, in the example in which the data 3 following the data 0 to 2 is written, the data 3 is written and held in an area different from the specific area in which the data 0 to 2 is previously written.

  As described above, in the memory unit 10, the data DT written to the nonvolatile memory 13 is temporarily held in the buffer memory 15 while the write protection of the memory unit 10 is released, and at the timing when the write protection is returned to the setting. The data is read from the buffer memory 15 and written to the nonvolatile memory 13. Further, while the memory control module 14 is writing the data DT (data 0 to 2) held in the buffer memory 15 to the nonvolatile memory 13, the CPU 12 performs the following on the memory unit 10 (nonvolatile memory 13). Data DT (data 3) can be written.

  Next, data management in the buffer memory 15 performed by the memory control module 14 in the above operation will be described using three types of examples.

  In the case of the data management example (1) shown in FIG. 3, the memory control module 14 writes data to the buffer memory 15 and writes the data sent from the CPU 12 to the nonvolatile memory 13 designated by the CPU 12. Assign (associate) and save the address.

  For example, the write data is data 0, data 1, data 2, data 3,..., Data N−1, data N, and the address of the write destination of each data to the nonvolatile memory 13 is address X0, address X1, In the case of address X2, address X3,..., Address XN-1, and address XN, the memory control module 14 is sent from the CPU 12 while the write protection of the memory unit 10 is being released (T1 to T6 in FIG. 2). Associate address X0 with incoming data 0, associate address X1 with data 1, associate address X2 with data 2, associate address X3 with data 3, ..., address XN-1 with data N-1 , And the address XN is associated with the data N and stored in the buffer memory 15. When the write protection of the memory unit 10 is switched from the release to the setting (T6 in FIG. 2), the memory control module 14 reads each data (data 0 to N) from the buffer memory 15 and specifies each designation in the nonvolatile memory 13. Write to addresses (addresses X0 to XN). In the case of this example, the addresses may be discontinuous.

  In the case of the data management example (2) shown in FIG. 4, the memory control module 14 writes the data sent from the CPU 12 to the nonvolatile memory 13 designated by the CPU 12 by writing data to the buffer memory 15. The data is blocked in units of consecutive addresses, header information including the write start address (head address) and size of the data in the block is assigned to each block, and the data is stored in the buffer memory 15.

  For example, the write data is data 0, data 1, data 2, data 3, data 4, data 5,..., Data N-1, and data N, and the address of the write destination of each data to the nonvolatile memory 13 is In the case of address X0, address X1, address X2, address X3, address X7, address X8,..., Address XX-1, and address XX, the memory control module 14 is in the process of releasing the write protection of the memory unit 10 (FIG. 2, T 1 to T 6), data 0 to 3 having consecutive addresses sent from the CPU 12 are blocked, and the header information including the write start address X 0 and the size 4 of the data block 0 is given. The data 5 is blocked and the data block 1 including the write start address X7 and the size 2 is included. The header information is applied, ..., and blocks of data N-1 and data N Grant header information including the write start address XX-1 and Size 2 of the data block M, and stored in the buffer memory 15. When the write protection of the memory unit 10 is switched from the release to the setting (T6 in FIG. 2), the memory control module 14 reads each data from the buffer memory 15 in units of blocks (data blocks 0 to M), and the nonvolatile memory Write to the area starting from each of 13 designated start addresses (start address X0, start address X7,..., Start address XX-1).

  In the case of the data management example (3) shown in FIG. 5, the memory control module 14 includes the address of the write destination to the nonvolatile memory 13 of the data received from the CPU 12 in the data write to the buffer memory 15. The physical block is read from the nonvolatile memory 13, the data is written and reflected in the read physical block, and stored in the buffer memory 15.

  For example, when the write data is data 0, the address of the write destination to the nonvolatile memory 13 is the address XM, and the physical block of the nonvolatile memory 13 including the address XM is the physical block M, the memory control module 14 During the write protection cancellation of the memory unit 10 (T1 to T6 in FIG. 2), the physical block M including the address XM of the data 0 sent from the CPU 12 is read (fetched) from the nonvolatile memory 13, and the read physical Data 0 is written in the block M and integrated (merged), and stored in the buffer memory 15. When the write protection of the memory unit 10 is switched from the release to the setting (T6 in FIG. 2), the memory control module 14 reads the physical block M in which the data 0 is integrated from the buffer memory 15 and stores it in the nonvolatile memory 13. Write back.

  In this data management example (3), only the physical block including the address of the write destination of the data received from the CPU 12 to the nonvolatile memory 13 is rewritten.

  As described above, in the memory unit 10 according to this embodiment, the data DT to be written to the nonvolatile memory 13 is temporarily stored in the buffer memory 15 in the memory control module 14 while the write protection of the memory unit 10 is released. When the write protection is switched to the setting, the data is read from the buffer memory 15 and written to the non-volatile memory 13. For example, the CPU 12 repeats the process of reading, decoding, executing, and writing back the instruction to store a series of data DT in a non-volatile manner. Compared with the case where data is written in the volatile memory 13, the data DT is directly transferred (DMA transfer) from the buffer memory 15 to the nonvolatile memory 13 without using the CPU 12, so that processing can be performed in a short time. Even if the power is cut off during data transfer from the buffer memory 15 to the nonvolatile memory 13, all the data DT can be written to the nonvolatile memory 13 while the memory unit 10 is operable.

  In addition, even when the power is shut off during the writing of data DT to the buffer memory 15 or before the data DT held in the buffer memory 15 is transferred from the buffer memory 15 to the nonvolatile memory 13, the data is held in the buffer memory 15. The incomplete data is not written in the nonvolatile memory 13 only by the disappearance of the data DT. As a result, even when user data that has correlation (continuity) in individual information contained therein is written to the non-volatile memory 13, the end of data writing due to power interruption and incomplete data update may occur. Therefore, it is possible to avoid the problem that the data is treated as invalid data and must be initialized at the next startup. Therefore, it is possible to prevent illegal data from being generated due to power interruption while writing a series of data in the nonvolatile memory 13 with a simple configuration without requiring a redundant nonvolatile memory. In addition, when the above-described control is executed by using the write protect function provided in the memory unit 10, that is, the timing at which the write protect signal PS1 is switched from the release to the setting (Low → High), a write request is issued during the release of protection. This indicates that all data has been written (data retention by the buffer memory 15 is completed). By using this write protect signal PS1 as a trigger signal for control operation, for example, a dedicated trigger signal is generated. Therefore, the configuration (control method) can be simplified as compared with the case where control is performed.

  In addition, by continuously writing the data DT (data 0 to 2) held in the buffer memory 15 to the nonvolatile memory 13, the data DT can be transferred from the buffer memory 15 to the nonvolatile memory 13 at a high speed. It is possible to transfer characteristic data in a shorter time.

  Furthermore, while the memory control module 14 is writing the data DT from the buffer memory 15 to the nonvolatile memory 13, the CPU 12 can write the next data DT, so that the writing speed does not decrease.

  The embodiment of the present invention has been described with reference to the drawings. However, the specific configuration is not limited to that shown in the embodiment, and there are changes and additions within the scope of the present invention. Are also included in the present invention.

  For example, in the embodiment, the buffer memory 15 included in the memory unit 10 is provided inside the memory control module 14. However, the buffer memory 15 may be provided outside the memory control module 14.

  Further, the power shutdown is monitored, and while the write protect signal PS1 from the CPU 12 indicates the protection release (signal level Low), or before the write protect signal PS1 switches from the release to the setting (signal level Low → High). The data may be written from the buffer memory 15 to the non-volatile memory 13 on condition that the power interruption is not detected during the predetermined period. As a result, it is possible to reliably prevent the operation possible time after power-off from being overwritten during the writing of data from the buffer memory 15 to the nonvolatile memory 13 and becoming unwritable. The predetermined period described above may be set based on the remaining time obtained by subtracting the time required for writing data from the buffer memory 15 to the nonvolatile memory 13 from the operable time after the power is turned off.

  In the embodiment, the case where both the memory unit 10 and the nonvolatile memory 13 have the write protect function has been described as an example. However, the write protect function of the nonvolatile memory 13 may not be provided. Whether or not the nonvolatile memory itself has a write protection function depends on the specifications of the memory. According to the present invention, the nonvolatile memory itself does not have the write protection function, but the device including the nonvolatile memory itself does not have the write protection function. The present invention can also be applied to a memory device (nonvolatile memory unit) having a protect function.

It is a block diagram which shows the main structures of the data processor provided with the memory unit which concerns on embodiment of this invention. It is a timing chart which shows the operation timing at the time of data writing of the data processor concerning an embodiment of the invention. It is explanatory drawing which shows the data management example (1) in the buffer memory which concerns on embodiment of this invention. It is explanatory drawing which shows the data management example (2) in the buffer memory which concerns on embodiment of this invention. It is explanatory drawing which shows the data management example (3) in the buffer memory based on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Memory unit 11 ... Data processing apparatus 12 ... CPU
DESCRIPTION OF SYMBOLS 13 ... Nonvolatile memory 14 ... Memory control module 15 ... Buffer memory DT ... Data PS1 ... Write-protect signal PS2 ... Write-protect signal WS1 ... Write request signal WS2 ... Write-request signal

Claims (2)

A memory device that operates by receiving power supply from a power supply unit capable of continuing power supply for a predetermined time even after power-off,
Non-volatile memory in which data is stored;
A volatile buffer memory that temporarily holds data stored in the nonvolatile memory;
Control means for controlling the writing of data to the nonvolatile memory and the buffer memory;
With
The capacity of the buffer memory allocated for holding during one release of protection is set to a capacity capable of transferring all the held data to the nonvolatile memory within the predetermined time.
The control means writes the data requested to be written to the nonvolatile memory into the buffer memory and temporarily holds the data while the input write protect signal indicates that the protection is released, and the write protect When the signal indicates a protection setting, the data is read from the buffer memory and written to the non-volatile memory on condition that a power interruption is not detected during the protection release . The memory device according to claim 1, wherein the control unit continuously writes the data to the nonvolatile memory.

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