JP2000020401A - Cpu device, information processor and control method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-reliability CPU device by preventing a CPU from reloading a program copied in a DRAM by itself concerning the CPU device with built-in DRAM. SOLUTION: Concerning a CPU device 10 with a built-in CPU core 11 and DRAM 12, a managing part 15 for managing the DRAM 12 is provided with a write protect circuit 16 for inhibiting write to the prescribed address of the DRAM 12. At the time of copying the program into the DRAM 12, write inhibition is canceled and after copy, the program is executed in the state of write inhibition. When a write instruction is outputted to the address of write inhibition, an interruption signal is returned to the CPU core 11. Thus, the program is prevented from being reloaded, a module, to which an illegal access is performed, is specified and program development efficiency can be improved as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CPU device mounted on a printer or other information processing device, and an information processing device using the same.

[0002]

2. Description of the Related Art In an information processing apparatus such as a printer for performing a specific process, an execution program stored in a ROM in advance is copied to a RAM having a high input / output speed, and the
The processing speed has been improved by executing a program on the AM by a CPU.

[0003]

In a color printer or the like, the amount of data to be processed by the CPU becomes enormous.
C (personal computer, personal computer) for storing printing data inputted, or storing an intermediate code obtained by processing the data, and further sending to a printing mechanism (print engine) for performing color printing. In order to store data, a RAM having a large storage capacity is required. In addition, the storage area required for storing programs due to factors such as an increase in the number of functions to be processed on the printer side and an increase in the number of languages mounted on the printer to enhance versatility. Is also getting bigger.

On the other hand, although the market price of the RAM is decreasing, the RAM having a large storage capacity is expensive.
Further, a RAM having a high input / output speed such as an SDRAM is also commercially available, but such a high-speed RAM is expensive in terms of storage capacity. Therefore, in order to realize a low-cost, high-speed printer, it is important to efficiently allocate a storage area of the RAM having an appropriate storage capacity to an area for storing processing data and an area for copying a program. It has become.

As one method, as shown in FIG. 1, a TL having a function of converting a virtual address to a physical address is provided.
Using a memory management unit (MMU) such as B (Translation Lookaside Buffer) 19, RA is limited to the program modules necessary for one job processed by the printer among the programs stored in the ROM 5.
Copying to M3, assigning a physical address of the RAM to the module, and executing the module on the RAM are being considered. According to this method, the area of the RAM required for copying the program module can be reduced, and the storage capacity of the RAM can be effectively used.
Therefore, the storage capacity of the RAM does not become too large. Even if an expensive memory such as an SDRAM is used, the limited storage capacity is effectively used as a storage area for programs and data, and the processing speed is high. A printer can be realized at low cost.

FIG. 1 is a block diagram showing an outline of a control system of the printer 1, which includes a CPU device 10 having a CPU core 11 and a TLB 19.
An SDRAM 3 serving as a work storage area, a memory controller 2 for managing addresses of the memory, input / output, management of other memories, and the like, and a CPU bus 6 for connecting these are provided. The memory controller 2 is further provided with an initial setting program (IP
L) is connected to a ROM 5 storing a plurality of program modules for executing a drawing processing function, a language processing function, and the like, and these programs are loaded into the CPU core 11 to operate the printer 1. I do.
The CPU bus 6 further stores print data from a PC (not shown) or the like in a predetermined storage area of the SDRAM 3 by DMA.
A receiving DMA controller 21 to be transferred and a DMA controller 22 to DMA-transfer drawing data processed by the CPU core 11 from a predetermined area of the SDRAM 3 to a printing mechanism (engine) 23 are also connected.

Further, in recent years, as shown in FIG.
A DRAM 12 of about 2-3 MB together with the core 11 and a DRA for managing input / output and addresses of the DRAM 12
CPU device 10 having a built-in M control circuit 18 and connected to CPU bus 6 via external bus control circuit 13
It has been studied to use as a control system of the printer 1. Of course, DRAM built in CPU device
However, at present, it is difficult to incorporate a DRAM having an extremely large storage capacity into a CPU device in view of the size and cost of a CPU chip. However, the DRA built into this CPU device
If the program is copied to M and executed, the processing speed can be maximized because there is no restriction on the interface between the chips or the access speed of the bus for connecting the chips.

Further, if the program module to be copied on the RAM can be limited by the above-described method using the TLB, the program is actually copied to a limited storage capacity DRAM built in the CPU device. This makes it possible to execute a program in the DRAM 12 by using the program as an area to be executed. In particular, unlike a PC that executes general-purpose applications and is expected to be able to process them at a high speed, an information processing apparatus specialized for a predetermined use such as a printer or a scanner requires a CPU in consideration of a job unit. Are limited in the number of program modules to be executed. Therefore, MM such as TLB
Even if the virtual storage method using U is used, there is almost no chance that the processing time of the CPU is devoted to processing such as paging due to a TLB miss, and the processing speed can be greatly improved.

Some CPU devices for PCs incorporate a SRAM (static RAM) having a shorter access cycle than a DRAM (dynamic RAM) for a primary cache. It is necessary to ensure that data on the cache memory is identical to data on a storage medium such as an external RAM or a hard disk. For this reason, a cache management circuit of the write-through or write-back cache system is replaced with an SRA having a large circuit scale.
Since it is necessary to incorporate the memory together with M, the area for the cache becomes very large, and it is difficult to increase the storage capacity of the cache. On the other hand, since the DRAM may have a smaller circuit scale than the storage capacity, a memory having a large storage capacity can be built in the CPU device at a relatively low cost.

Furthermore, in an information processing apparatus specialized for a specific application such as a printer, not a general-purpose information processing apparatus such as a PC, as described above, the memory built in the CPU device has a program. Is used as an area to be copied to execute the operation, or as a temporary work area where the data does not need to be kept identical to the data on the external RAM or the hard disk, so that no cache management circuit is required. It is. In addition, as described above, in an information processing apparatus specialized for a use such as a printer, the frequency of rewriting the memory in the CPU device is small when considered on a job basis, so that the effect of sufficiently improving the processing speed with the DRAM can be expected. . As described above, by employing a CPU device having a built-in DRAM, it is possible to provide a low-cost, high-performance printer.

However, the DRAM 1 in the CPU device
When the operation is performed using the information processing device 2, the state cannot be monitored outside the CPU device 10.
R is stored in the program area of the DRAM 12 in the CPU device.
The module required for the execution program is copied from the OM 5, the CPU core 11 fetches an instruction from the DRAM 12, and stores data in the DRAM 12 according to the instruction.
Consider output to the work area.

In this process, a write signal φw, a read signal φr, and an address signal φa are input to the DRAM 12 to input and output data signals. Of these, the write and read signals and the address signal are ,
It is supplied from a DRAM controller connected to the CPU core 11 and the address bus 14a of the internal bus 14. The data input to and output from the DRAM 12 is also used by the CPU core 1.
1 through the data bus 14d of the internal bus 14. Therefore, signals to DRAM 12 are all C
Since the replacement is performed inside the PU device 10, the execution status cannot be monitored from outside the CPU device. Therefore, even if there is an illegal access to the DRAM 12 due to a defect at the time of copying to the DRAM 12 or a defect of the execution program stored in the ROM 5, even if a part of the copied program is rewritten, it should be monitored. Can not. For this reason, when an instruction rewritten incorrectly is fetched, the CPU core 11 repeats illegal access or stops the subsequent processing as an abnormal instruction. Then, at this stage, you can finally understand that an abnormality has occurred,
In many cases, it is not possible to determine the cause of the abnormality or to restore the data or program to normal.

An SD outside the CPU device as shown in FIG.
If the processing is executed using the RAM 3, it is possible to determine what processing is being executed by the CPU core 11 by observing the CPU bus 6. Also,
When a situation in which the program copied to the SDRAM 3 is rewritten due to a program failure or the like occurs, it is easy to detect the situation because a write cycle to the SDRAM 3 occurs only. Therefore, even when developing a program, a defect can be found without taking much time. However, in the system as shown in FIG. 2, since the processing is closed in the CPU device, it cannot be detected externally, and it takes time to develop a program. Furthermore, the DRA built in the CPU device
As the capacity of M increases and the number of processes closed in the CPU device increases, it becomes more difficult to grasp the instruction being executed by the CPU, and the program development efficiency also decreases. Therefore, it takes time and cost to provide a highly reliable program, and it is difficult to provide a product utilizing the hardware in an environment where a high-performance printer can be provided at low cost. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a CPU device having a built-in RAM which can prevent unauthorized access when a program copied to the RAM is executed inside the CPU device. And It is another object of the present invention to provide a CPU device capable of observing such an execution state externally and efficiently developing a highly reliable program that does not cause unauthorized access. It is still another object of the present invention to provide an information processing device using such a CPU device, a control method for the information processing device, and a control program.

[0015]

Therefore, according to the present invention, a protection function for inhibiting writing to a specific address of a RAM built in a CPU device is provided in the CPU device so that a program copied to the RAM is illegal. It is designed to prevent modification by access.
Further, when a write instruction for a write-protected address is output from the CPU core, it is fed back to the CPU core to notify the outside that an illegal access has occurred. That is, of the present invention,
A CPU core unit, a RAM unit, a RAM management unit that manages input and output to and from the RAM unit, a CPU core unit, and a RAM
In a CPU device having a built-in unit and a bus connecting the RAM management unit, the RAM management unit is characterized in that it has a protection function capable of prohibiting writing to a specific address of the RAM unit. Furthermore, the RAM management unit has a notifying function of notifying the CPU core unit that the CPU core unit is illegal when a write instruction for an address for which writing is prohibited by the protection function is output from the CPU core unit. .

In an information processing apparatus including such a CPU device and an external storage device such as a ROM storing a program executable by the CPU device, a protection function capable of prohibiting writing of a specific address is provided. , RA
A first function or step of making the write-protected area of the M section writable and copying at least a part of the program (module) of the external storage device; And a second function or step of executing the copied program. By using these functions or processes, the area (address space) where the program on the RAM section is copied can be write-protected, so that the program is protected from being modified even if there is an access to perform an illegal write at that address. it can.

Further, by notifying the CPU core unit that such unauthorized access has been made to the RAM unit, the CPU core unit can stop the process and issue a warning to the user. Alternatively, by providing a third function or step of determining and outputting a module that has issued an illegal write command, a failure in the program module can be notified to the developer, so that program development efficiency can be improved.

The write protection function can be implemented by some means. The RAM management unit can be provided with a write protect circuit that decodes an address output from the CPU core unit and does not output a write enable signal to the RAM unit if the address is prohibited from being written. By providing a dedicated circuit for write protection,
Even a CPU device that does not have an address conversion function described later can incorporate a protection function. Also,
It is possible to provide a protection function with the highest versatility, such as prohibiting rewriting of a program as well as rewriting of important data for executing processing in the CPU core.

When the RAM management unit has a conversion buffer for converting a virtual address output from the CPU core unit to a physical address of the RAM unit, an address for which writing is prohibited is set in the physical buffer in this conversion buffer. The protection function can also be realized by providing the function. Further, the area on the CPU device required to realize the protection function can be reduced. Furthermore, by removing the write-protection to the write-protected address and copying the program, and then activating the protection function, even if the program copied on the RAM is changed, the write-protection is surely performed. Can be.

An information processing apparatus having such a CPU device and an external storage device such as a ROM storing a program executable by the CPU device has a limited number of program modules to be executed for each job. It is suitable for an information processing apparatus specialized for a specific use, such as a printing apparatus that is rarely copied to a RAM in the printer. In an information processing apparatus that specializes in such processing, furthermore, the frequency of copying is low, and the input / output to / from an external storage device is performed so that data rewritten like a cache matches the external storage device. Since there is no need to repeat this, the RAM unit incorporated in the CPU device may be a DRAM. Therefore, according to the present invention, a CPU device having a compact memory having a large storage capacity, which can be supplied at low cost, and which has a high-speed and highly reliable processing function.
A U-device can be provided. Further, by using this CPU device, it is possible to provide an information processing device which can be supplied at high speed, with high reliability and at a low cost, and a printing device having a printing mechanism for printing data processed by the CPU device. Can be.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the drawings. FIG. 3 is a block diagram showing a schematic configuration of the printer 1 according to the present invention. The main configuration of the control system 8 of the printer 1 of this embodiment is the same as that of the printer control system shown in FIG. 1 or FIG.
U device 10, working SDRAM3, SDRAM3
And a memory controller 2 for managing other memories, etc., are connected via a CPU bus 6, and a ROM 4 storing an initial setting program (IPL) in the memory controller 2 via an external bus 7, A ROM 5 that stores a plurality of program modules for executing processing functions, language processing functions, and the like is connected. Also,
The CPU bus 6 includes a receiving DMA controller 21 for transferring DMA for printing data and a DMA controller 22 for transferring DMA for drawing data processed by the CPU core 11 to a printing mechanism (engine) 23. It is connected.

The CPU device 10 of the present embodiment includes a CPU core 11 that executes processing based on instructions fetched from the ROM 4 or 5 and the built-in DRAM 12, a DRAM 12 serving as a working memory inside the CPU device 10, and A management unit 15 that manages the DRAM 12, an internal bus 14 that connects these inside the device, and an external bus control unit 13 that is an interface between the CPU bus 6 of the external bus and the internal bus 14 are provided. The management unit 15 of this example that manages the DRAM 12 converts the virtual address into a physical address by using T
LB 19 and a DRAM that decodes an address output from CPU core 11 and supplies write signal φw, read signal φr, and address signal φa to DRAM 12
And a controller 18.
A write protect circuit 16 is provided which can write-protect a part of the AM 12.

As shown in an enlarged manner in FIG. 4, the write protect circuit 16 includes a look-up table 32 in which addresses to be write-protected among the physical addresses of the DRAM 12 are set. A decoding unit 31 that decodes an address output to the address bus 14a to determine whether the address is a write-protected address, and is set to 0 if the address is write-protected and set to 1 if the address is write-protected. And a flip-flop 33. Further, the write protect circuit 16 outputs the output of the flip-flop 33 and the DR
An AND circuit 34 is provided for calculating the logical product of the write signal φw from the AM controller 18 and the write signal φw output from the DRAM controller 18 when the write signal φw is a write signal for an address to which writing is permitted.
The write signal φwp for the RAM 12 is set to 1 and supplied. Even if the write signal φw is 1 for the write-protected address, the write signal φwp for the DRAM 12 is
wp is not set to 1.

Further, there is provided an AND circuit 35 for inverting and inputting the output of the flip-flop 33 and taking a logical product with the write signal φw from the DRAM controller 18.
DRAM controller 18 for write-protected addresses
When the write signal φw from the CPU becomes 1, the interrupt signal φi is set to 1 and output to the CPU core 11. Note that the final write signal φ for the DRAM 12
The output of the flip-flop 33 is input from the external memory controller 2 to the AND circuit 34 for generating wp via the OR circuit 36 for calculating the logical sum with the protect signal φp, and the program is copied from the ROM 5 to the DRAM 12. In this case, the write protection can be removed by setting the protection signal φp to 1.

As described above, the write protect circuit 16 of the present embodiment switches the write signal φwp to output a write enable signal to a write-protected address without prohibiting writing to a predetermined address. When a write signal for the write-protected address is output, the CPU core 1
1 is provided with a notification function for feeding back to the user. Therefore, the write protect circuit 16 allows the DRAM
A write-protected area 12a in the address space of No. 12;
It is possible to set an area 12b that is not write-protected, and the write-protection of the area 12a that is write-protected can be released as necessary.

An outline of the processing in the control system 8 of the printer 1 including the CPU device 10 of the present embodiment will be described with reference to FIGS. FIG. 5 shows the DRA of the CPU device 10.
A process for copying a part (module) of the program stored in the ROM 5 to M12 is shown.
This processing is performed when the printer 1 is reset.
4 is performed by the IPL stored in the IPL. Also,
This is performed when it is necessary to rewrite the program copied to the DRAM 12 due to a TLB miss or the like. The printing data supplied to the printer 1 is described in different languages such as ESC / P of Seiko Epson or PCL of Hewlett-Packard, but these processing languages may be changed on a job-by-job basis. There is no. In addition, since the conditions such as the resolution of the image data to be processed or the color / monochrome are not changed, the process of switching the programs stored in the DRAM 12 of the CPU device is performed while one job is being executed. This is not performed, and is performed when a job having a different condition such as a processing language occurs.

To change the program copied to the DRAM 12, first, at step 51, the protect signal φp output from the memory controller 2 is set to 0.
Then, the write protection of the DRAM 12 is released, and the module necessary for executing the job among the programs stored in the ROM 5 is set to the DRA in step 52.
Copy to a write-protectable area of M12 (first function or step). Since a part of the execution program stored in the ROM 5 under the control of the memory controller 2 is copied to the DRAM 12, the DRAM 1
The timing of copying to the write protected area 2 can be grasped by the memory controller 2. As described above, by allowing the memory controller 2 to release the write protection,
The write protection of the DRAM 12 can be canceled or set without being affected by the program executed by the CPU core 11. Therefore, even if the program copied to the DRAM 12 is abnormal, the CPU core 1
1 will not release write protection,
It is safe.

Next, when the data is copied to the DRAM 12, the protection signal φp is set to 0 in step 53, and the address where the program has been copied is written to the write protection circuit 16.
Write protection is performed using the protection function described above, and the area of the DRAM 12 where the program is copied is write-protected. In this state, the CPU core 11 fetches an instruction from the program (module) copied to the DRAM 12 in step 54 and executes the job (second function or process). Then, if a write instruction is fetched illegally during the execution of the job, the write is not executed and the program is protected as shown in FIG. 6, and an error signal φi is generated to perform error processing. Therefore, R
Even when a program module prepared in the OM 5 includes an instruction for performing an illegal access, the operation of the CPU core 11 is stopped before the execution, and a service call is requested to the user. Can be. For this reason, it is possible to prevent a program copied to the DRAM 12 from being altered or an abnormal process being executed by the CPU core 11 accompanying the modification. Therefore, the reliability of the control operation of the printer 1 can be further improved.

In step 61, when a write address is output from the CPU core 11 to the address bus 14a of the internal bus, in step 62 the write protect circuit 16 decodes the address and determines whether the address is write protected. Determine whether or not. Step 63
In the case where a write signal φw is output to an address that is not write-protected, φwp is set to 1
In step 66, writing to the DRAM 12 is executed.

On the other hand, if the write signal φw has been output for the write-protected address, an interrupt signal φi is output to the CPU core 11 in step 64, and error processing is performed in step 65. In this error processing, it is indicated that an illegal write instruction has been issued, and the module that fetched the instruction is specified and output (third function or process). The module containing the illegal write instruction can be immediately identified. Therefore, even if the program module controls the process closed by the PCU device 10, the
Regarding the illegal write process for the module 12, the module containing the instruction can be immediately specified and debugged.

For this reason, even for a program that performs processing that is closed by the CPU device, it is easy to grasp the location of a defect at the development stage, and the program development efficiency can be greatly improved, and a highly reliable program can be obtained. Can be provided. Further, even when an error occurs on the user side, the location of the defect can be specified, so that the after-sales service or the complaint processing can be quickly dealt with.

As described above, by employing the CPU device 10 having the write protection function of the built-in memory according to the present embodiment, it is possible to rewrite the program module copied to the DRAM 12 built in the CPU device 10 by itself. Can be prevented. Therefore, C
Copy the program module to the DRAM 12 built in the PU device 10 and execute processing based on the copied program module.
A high-speed and highly reliable printer 1 can be provided. Further, only the program modules necessary for the job executed by the printer 1 can be copied to the DRAM 12, and the copied program can be protected.
For this reason, it is possible to provide a high-reliability, high-speed printer at a low cost, which effectively utilizes the DRAM 12 built in the CPU device 10. Of course, it is also possible to use the entire DRAM 12 as a copy area of the program module and write-protect the entire DRAM 12 during execution of the program. However, as in this example, D
By dividing the RAM 12 into a write-protected area 12a and a non-write-protected area 12b and using a part of the DRAM 12 as a work area for outputting drawing data and the like, the total processing time may be reduced.

In this embodiment, the write protect circuit 1
6, the protection function of the DRAM 12 is realized.
When converting the virtual address to the physical address in the TLB 19, it is of course possible to set an address for which writing is prohibited in the physical address. The method using TLB is excellent in that no new circuit is required, but
There is a possibility that the protection function cannot be used in an information processing apparatus that operates on an OS that does not use the virtual storage method, and the opportunity to use the protection function may be limited. Therefore, in terms of versatility, it is desirable to provide a dedicated circuit for the protection function.

Although the DRAM is used as the built-in memory in the CPU device 10 of the present embodiment, it is of course possible to provide the above-described write inhibit function in the cache circuit using the SRAM. However, as described above, the cache circuit is a circuit having great versatility, and it is necessary to ensure the sameness as data on an external storage device such as a hard disk or a RAM disk. If the function is installed, the circuit scale becomes very large, and it is difficult to realize. On the other hand, as in the case of the CPU device 10 of the present embodiment, a DRAM having a large storage capacity can be built in at a relatively low cost. Furthermore, in an information processing apparatus such as a printer, which specializes in processing, the method of using the DRAM is limited to a copy of a program or a storage area for temporarily generated data. Yes. Therefore, it is possible to provide a CPU device having a built-in write protection function at low cost, and it is possible to provide an information processing device such as a printer capable of executing high-speed and highly reliable processing at low cost.

[0035]

As described above, according to the present invention, a protection function capable of prohibiting writing to the RAM built in the CPU device is provided.
It is possible to prevent the program copied to the RAM from being rewritten by the CPU itself, and to obtain a highly reliable CP.
A U device and an information processing device using the same can be provided.
Furthermore, by providing a notification function for outputting a module when an unauthorized access is made, together with a protection function, program development efficiency can be improved, and a highly reliable program can be easily developed and provided. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an outline of a printer having a function of copying some modules of an execution program on a ROM to a RAM using a virtual storage method and executing the modules.

FIG. 2 is a block diagram illustrating an outline of a printer using a CPU device having a built-in memory.

FIG. 3 shows a C having a protection function according to the embodiment of the present invention.
FIG. 2 is a block diagram illustrating an outline of a printer using a PU device.

FIG. 4 is a diagram illustrating a circuit example of the write protect circuit illustrated in FIG. 3;

FIG. 5 is a flowchart illustrating a process of copying a part of a program to a DRAM built in a CPU device in the printer illustrated in FIG. 3;

FIG. 6 is a flowchart showing how the printer shown in FIG. 3 executes a program copied to a DRAM incorporated in a CPU device.

[Explanation of symbols]

 Reference Signs List 1 printer 2 memory controller 3 SDRAM 4, 5 ROM 6, 7 bus 10 CPU device 11 CPU core 12 built-in DRAM 13 external bus control circuit 15 DRAM management unit 16 write protect circuit 18 DRAM controller 19 TLB 21 receive DMAC 22 video DMAC 23 print Mechanism (engine)

Claims (12)

[Claims] 1. A CPU core unit, a RAM unit, and an RA
A RAM management unit for managing input / output to / from the M unit;
A CPU device including a PU core unit, a RAM unit, and a bus connecting the RAM management unit, wherein the RAM management unit has a protection function capable of prohibiting writing to a specific address of the RAM unit. A CPU device characterized by the above-mentioned. 2. The RAM management unit according to claim 1, wherein the RAM management unit notifies the CPU core unit that if a write instruction for an address that is write-protected by the protection function is output from the CPU core unit, the CPU core unit is invalid. A CPU device having a notifying function to perform the following. 3. The RAM management unit according to claim 1, wherein the RAM management unit decodes an address output from the CPU core unit, and if the address is a write-protected address, the RAM management unit decodes the address.
A CPU device comprising a write protect circuit that does not output a write enable signal to an M section. 4. The RAM according to claim 1, wherein the RAM management unit includes a conversion buffer for converting a virtual address output from the CPU core unit to a physical address of the RAM unit. A CPU device having a function of setting a write-protected address in an address. 5. The RAM according to claim 1, wherein the RAM unit is a DR unit.
A CPU device, which is an AM. 6. The CPU device according to claim 1, wherein
A first function of having an external storage device storing a program executable by the PU device, and making at least a writable area of the RAM unit writable to copy at least a part of the program of the external storage device; A second function of executing write-protected areas of the RAM unit and executing programs copied to the RAM unit. 7. The CPU device according to claim 2, wherein
A first function of having an external storage device storing a program executable by the PU device, and making at least a writable area of the RAM unit writable to copy at least a part of the program of the external storage device; A second function of executing a program copied to the RAM unit by writing-protecting a write-protectable area of the RAM unit, and a program copied to the RAM unit when notified that the program is illegal. A third function of specifying a module that has output the write instruction from among the modules and outputting the specified module. 8. The information processing apparatus according to claim 6, wherein the external storage device is a ROM. 9. A printing apparatus, comprising: the information processing apparatus according to claim 6; and a printing mechanism that prints print data processed by the CPU device. 10. An R which can set a write-protectable area.
A method for controlling an information processing device having a CPU device having a built-in AM and an external storage device storing a program executable by the CPU device, comprising: A first step of copying at least a part of a program of the storage device; and a second step of executing a program copied to the RAM by writing-protecting a write-protectable area of the RAM. Control method for an information processing apparatus. 11. The method according to claim 10, wherein in the second step, when there is a write instruction for an address of a write-protected area from the program copied to the RAM,
A method for controlling an information processing apparatus, wherein a module that has output a write instruction is specified and output from modules of a program copied to the RAM. 12. An R which can set a write-protectable area.
A first process of making a writable area of the RAM of a CPU device having a built-in AM writable and copying at least a part of the program from an external storage device storing a program executable by the CPU device; A setting program having an instruction capable of executing a second process of executing a program copied to the RAM with a write-protected area of the RAM being write-protected; Readable recording medium.