JP4976060B2 - Spread spectrum clock generator - Google Patents

Description

  The present invention relates to a spread spectrum clock generator that generates a spread spectrum clock whose frequency varies periodically from a constant frequency clock.

  2. Description of the Related Art In recent years, with increasing speed and density of electronic devices, electromagnetic noise (EMI (Electro Magnetic Interference) noise) radiated from the electronic devices tends to increase.

  Here, a spread spectrum clock generator (SSCG) is known as means for suppressing electromagnetic wave noise. Spread spectrum refers to periodically changing the frequency of a basic clock generated by a crystal resonator or the like with a predetermined profile (referred to as a frequency modulation profile). Since the frequency of the electromagnetic noise is dispersed by this, the peak level of the electromagnetic noise can be kept small.

As a spread spectrum clock generator system, there are an analog system using a PLL (Phase Locked Loop) circuit and a digital system using a delay circuit (delay line). Here, as a digital spread spectrum clock generator, a delay circuit that delays an input clock signal by a different delay time and outputs a clock signal delayed by a different delay time, and a clock signal output from the delay circuit There has been proposed a spread spectrum clock generator including a selector for selecting a signal and a control circuit for supplying a bit output signal of a combination that makes a round in a predetermined cycle to the selector (see Patent Document 1). According to this spread spectrum clock generator, the period of the output clock signal selected by the selector and sequentially output increases or decreases corresponding to the combination of the bit output signals. For this reason, the frequency of the output clock signal fluctuates. Therefore, the frequency of the electromagnetic wave noise is dispersed, and the peak level of the electromagnetic wave noise can be kept small.
International Publication No. WO00 / 45246 Pamphlet

  The conventional digital spread spectrum clock generator realizes frequency modulation in which the frequency is periodically varied from a constant frequency clock by dynamically switching the number of delay line stages. The longer the frequency modulation period, the larger the required delay line size (circuit scale). In other words, a mechanism that digitally calculates how much time to delay in order to obtain a desired frequency modulation profile for each input clock period, and adjusts the length of the delay line based on the result is adopted. The For this reason, if the necessary accumulated delay increases, the number of delay stages also increases accordingly.

  In other words, the number of required delay stages increases if a slow frequency modulation or a large modulation degree is to be realized. In a typical digital spread spectrum clock generator, the required maximum delay time is as long as five cycles of the input clock. Further, since the delay time depends on PVT (Process (process) / Voltage (power supply voltage) / Temperature (temperature)), the degree of modulation necessarily has a condition dependency. Therefore, it is difficult to perform frequency modulation with high accuracy.

  In view of the above circumstances, an object of the present invention is to provide a spread spectrum clock generator capable of accurately performing frequency modulation while suppressing an increase in circuit scale.

The spread spectrum clock generator of the present invention that achieves the above object is
A plurality of first delay elements that change the delay amount in accordance with the applied voltage are connected in series, and a plurality of first delay elements sequentially delay the input clock to generate a plurality of phase clocks. A first modulation unit that generates a first modulation clock in which the input clock is modulated by selecting a desired clock from among the plurality of phase clocks in a switchable manner;
A plurality of second delay elements that change the delay amount according to the applied voltage are connected in parallel, and a second delay circuit that delays the first modulation clock is provided. A second modulation unit that generates a second modulation clock delayed by the second delay element by selecting any one of the second delay elements;
Delay for generating a delay amount adjusting voltage and applying the voltage to a plurality of first delay elements arranged in the first delay circuit and a plurality of second delay elements arranged in the second delay circuit And a quantity control unit.

  The spread spectrum clock generator of the present invention is capable of switching a desired clock among a plurality of phase clocks generated by sequentially delaying an input clock with a plurality of first delay elements connected in series. Then, a first modulation unit (coarse modulation unit) for generating a first modulation clock (coarse modulation clock) obtained by modulating the input clock is provided. For this reason, even if the delay time of each of the plurality of clocks is within one clock, an infinite cumulative delay can be realized by selecting and combining them. Therefore, if the necessary accumulated delay increases, the circuit scale can be reduced as compared with the spread spectrum clock generator in which the number of delay stages increases accordingly.

  In the spread spectrum clock generator of the present invention, the first modulation clock generated by the first modulation unit may be the second one of the plurality of second delay elements connected in parallel. A second modulation unit (fine modulation unit) that generates a second modulation clock (fine modulation clock) delayed by the second delay element by selecting the delay element is provided. For this reason, frequency modulation with a small delay amount can be realized.

  Further, the spread spectrum clock generator of the present invention generates the first modulation clock and the second modulation clock according to the applied voltage for adjusting the delay amount. For this reason, even when the delay amount required for realizing the frequency modulation varies due to the variation of the frequency of the input clock or PVT, an applied voltage corresponding to the variation is generated, The delay amount between the clocks of a plurality of phases also changes by the amount of the change, and the change in the frequency of the input clock and the dependence on the modulation degree due to the PVT can be suppressed to a low level. Therefore, according to the spread spectrum clock generator of the present invention, it is possible to accurately perform frequency modulation while suppressing an increase in circuit scale.

Here, the first modulation unit further includes a first clock for generating a rising edge and a second clock for generating a falling edge from among a plurality of phase clocks generated by the first delay circuit. A first selector that switches between the first clock and an edge detector that detects the edge of the first clock and the edge of the second clock and generates the first modulated clock modulated in the time axis direction; With
The second modulation unit includes a second selector that outputs the second modulation clock by selecting a desired clock from the plurality of clocks output from the plurality of second delay elements. It is preferable that

  In this way, the first modulation clock and the second modulation clock can be easily generated, as shown in an embodiment described later.

  According to the spread spectrum clock generator of the present invention, it is possible to accurately perform frequency modulation while suppressing an increase in circuit scale.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 is a diagram illustrating a circuit configuration of a spread spectrum clock generator according to an embodiment of the present invention. FIG. 2 is a configuration of a VCDL (Voltage Control Delay Line) of the spread spectrum clock generator illustrated in FIG. FIG.

  A spread spectrum clock generator 10 shown in FIG. 1 includes a VCDL 1000, a first selector 120, an edge detector 130, a fine modulation unit 200 (corresponding to an example of a second modulation unit in the present invention), an arithmetic circuit 400 is provided.

  As shown in FIG. 2, the VCDL 1000 includes a delay amount control unit 300 including a PFD (Phase Frequency Detector: phase / frequency detection circuit) 310 and an LPF (Low Pass Filter: low pass filter) 320, and a coarse modulation unit 100 (this A coarse delay circuit 110 (corresponding to an example of the first delay circuit according to the present invention) is provided. In the coarse delay circuit 110, first delay elements 110_1, 110_2, 110_3,..., 110_30, 110_31, 110_32 that change a delay amount according to an applied voltage Vcont described later are connected in series, and are input at a constant frequency. Are sequentially delayed by the first delay elements 110_1, 110_2, 110_3,..., 110_30, 110_31, 110_32, so that the 32-phase clocks CK1, CK2, CK3,. Is generated.

  The coarse modulation unit 100 includes the coarse delay circuit 110 described above, the first selector 120 and the edge detector 130 also shown in FIG.

  The first selector 120 selects a coarse modulation clock CKC (first modulation clock according to the present invention) from the 32 phase clocks CK1, CK2, CK3,... CK30, CK31, CK32 generated by the coarse delay circuit 110. The first clock CKA for generating the rising edge and the second clock CKB for generating the falling edge for generating the second edge are generated in a switchable manner.

  For example, if the period of the input clock CLKIN is 9.6 ns, the phase difference between the 32-phase clocks CK1, CK2, CK3,... CK30, CK31, CK32 is 300 ps. If you want to create a clock that is just 300 ps longer (ie, 9.6 ns + 300 ps = 9.9 ns cycle), the first selector 120 selects a clock that is delayed by one phase every clock. I'll do it. That is, in FIG. 2, the clock is selected in the order of CK1 → CK2 → CK3 → CK4 →. Note that implementation examples of clocks with various periods will be described later.

  The edge detector 130 detects the rising edge of the first clock CKA and the rising edge of the second clock CKB, and generates a coarse modulation clock CKC modulated in the time axis direction. The configuration of the edge detector 130 will be described later.

  Next, the PFD 310 and the LPF 320 constituting the delay amount control unit 300 will be described.

  An input clock CLKIN having a constant frequency is input to the PFD 310 from the outside. Further, the delay clock CKDLY from the coarse delay circuit 110 is also input to the PFD 310. The PFD 310 compares the frequency and phase of the input clock CLKIN and the delayed clock CKDLY, and outputs a voltage level signal corresponding to the error signal of the frequency and phase. This signal is input to the LPF 320. The LPF 320 converts the input signal into a DC level voltage Vcont. This voltage Vcont is applied to the control terminals of the first delay elements 110_1, 110_2, 110_3,..., 110_30, 110_31, 110_32 constituting the coarse delay circuit 110. The voltage Vcont is also applied to the fine modulation unit 200 described later.

  Here, the principle of generating a frequency-modulated output clock by switching the multiphase clock will be described with reference to FIG.

  FIG. 3 is a diagram for explaining the principle of generating a frequency-modulated output clock.

  Here, in order to simplify the explanation, an example of 10-phase clocks CK1,.

  As shown in FIG. 3, the rise of the pulses constituting the output clock OUT is determined by the rise timing of the clocks CK1, CK2, CK4, CK7, CK10, CK4 (14), CK9 (19), and CK5 (25). . Further, the falling edge of the pulse constituting the output clock OUT is determined by the falling timing of the clocks CK6, CK7, CK9, CK2 (12), CK5 (15), CK9 (19), and CK4 (24). By doing so, it is possible to generate the output clock OUT subjected to frequency modulation.

  As can be seen from FIG. 3, even when the delay times of the clocks CK1,..., CK10 are within one clock, an infinite cumulative delay is ideally realized by selecting and combining them. I understand that it is possible. Here, the clock switching timing and the calculation speed, which should be noted in this implementation, will be described. First, clock switching timing will be described with reference to FIG.

  FIG. 4 is a diagram illustrating clock switching timing.

  In FIG. 4, the first selector 120 changes the CKA of the first selector 120 from CKα that is one of the 32-phase clocks of the VCDL 1000 to CKβ that is the other of the 32-phase clocks of the VCDL 1000. It shows how it is switched by.

  In the spread spectrum clock generator 10 of this embodiment, the maximum value of delay switching is at most several percent of the period of the input clock CLKIN. That is, the phase difference between the clock CKα and the clock CKβ in FIG. Here, when the CKA of the first selector 120 is switched from the clock α to the clock β, the switching is simply performed at the timing immediately after the rising of the clock CKα, as shown in FIG. 4, the transfer from CKα to CKβ. May be too early, in which case a small pulse (whisker) is generated. Therefore, by setting the timing of CKA switching by the first selector 120 to the rising edge of XNOR of CKα and CKβ, for example, a clock in which the transfer from CKα to CKβ is normally performed as shown in FIG. 4 can be obtained. . Note that a delay may be simply added to the phase change timing.

  Next, the calculation speed in the spread spectrum clock generator 10 of this embodiment will be described. When the calculation is complicated, there is a problem that the calculation speed is reduced. However, in the spread spectrum clock generator 10 of the present embodiment, since the phase to be selected is 32 phases, no problem occurs. That is, since the lower 5 bits of the calculation result performed by the conventional spread spectrum clock generator can be used as a select signal as it is, the calculation complexity is exactly the same, and there is no restriction on the speed related to the calculation.

  FIG. 5 is a diagram showing a circuit configuration of the edge detector.

  The edge detector 130 shown in FIG. 5 includes a first flip-flop 131, a second flip-flop 132, and an exclusive OR gate 133.

  The input terminal D of the first flip-flop 131 is connected to the inverting output terminal QB of the second flip-flop 132. The output terminal Q of the first flip-flop 131 is connected to the input terminal D of the second flip-flop 132 and to one input terminal of the exclusive OR gate 133. Further, the output terminal Q of the second flip-flop 132 is connected to the other input terminal of the exclusive OR gate 133. The first clock CKA is input from the first selector 120 to the clock terminal of the first flip-flop 131, and the clock terminal of the second flip-flop 132 is input from the first selector 120 to the first clock CKA. Two clocks CKB are input.

  In the edge detector 130 configured as described above, a coarse modulation clock CKC, which is one output clock, is generated from the two input first and second clocks CKA and CKB as described below.

  It is assumed that both the output terminals Q of the first and second flip-flops 131 and 132 are at the “L” level at the first time point. Since the 'L' level is input to both the input terminals of the exclusive OR gate 133, the coarse modulation clock CKC output from the exclusive OR gate 133 is at the 'L' level.

  Here, when the first clock CKA rises, the input terminal D of the first flip-flop 131 is inputted with the “H” level from the inverting output terminal QB of the second flip-flop 132, so The “H” level is output from the output terminal Q of one flip-flop 131. Since the 'H' level is input to one input terminal of the exclusive OR gate 133, the coarse modulation clock CKC output from the exclusive OR gate 133 changes to the 'H' level. In this way, when the first clock CKA rises, the coarse modulation clock CKC rises.

  Next, the second clock CKB rises. Here, since the “H” level from the output terminal Q of the first flip-flop 131 is input to the input terminal D of the second flip-flop 132, the output terminal Q of the second flip-flop 132 is used. Outputs an “H” level. Since this “H” level is input to the other input terminal of the exclusive OR gate 133, the “H” level is input to both the exclusive OR gate 133, and therefore, is output from the exclusive OR gate 133. The coarse modulation clock CKC changes from “H” level to “L”. In this way, when the second clock CKB rises, the coarse modulation clock CKC falls. In order to guarantee the duty of the coarse modulation clock CCK, the first clock CKA and the second clock CKB have a phase difference of 180 degrees. The rising edges of these two first and third clocks CKA and CKB are alternately performed once each.

  As long as CKA and CKB rise alternately one time in this way, regardless of the initial state of the output terminals Q of the first and second flip-flops 131 and 132, CKA raises the rising edge of the coarse modulation clock CCK. Determines the falling edge of the coarse modulation clock CKC.

  Next, the fine modulation unit 200 will be described with reference to FIG.

  FIG. 6 is a diagram illustrating a circuit configuration of the fine modulation unit.

  The fine modulation unit 200 shown in FIG. 6 includes a fine delay circuit 210 (corresponding to an example of the second delay circuit in the present invention) and a second selector 220.

  The fine delay circuit 210 receives a coarse modulation clock CKC in which second delay elements 210_1, 210_2, 210_3, 210_4, and 210_5 that change the delay amount according to the applied voltage Vcont from the LPF 320 shown in FIG. This is a delay circuit for delaying. Each delay element 210_1, 210_2, 210_3, 210_4, and 210_5 has a delay value of 180 ps, 240 ps, 300 ps, 360 ps, and 420 ps. Which one of the second delay elements 210_1, 210_2, 210_3, 210_4, and 210_5 is used is selected by the second selector 220 that receives an instruction from the arithmetic circuit 400. For example, when the delay element 210_3 is used, a delay amount of −60 ps is relatively added by switching to the delay element 210_2. Conversely, if the delay element 210_4 is switched, a delay amount of 60 ps is relatively added. become. That is, in the fine modulation unit 200, the minimum delay amount adjustment is 60 ps. Further, even when the frequency of the input clock CLKIN inputted from the outside to the spread spectrum clock generator 10 shown in FIG. 1 is changed, the delay value from the LPF 320 is changed in proportion to the change. The delay values of the second delay elements 210_1, 210_2, 210_3, 210_4, and 210_5 are adjusted by the voltage Vcont.

  The arithmetic circuit 400 (see FIGS. 1 and 2) includes a selector switching table for determining a phase for periodically changing the frequency from an input clock CLKIN having a constant frequency input from the outside. .

  Here, how to generate a fine modulation clock CLKOUT (corresponding to an example of the second modulation clock in the present invention) having various cycles (here, a cycle adjustable in increments of 60 ps) is shown. Description will be made with reference to Table 1, Table 2 and Table 3.

  Table 1 shows a selector switching table necessary for extending the period T (9.6 ns) of the input clock CLKIN by 60 ps. Specifically, this is a table for realizing the period T = 9.66 ns (9.6 ns + 60 ps) of the input clock CLKIN with respect to the first clock CKA.

  In the upper part of the switching table shown in Table 1, CK1, CK2, and CK3 selected from the 32-phase clocks output from the coarse delay circuit 110 constituting the VCDL 1000 are shown. In the lower stage, second delay elements 210_1, 210_2, 210_3, 210_4, and 210_5 in the fine modulation unit 200 (Fine Delay) are shown. Here, for the sake of convenience, the second delay elements 210_1, 210_2, 210_3, 210_4, and 210_5 are denoted by reference numerals (A), (B), (C), (D), and (E).

  The clock CK is selected from the 32-phase clocks output from the VCDL, and is switched in the order of (A), (B), (C), (D), (E). When it comes to ((E)), this time, the switching of the multi-phase of VCDL (switching from CK1 to CK2) is performed in the way of the quinary system. In this way, the period T = 9.66 ns of the input clock CLKIN with respect to the first clock CKA is realized.

  The realization of the period T = 9.66 ns of the input clock CLKIN with respect to the second clock CKB will be described with reference to Table 2.

  Table 2 is a table for realizing the period T = 9.66 ns of the input clock CLKIN with respect to the second clock CKB.

  As is clear from comparison with Table 1, the second clock CKB is advanced 180 degrees (for 16 phases in VCDL) from the first clock CKA.

  The clock CK17 of the 32-phase clocks output from the VCDL is selected and switched in the order of (A), (B), (C), (D), (E), and fine adjustment settings are completed. When it comes to ((E)), this time, the switching of the multi-phase of VCDL (switching from CK17 to CK18) is performed in the way of the quinary system. In this way, the period T = 9.66 ns of the input clock CLKIN with respect to the second clock CKB is realized.

  Hereinafter, the second clock CKB is shown as being advanced by 16 phases of the first clock CKA, and only the table for the first clock CKA is shown.

  Table 3 is a selector switching table necessary to increase the period T (9.6 ns) of the input clock CLKIN by 240 ps.

  Table 3 shows that the input clock CLKIN is switched by selecting (E) for the selection of the clock CK1 output from the VCDL and selecting (D) for the selection of the clock CK2. Period T = 9.84 ns (9.6 ns + 240 ps). In this way, the fine modulation clock CLKOUT having various cycles can be generated in increments of 60 ps.

  In the present embodiment, an example in which a 32-phase clock and five second delay elements are provided has been described. However, the present invention is not limited to this, and the present invention is not limited to this. Any delay element may be used. Of course, if the frequency of the input clock CLKIN changes, the delay amount between the multiphase clocks also changes continuously.

It is a figure which shows the circuit structure of the spread spectrum clock generator of one Embodiment of this invention. It is a figure which shows the circuit structure containing the structure of VCDL of the spread spectrum clock generator shown in FIG. It is a figure for demonstrating the principle which produces | generates the frequency-modulated output clock. It is a figure which shows the switching timing of a clock. It is a figure which shows the circuit structure of an edge detector. It is a figure which shows the circuit structure of a fine modulation part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Spread spectrum clock generator 100 Coarse modulation part 110 Coarse delay circuit 110_1,110_2,110_3, ..., 110_30,110_31,110_32 1st delay element 120 1st selector 130 Edge detector 131 1st flip-flop 132 2nd flip-flop 133 Exclusive OR gate 200 Fine modulation unit 210 Fine delay circuit 210_1, 210_2, 210_3, 210_4, 210_5 Second delay element 220 Second selector 300 Delay amount control unit 310 PFD
320 LPF
400 arithmetic circuit 1000 VCDL

Claims (2)

A plurality of first delay elements that change the delay amount according to the applied voltage are connected in series, and a first clock is generated by sequentially delaying an input clock by the plurality of first delay elements. A first modulation unit that generates a first modulation clock obtained by modulating the input clock by selecting a desired clock from the plurality of phase clocks so as to be switchable;
A plurality of second delay elements that change the delay amount in accordance with the applied voltage, and a second delay circuit that delays the first modulation clock is connected in parallel; A second modulation unit that generates a second modulation clock delayed by the second delay element by selecting any one of the second delay elements;
Delay for generating a voltage for adjusting a delay amount and applying the voltage to a plurality of first delay elements arranged in the first delay circuit and a plurality of second delay elements arranged in the second delay circuit A spread spectrum clock generator comprising a quantity control unit. The first modulation unit can further switch between a first clock for generating a rising edge and a second clock for generating a falling edge from among a plurality of clocks generated by the first delay circuit. A first selector that selects the edge of the first clock and an edge detector that detects the edge of the first clock and the edge of the second clock to generate the first modulated clock modulated in the time axis direction,
The second modulation unit includes a second selector that outputs the second modulation clock by selecting a desired clock among a plurality of clocks output from the plurality of second delay elements. The spread spectrum clock generator according to claim 1.

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