JP2573787B2 - Pulse width modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to various electric circuits,
Those related to Rupa pulse width modulation circuits are used in electrical equipment.

[0002]

2. Description of the Related Art FIG. 6 shows a PLL (Phase Locked Loop) circuit which is an example of a circuit conventionally used for generating a control signal. In the figure, reference numeral 121 denotes an input clock and this PLL
A phase difference detection circuit for detecting a phase difference from the output clock of the circuit; a phase difference voltage conversion circuit for converting the phase difference detected by the phase difference detection circuit into a voltage corresponding to the phase difference; This is a voltage controlled oscillation circuit whose oscillation frequency changes according to the voltage converted by the voltage conversion circuit 122.

Next, the operation will be described. The input clock input to the phase difference detection circuit 121 is compared with the output clock of the present PLL circuit to detect the phase difference. A signal corresponding to the phase difference detected by the phase difference detection circuit 121 is input to the phase difference voltage conversion circuit 122, converted into a voltage corresponding to the phase difference, and input to the voltage control oscillation circuit 123. The voltage controlled oscillation circuit 123 oscillates at an oscillation frequency corresponding to the input voltage, and the oscillation signal is output to the outside as an output clock of the present PLL circuit.

With such a configuration, a PLL circuit that detects a phase difference between input and output so that the frequency and phase of the voltage controlled oscillator matches the frequency and phase of the input clock and performs feedback control is a known technique. , For controlling a single frequency.

FIG. 7 shows a pulse width modulation (PW) as an example of a conventional delay control circuit constituted by a digital circuit.
M) circuit, and 131, 132, 13
Reference numerals 3,..., 13N denote D flip-flops which delay the input signal by one clock in synchronism with the clock signal. A clock signal having a frequency equal to or greater than the required time resolution is input, and a signal delayed by one clock is output from the Q output. The Q output of the D flip-flop 131 is input to the D input of the D flip-flop 132,
The same clock signal as that input to the D flip-flop 131 is input to the input, and 1 is output from the Q output.
A signal delayed by the clock is output. Hereinafter, similarly, D flip-flops are connected in series with each other, and the D input of the D flip-flop 13N is connected to the D flip-flop 13N-
1 is input to the D flip-flop 13
A PWM signal can be generated by a combination logic of Q outputs 1 to 13N.

Next, the operation will be described. The input signal is D
The signal is input to the flip-flop 131, delayed by one clock of the clock signal by the D flip-flop 131, and output to the D flip-flop 132. The output signal of the D flip-flop 131 is delayed by one clock of the clock signal by the D flip-flop 132 and output to the D flip-flop 133, similarly to the D flip-flop 131. In the same manner, the delay amount increases by one clock signal each time the signal passes through the D flip-flop one stage at a time.
3N outputs a signal whose input signal is delayed by the same number of clocks as the number of D flip-flops 131 to 13N connected in series.

FIG. 8 shows an example of a conventional delay control circuit constituted by an analog circuit, which can be constituted by using a ramp circuit and a voltage comparator. In the figure, 141
Is a ramp circuit for generating a ramp waveform, which is a constant current circuit 1411 for generating a constant current and a constant current circuit 1411 for generating a constant current.
11 comprises a capacitor 1412 connected between a constant current node outputting a constant current and a ground node. 1
42, a ramp waveform signal output from a connection node between the constant current circuit 1411 and the capacitor 1412 of the ramp circuit 141 is input to its non-inverting input terminal, and the set voltage VR is input to its inverting input terminal. This is a voltage comparator for comparing the voltage with the set voltage VR.

Next, the operation will be described. Lamp circuit 1
As shown in FIG. 9 , the ramp waveform signal generated by the ramp 41 has a voltage value which rises linearly with time, and while the ramp waveform signal is lower than the set voltage VR, the output of the voltage comparator 142 is low level ( = 0V), and when this ramp waveform signal exceeds the set voltage VR, the output of the voltage comparator 142 is inverted from a low level to a high level (= 5V). Therefore, the capacitor 1412
, The time until the output Vout of the voltage comparator 142 is inverted can be changed.

[0009]

The conventional control signal generating circuit is configured as described above, and the PLL circuit of FIG. 6 can be used only for the purpose of adjusting a single frequency.

In the PWM circuit shown in FIG. 7 , the pulse width is determined by the number of delay elements, so that the circuit is not flexible and a very high frequency clock is required to satisfy a desired time resolution. For example, in order to achieve a resolution of 0.1 nanosecond, a clock several times higher than 10 GHz is required. Therefore, there is a problem that it is not practical to achieve high resolution.

In addition, the analog circuit shown in FIG. 8 has a problem that it is difficult to increase the resolution due to variations in element values and temperature fluctuation peculiar to the analog circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and does not require a clock having a very high frequency and can stably generate a control signal having a high time resolution. and to obtain a pulse width modulation circuits having a generator.

[0013]

A pulse width according to the present invention
The modulation circuit includes a clock signal generation circuit and a clock signal generation circuit.
Multiple delay elements in series that delay the phase according to the control voltage
And stage connection, enter the clock <br/> click signal generated by the clock signal generation circuit to the first-stage delay element, out of the delay elements of each stage
Phase difference detection and delay circuit so as to take out each force as a delay signal, the phase difference between the clock signal output delay signal output from the delay elements of the last stage of the delay circuit from the clock signal generating circuit A detection circuit, and a phase difference signal output from the phase difference detection circuit to the phase difference.
Into a corresponding voltage, and use this voltage as a control voltage as described above.
A phase difference voltage converting circuit for output to the delay element of each stage of the extending circuit, based on an external control signal, each of the delay circuit
From each delay signal output from the delay element of the stage,
Separately, the two delay signals are divided into a first selection signal and a second selection signal.
An output selection circuit for selecting at least one set as a selection signal ;
When the first selection signal is input, the level becomes high,
When the second selection signal is input, the signal is set to a low level.
And a pulse width modulation signal generating circuit for outputting a pulse width modulation signal .

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

In the pulse width modulation circuit according to the present invention, the clock signal generation circuit and the phase of the clock signal are controlled.
Multiple delay elements connected in series with a delay depending on the control voltage
And inputs the clock signal generated by the clock signal generation circuit to the first-stage delay element, slow the output of the delay element of each stage
A delay circuit for extracting each as an extended signal ,
A phase difference detection circuit for detecting a phase difference between a delay signal output from the delay element at the last stage of the delay circuit and the clock signal output from the clock signal generation circuit; and a phase output from the phase difference detection circuit. The phase difference signal is converted into a voltage corresponding to the phase difference, and the voltage is used as a control voltage in the delay circuit.
A phase difference voltage converting circuit for output to the delay element of each stage of, based on external control signals, for each stage of the delay circuit slow
From the delay signal output from the extension element, each independently
A first selection signal and a second selection signal are used as two delay signals.
An output selecting circuit for selecting at least one pair as said first
When the selection signal of 1 is input, the level becomes high, and the second
Pulse width so that it becomes low level when the selection signal of
Since a pulse width modulation signal generation circuit that outputs a modulation signal is provided , the same frequency as the input clock signal is used.
With any duty and any rising edge
A pulse width modulated signal having a position can be obtained.

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
Shows a control signal generation circuit in the pulse width modulation circuit according to one embodiment of the present invention. In the figure, reference numeral 1 denotes a delay circuit for delaying an input clock signal generated by a clock generation circuit (not shown). The delay circuit 1 outputs a signal delayed by the same amount from a plurality of taps taken out. The delay amount is controlled according to the delay amount control voltage from the circuit. Reference numeral 2 denotes a phase difference detection circuit for detecting a phase difference between the input clock signal and the signal delayed by the maximum amount by the delay circuit 1, and 3 denotes a phase difference detected by the phase difference detection circuit 2 to a voltage corresponding thereto. The phase difference voltage conversion circuit 4 for conversion is an output selection circuit that selects one of the outputs of the taps extracted from the delay circuit 1 and outputs it as a control signal to the outside.

FIG. 2 is a diagram showing a circuit configuration example of the delay circuit 1 and the output selection circuit 4 in FIG. 1. In the figure, the delay circuit 1 is composed of delay elements D1 to Dn connected in series with each other. Each of the delay elements D1 to Dn includes a buffer amplifier 11 to 1n for amplifying the input signal, transistors T1 to Tn and a capacitor connected in series between output nodes O1 to On of the buffer amplifiers 11 to 1n and a ground node. The delay amount control voltage from the phase difference voltage conversion circuit 3 of FIG. 1 is applied to the gates of the transistors T1 to Tn. The output selection circuit 4 includes a plurality of buffer amplifiers 41 to 4 having control terminals.
n, and the buffer amplifiers 41 to 4n
Are controlled by control signals G1 to Gn input to the control terminal so that only one of them can perform an amplifying operation.

Next, the operation of the control signal generation circuit will be described with reference to FIGS. First, the input clock input from the clock signal generation circuit is input to the delay circuit 1, and a signal whose delay amount is increased by a predetermined amount from the outputs O1 to On of the delay elements D1 to Dn is output from a plurality of taps. The delay signal output from the delay element Dn at the last stage of the delay circuit 1 is output from the tap similarly to the outputs of the other delay elements and is input to the phase difference detection circuit 2, and the phase difference detection circuit 2 The phase difference is detected by comparing the delay signal output from the delay element Dn at the last stage of the circuit 1 with the original input clock. The detection result is converted by the phase difference voltage conversion circuit 3 into a voltage corresponding to the phase difference, and this is applied to the delay circuit 1 as the delay amount control voltage. This delay amount control voltage is applied to the gates of the transistors T1 to Tn connected together with the capacitors C1 to Cn between the outputs of the buffer amplifiers 11 to 1n of each delay element and the ground. Thus, the opening degree of the transistors T1 to Tn is determined, whereby the time constant of the time constant circuit formed together with the capacitors C1 to Cn changes, and the delay amount can be controlled. The signal whose delay amount is controlled in this way is output from the plurality of taps of the delay circuit 1 to the output selection circuit 4.
By selecting which one of the control signals G1 to Gn of the selection circuit 4 is to be at a high level, which of the delay elements of the delay circuit 1 is to be selected is selected from the input signals. A delay time in which the delay amount is delayed can be obtained.

As described above, in the control signal generation circuit , the delay elements connected in series with each other constitute a delay circuit. The delay elements of the clock signal input to the delay circuit and the output clock signal from the last stage of the delay element Since the amount of delay is controlled so that the phases match, the delay signal output from each tap has a time resolution of (1 / the number of delay elements) of the cycle of the input clock signal. By selecting by a circuit, a control signal with this time resolution can be generated.

For example, when the input clock frequency is 20 MHz and the number of delay elements is 500, a signal having a resolution of 0.1 nanosecond can be obtained.

Therefore, it is possible to stably generate a control signal having a high time resolution without requiring a clock having a very high frequency.

[0043]

[0044]

[0045]

FIG. 3 shows a pulse width modulation circuit according to the present embodiment. In FIG. 3 , reference numeral 1 denotes a delay circuit for delaying an input clock signal generated by a clock generation circuit (not shown). A signal delayed by the same amount is output, and the delay amount is controlled according to the delay amount control voltage. 4 is the delay circuit 1
An output selecting circuit for selecting one of the tap outputs extracted from the plurality of taps and outputting the selected output as a control signal to the outside; and a pulse width modulation signal 6 based on the output signal selected by the output selecting circuit 4. Is a PWM signal generation circuit that generates Although not shown in FIG. 3, detects a phase difference between the output signal of the last stage of the input clock signal and the delay circuit 1 and similarly by the phase difference detecting circuit delay amount control voltage of the delay circuit 1 and FIG. 1 Are converted into voltage signals by a phase difference voltage conversion circuit.

Further, FIG. 4 is a diagram showing a circuit configuration example of the delay circuit 1 and the output selection circuit 4 in FIG. 3, in the drawing,
The delay circuit 1 includes delay elements D1 to D connected in series with each other.
2m, each of the delay elements D1 to D2m is a buffer amplifier 11 to 12m for amplifying the input signal,
Output nodes O1 to O of buffer amplifiers 11 to 12m
It is composed of transistors T1 to T2m and capacitors C1 to C2m connected in series between 2m and the ground node. A delay amount control voltage from a phase difference voltage conversion circuit (not shown) is applied to the gates of the transistors T1 to T2m. Is done. The output selection circuit 4 includes a plurality of buffer amplifiers 41 to 42 m and 411 to 412 m with control terminals.
And the buffer amplifiers 41 to 42 m
Is a control signal (external control signal) input to the control terminal G1
1 to G12m, and buffer amplifiers 411 to 41
2m is controlled by a control signal (external control signal) G21 to G22m so that only one of them can perform an amplifying operation. Further, the PWM signal generation circuit 6 includes an output selection circuit 4
Of the buffer amplifiers 41 to 4m are input to the set terminal S1 and the outputs of the buffer amplifiers 4m + 1 to 42m are input to the reset terminal R1, and the outputs of the buffer amplifiers 411 to 41m are input to the set terminal S2 and buffered. Flip-flop 62 in which outputs of amplifiers 41m + 1 to 412m are input to reset terminal R2
And a logical sum circuit 63 for outputting the logical sum of the outputs of the flip-flops 61 and 62 as a PWM signal output.

[0048] Next, the operation will be described with reference to FIGS. First, the input clock input from the clock signal generation circuit is input to the delay circuit 1 and each of the delay elements D1
A signal whose delay amount is increased by a predetermined amount from outputs O1 to O2m of D2m to D2m is output from a plurality of taps. The delay signal output from the delay element D2m at the last stage of the delay circuit 1 is output from the tap similarly to the outputs of the other delay elements and is input to a phase difference detection circuit (not shown). The phase difference is detected by comparing the delay signal output from the delay element Dn at the last stage of the circuit 1 with the original input clock. The detection result is converted into a voltage corresponding to the phase difference by a phase difference voltage conversion circuit (not shown), and this voltage is applied to the delay circuit 1 as a delay amount control voltage. This delay amount control voltage is applied to the gates of the transistors T1 to T2m connected together with the capacitors C1 to C2m between the outputs of the buffer amplifiers 11 to 12m of each delay element and the ground. Accordingly, the opening degree of the transistors T1 to T2m is determined, whereby the time constant of the time constant circuit formed together with the capacitors C1 to C2m changes, and the delay amount can be controlled. The signal whose delay amount is controlled in this way is input in parallel to the output selection circuit 4 from a plurality of taps of the delay circuit 1, and the control signal of the selection circuit 4 determines which delay element of the delay circuit 1 is to be selected for output. G1 to G2m
By selecting which one of the signals has a high level, it is possible to obtain a delay time obtained by delaying a required amount of delay from the input signal.

In this embodiment, the output selection circuit 4
Are input to a set input terminal S1 and a reset input terminal R1 of a flip-flop 61 included in the PWM signal generation circuit 6, respectively.
, The signal S1 is output to the output terminals O1 to Om of the delay circuit 1.
Is the control signal G1 of the output selection circuit 4.
The signal R1 is selected and input, one of the outputs of the output terminals Om + 1 to O2m of the delay circuit 1 is selected and input by the control signals G1m + 1 to G12m of the output selection circuit 4, and the signal S2 is delayed. One of the outputs of the output terminals O1 to Om of the circuit 1 is an output selection circuit 4
Are selected and input by the control signals G21 to G2m of
One of the outputs of the output terminals Om + 1 to O2m of the delay circuit 1 is the control signal G2m + of the output selection circuit 4.
1 to G22m.

The flip-flops 61 and 62 generate a high-level voltage when the signals S1 and S2 are input, and generate a low-level voltage when the signals R1 and R2 are input. Therefore, by selecting the output of the delay elements of the delay circuit 1 by the output selecting circuit 4, 5
As shown in (1), the pulse width of the PWM output can be obtained.

[0051]

[0052]

[0053]

[0054]

[0055]

[0056]

As described above, the pulse width according to the present invention is
According to the modulation circuit, the clock signal generation circuit and the clock
A delay element that delays the signal phase according to the control voltage is connected in series.
A plurality of stages connected to, enter the <br/> clock signal generated by the clock signal generating circuit in the first stage of the delay element, the delay element of each stage
A delay circuit configured to take out the outputs of the slaves as delay signals, and a position of a delay signal output from a delay element at the last stage of the delay circuit and a clock signal output from the clock signal generation circuit. a phase difference detecting circuit for detecting a phase difference, the phase difference signal outputted from the phase difference detecting circuit
Is converted to a voltage corresponding to the phase difference, and this voltage is used as the control voltage.
A phase difference voltage conversion circuit that outputs to each delay element of each stage of the delay circuit, and a delay signal output from each stage of the delay circuit based on an external control signal .
Each of the two delayed signals is separated into a first selection signal, and
An output selection circuit that selects at least one set as a second selection signal; and a high level when the first selection signal is input.
When the second selection signal is input, the level becomes low.
Pulse width modulated signal generator that outputs a pulse width modulated signal
Circuit, so that the input clock signal and
At the same frequency, having an arbitrary duty, and
Obtaining a pulse width modulated signal with a rising edge position
The can be either One stable pulse width modulated signal with a high time resolution
There is an effect that can be obtained .

[0057]

[0058]

[0059]

[0060]

[0061]

[0062]

[0063]

[0064]

[0065]

[0066]

[0067]

[Brief description of the drawings]

FIG. 1 shows a pulse width modulation circuit according to an embodiment of the present invention.
It is a block diagram showing a definitive control signal generating circuit.

FIG. 2 shows a pulse width modulation circuit according to an embodiment of the present invention.
It is a diagram showing a detailed configuration of an internal circuit of definitive control signal generating circuit.

FIG. 3 is a configuration diagram showing a pulse width modulation circuit according to one embodiment of the present invention.

[Figure 4] of the pulse width modulation circuit according to an embodiment of the present invention
It is a view to view a detailed configuration of the internal circuit.

[5] of the pulse width modulation circuit according to an embodiment of the present invention
An example of an operation waveform is shown to view.

FIG. 6 shows a PLL circuit as an example of a conventional control signal generation circuit.
It is a block diagram showing a road .

FIG. 7 shows an example of a PWM signal which is an example of a conventional control signal generation circuit.
It is a block diagram showing a road .

8 is an example of a conventional control signal generating circuits Analog
FIG. 2 is a configuration diagram illustrating a circuit .

9 is a view to view the operating waveforms of the circuit of Figure 8.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-141121 (JP, A) JP-A-3-289813 (JP, A) JP-A-4-910 (JP, A) JP-A-2- 296410 (JP, A) JP-A-4-192914 (JP, A)

Claims (1)

(57) [Claims] 1. A clock signal generating circuit, and a delay element for delaying a phase of a clock signal according to a control voltage.
A plurality of stages connecting the child in series, with the clock signal generating circuit
The generated clock signal is input to the first-stage delay element,
The output of each delay element as a delayed signal.
A delay circuit configured to detect a phase difference between a delay signal output from a delay element at a final stage of the delay circuit and a clock signal output from the clock signal generation circuit; the phase of the phase difference signal output from the circuit
Convert to a voltage corresponding to the difference, and use this voltage as the control voltage.
A phase difference voltage conversion circuit that outputs to each of the delay elements of the delay circuit, and a delay signal that is output from each of the delay elements of each of the delay circuits based on the external control signal. Two
Using the delay signal as a first selection signal and a second selection signal
When an output selection circuit for selecting at least one set and the first selection signal are input , the output selection circuit becomes high level.
When the second selection signal is input, the signal is set to a low level.
The pulse width modulation circuit, characterized in that a pulse width modulation signal generating circuit for outputting a pulse width modulated signal.