JP4971123B2 - Board design equipment - Google Patents

Description

  The present invention relates to a board design apparatus for designing a printed circuit board, and more particularly to a board design apparatus for automatically arranging bypass capacitors.

  In recent years, printed circuit board design including the placement of electronic components and printed circuit board wiring on a printed circuit board has been performed efficiently using a printed circuit board design CAD (Computer Aided Design) board design apparatus. ing. In recent years, EMC (Electro Magnetic Compatibility) countermeasure requirements for printed circuit boards have increased, and a board design apparatus capable of designing bypass capacitors on printed circuit boards in order to reduce electromagnetic noise. Has also been proposed.

For details of a conventional substrate design apparatus capable of designing a bypass capacitor on a substrate, see, for example, Patent Documents 1 to 4 below.
JP 2002-16337 A JP 2002-215708 A JP 2000-99560 A JP 2002-140382 A

  By the way, in order to reduce electromagnetic noise, a bypass capacitor is placed close to the power supply pin or ground pin of the electronic component on the printed circuit board, and the power supply pin or ground pin of the electronic component is connected to the bypass capacitor. It is necessary to shorten the wiring length as much as possible. However, in the above Patent Documents 1 to 4, although it is checked whether or not the wiring length formed on the printed circuit board is longer than a predetermined length, the power supply of the electronic component is used when the bypass capacitor is arranged. The positional relationship with the pin and the ground pin is not considered, and it is considered not sufficient from the viewpoint of reducing electromagnetic noise.

  In addition, the bypass capacitor is provided to remove noise superimposed on the power supply. From experience, a bypass capacitor is provided between a power supply pin of a certain electronic component and a power supply pattern provided to supply power to another electronic component. Need to be placed between. In other words, the order of connection must be the order of a power pin, a bypass capacitor, and a power supply pattern of a certain electronic component. However, in Patent Documents 1 to 4 described above, since there was no function for checking the connection order, the noise superimposed on the power supply is diffused through the power supply pattern without being removed by the bypass capacitor. There was a possibility of increasing.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a board designing apparatus capable of automatically arranging a bypass capacitor capable of reducing electromagnetic noise.

In order to solve the above-described problems, a board design apparatus according to the present invention includes a board design apparatus (1) that automatically places a bypass capacitor using board data (D1) that is design information of a printed board. An extraction unit (33) for extracting data related to the electronic component placed on the printed circuit board, and a pin for associating the power supply pin and the ground pin of the electronic component using the data related to the electronic component extracted by the extraction unit Between the association unit (34) and the power supply pin and the ground pin associated by the pin association unit, the rats nest extending from the bypass capacitor to be arranged on the printed circuit board to the power supply pin and the ground pin is the shortest. A position calculation unit (35) for calculating a position to be set, and a situation around the position calculated by the position calculation unit A position determination unit (36) for changing the position of the bypass capacitor and determining a position where the current path between the power supply pin and the ground pin and the bypass capacitor is shortest as a position where the bypass capacitor is to be disposed; It is characterized by comprising.
According to the present invention, data on an electronic component arranged on a printed circuit board is extracted from the board data, and the paired power supply pin and the ground pin are paired using the extracted data. The position where the rats nest is minimized is calculated between the ground pin and the current path between the power supply pin and the ground pin and the bypass capacitor is bypassed according to the situation around the calculated position. The position where the capacitor is to be placed is changed.
Further, in the board designing apparatus of the present invention, the pin associating unit includes a pin name assigned to the power supply pin and the ground pin, coordinate information of the power supply pin and the ground pin on the printed circuit board, or a user. The power supply pin and the ground pin are associated with each other based on designated association information.
The board designing apparatus of the present invention includes at least a power supply pin and a ground pin of the electronic component and a display unit (13) for displaying a position on the printed board of the bypass capacitor whose position is determined by the position determining unit. It is characterized by that.
In the board designing apparatus of the present invention, when the position determining unit includes a signal pin whose wiring is limited around the power pin and the ground pin associated by the pin associating unit, The position of the bypass capacitor is determined at a position where the wiring drawing from the pin is not hindered.
Further, the board designing apparatus of the present invention includes a bypass capacitor whose position is determined by the position determination unit, a power supply pin and a ground pin of the electronic component, and a connection order of power supply patterns for supplying power to other electronic components. Is provided with a confirmation unit (38) for confirming whether or not the connection order is defined in advance.
Further, in the board designing apparatus of the present invention, the confirmation unit determines the voltage drop of the wiring to which the power supply pin of the electronic component and the bypass capacitor are connected, the physical characteristics of the wiring and the time change of the current flowing through the wiring. It is characterized in that it is obtained using a rate and whether or not the voltage drop exceeds a preset value (D2).

  According to the present invention, data on an electronic component arranged on a printed circuit board is extracted from board data, and the power supply pin and ground focus of the electronic component are paired using the extracted data, and the paired power supply pin and ground Calculate the position where the rats nest is shortest between the pin and the bypass capacitor so that the current path between the power supply pin and the ground pin and the bypass capacitor becomes the shortest according to the situation around the calculated position. The bypass capacitor is automatically set to a position that takes into account not only the length of the wiring to the electronic component but also the relative positional relationship between the power supply pin and the ground pin of the electronic component. As a result, the electromagnetic noise can be further reduced.

  Hereinafter, a substrate design apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a main configuration of a substrate design apparatus according to an embodiment of the present invention. As shown in FIG. 1, the board design apparatus 1 of the present embodiment includes a design apparatus main body 11, an input device 12, and a display device 13 (display unit), and according to instructions from the user via the input device 12. The design device main body 11 designs a printed circuit board and displays the result on the display device 13 as appropriate.

  The design apparatus main body 11 includes a CPU (Central Processing Unit) 21, a RAM 22, and a hard disk 23. The CPU 21 designs a printed circuit board according to a user instruction via the input device 12 according to various programs (not shown) stored in the hard disk 23. Specifically, the CPU 21 reads out various programs stored in the hard disk 23, so that a component placement correction unit 31, a wiring placement correction unit 32, a component extraction unit 33 (extraction unit), and a pairing unit 34 ( A pin association unit), a position calculation unit 35, a position determination unit 36, a wiring correction unit 37, and a check unit 38 (confirmation unit) are realized, and these cooperate to design a printed circuit board.

  The component arrangement correcting unit 31 arranges an electronic component such as an IC (Integrated Circuit) on a printed circuit board and an electronic component already arranged on the printed circuit board according to the operation of the input device 12 by the user. Correct the position. The wiring arrangement correction unit 32 performs arrangement of wirings formed on the printed circuit board, correction of wirings already arranged on the printed circuit board, and the like according to the operation of the input device 12 by the user.

  The component extraction unit 33 reads the board data D1 created by the user and recorded on the hard disk 23, and extracts data related to the electronic components arranged on the printed board from the board data D1. The data extracted here includes, for example, data indicating the types of electronic components and wiring, data indicating the positions of electronic components and wiring on a printed circuit board, data indicating the types and positions of pins of electronic components, and the like. Can be mentioned.

  The pairing unit 34 associates (pairs) the power supply pin and the ground pin of the electronic component using the data regarding the electronic component extracted by the component extraction unit 33. Here, the pairing unit 34 is, for example, a pin name given to the power supply pin and the ground pin of the electronic component, a coordinate value on the printed circuit board of the power supply pin and the ground pin of the electronic component, or a correspondence specified by the user The power supply pin and the ground pin are paired based on information or the like.

  FIG. 2 is a diagram illustrating an example of pairing between a power supply pin and a ground pin. FIG. 2A is a diagram illustrating an example of pairing in the case of a QFP (Quad Flat Package) type electronic component, and FIG. These are figures which show the example of pairing in the case of a BGA (Ball Grid Array) type electronic component. Here, pairing is performed based on the coordinate values of the power supply pins and the ground pins on the printed circuit board. In FIG. 2, the rectangular region with the symbol “V” is a land to which the power pin of the electronic component is connected, and the rectangular region with the symbol “G” is a land to which the ground pin of the electronic component is connected. The rectangular area without the symbol indicates each land to which the signal pin of the electronic component is connected.

  In the case of a QFP type electronic component, the power supply pin and the ground pin are often arranged close to each other. For this reason, the pairing unit 34 performs pairing between the power supply pin and the closest ground pin, as indicated by reference numeral P1 in FIG. On the other hand, in the case of BGA type electronic components, a plurality of power pins are often arranged around a plurality of ground pins. Therefore, as shown in FIG. 2B with the reference symbol P2, the pairing unit 34 prioritizes the pairing between the power supply pin and the closest ground pin, and when the closest ground pin is insufficient, Pair with the ground pin located at the closest distance.

  Here, in order to simplify the description, a case where a power supply pin and a ground pin are paired on a one-to-one basis is taken as an example. However, a plurality of power supply pins may be paired with one ground pin, and conversely, a plurality of ground pins may be paired with one power supply pin. In addition, when performing pairing using the pin names attached to the power supply pins and the ground pins of the electronic component, the pairing unit 34 has the same or similar power supply pins and ground pins with the same names. Is extracted and paired, and when the association information designated by the user is used, the power supply pin and the ground pin are paired according to the association information.

  The position calculation unit 35 calculates the position of the bypass capacitor between the power supply pin and the ground pin paired by the pairing unit 34 so that the ratsnest extending to the power supply pin and the ground pin is the shortest, and the ratsnest Create Here, as is well known, the rats nest refers to a net in which a terminal to be connected is connected by a straight line, and disappears when the connection between the terminals is completed. Since the ratsnest display / non-display makes it possible to intuitively and easily grasp the connection state between the terminals, it is extremely useful in designing a printed circuit board.

  The position determination unit 36 changes the position of the bypass capacitor according to the situation around the position calculated by the position calculation unit 25, and determines the position where the current path between the power supply pin and the ground pin and the bypass capacitor is the shortest. Decide where to place the bypass capacitor. For example, when there is a signal pin with wiring restrictions around the power supply pin and the ground pin, the position of the bypass capacitor is changed to a position that does not hinder the wiring of the signal pin. Here, the wiring restriction means that the wiring lines should be arranged adjacent to each other like the differential pair signal wiring, the wiring length should be equal, the wiring length should be a predetermined length, and other wiring restrictions. Say. The position determination unit 36 recognizes the situation around the position calculated by the position calculation unit 25 from the substrate data D1 recorded on the hard disk 23, and automatically executes the position change described above.

  Further, when the bypass capacitor cannot be disposed on the surface of the printed circuit board due to the above wiring restriction, the position determining unit 36 determines the position of the bypass capacitor on the back surface of the printed circuit board and the paired signal pin and ground pin on the front surface. Change the position as close as possible. FIG. 3 is a diagram illustrating an example of the position change of the bypass capacitor. As shown in FIG. 3, between a land to which a power supply pin is connected (rectangular region with a symbol “V”) and a land to which a ground pin is connected (rectangular region with a symbol “G”). When the differential pair signal wirings L1 and L2 are arranged, a wiring for connecting a bypass capacitor cannot be arranged between the differential pair signal wirings L1 and L2. In such a case, as shown in FIG. 3, it is preferable to dispose the bypass capacitor BP on the back surface of the printed board.

  The wiring correction unit 37 performs a process of correcting the wiring on the printed circuit board on which the bypass capacitor is arranged and determining the position on the printed circuit board according to the operation of the input device 12 by the user. The check unit 38 checks whether or not the connection order of the power supply patterns provided for supplying power to the power pins, bypass capacitors, and other electronic components of the electronic component is a predetermined connection order. Also, the voltage drop of the wiring to which the power supply pin of the electronic component and the bypass capacitor are connected is obtained by using the physical characteristics of the wiring and the time rate of change of the current flowing in the wiring, and this voltage drop is set to a preset value. Check if it exceeds. The threshold for the voltage drop is recorded on the hard disk 23 as the check condition D2.

FIG. 4 is a cross-sectional view of the microstrip line. As shown in FIG. 4, the microstrip line has a substrate 40 made of an insulator having a thickness h, a metal layer 41 formed on the entire back surface of the substrate 40, a width W formed on the surface thereof, and a thickness thereof. The structure includes t wirings 42. The inductance L [μH / cm] per unit length of the microstrip line having such a structure is expressed by the following equation. However, μ ₀ in the following formula is the magnetic permeability in vacuum, and μ _r is the relative magnetic permeability of the conductor.
L = (μ ₀ · μ _r /2π)(ln(5.98h/(0.8W+t))+(1/4))

The voltage drop V [V] of the wiring is expressed by the following equation using the inductance L shown in the above equation.
V = L · (di / dt)
Here, the inductance is determined by physical characteristics of the wiring (the thickness h of the substrate 40, the width W and the thickness t of the wiring). Also, (di / dt) in the above equation is the time change rate of the current flowing through the wiring. Therefore, it can be said that the voltage drop of the wiring to which the power supply pin of the electronic component and the bypass capacitor are connected is obtained by using the physical characteristics of the wiring and the rate of change of the current flowing through the wiring.

  The RAM 22 is a volatile memory, and temporarily stores values of various variables used in processing performed by the CPU 21, data in the middle of designing the printed circuit board, and the like. The hard disk 23 stores the board data D1 created by the user and the check condition D2 used by the check unit 38, and various programs (not shown) for realizing the component arrangement correcting unit 31 to the check unit 38 in FIG. ) Is stored.

  The input device 12 includes a keyboard, a mouse, and the like, and outputs operation information corresponding to a user operation to the design apparatus main body 11. The display device 13 includes a CRT (Cathode Ray Tube), a liquid crystal display device, or the like, and displays a result designed by the design device main body 11. Specifically, the position on the printed circuit board of at least the power supply pin and the ground pin of the electronic component and the bypass capacitor whose position is determined by the position determination unit 36 is displayed.

  Next, a printed circuit board design procedure using the circuit board design apparatus 1 having the above-described configuration will be described. FIG. 5 is a flowchart showing an outline of a printed circuit board design procedure. When the design of the printed circuit board is started, first, electronic components are arranged on the printed circuit board by a user operation (step S11). Specifically, the user operates the input device 12 while referring to the display content of the display device 13 to specify the position where the electronic component is to be placed and the type of electronic component placed at that position. Then, the component arrangement correcting unit 31 executes the arrangement of the electronic component designated by the user at the designated position.

  When it is necessary to arrange a plurality of electronic components on the printed circuit board, the same operation as described above is repeated by the user. In addition, not only the arrangement of new electronic components but also the position and type of electronic components already arranged on the printed circuit board can be corrected by user operation. When the arrangement of the electronic components is completed, the data created by the above operation is recorded on the hard disk 23 as the board data D1.

  Next, the wiring is arranged on the printed board by the user's operation (step S12). Specifically, the user operates the input device 12 while referring to the display content of the display device 13 to designate the position where the wiring is to be arranged. Then, the wiring arrangement correcting unit 32 executes the arrangement of the wiring designated by the user at the designated position. When it is necessary to arrange a plurality of wirings on the printed board, the same operation as described above is repeated by the user. As in the case of arranging electronic components, not only a new wiring arrangement but also a wiring already arranged on the printed circuit board can be corrected. When the arrangement of the electronic components is completed, the data created by the above operation is added to the board data D1 and recorded on the hard disk 23.

  When the arrangement of the electronic components and the wiring on the printed board is completed, a process of automatically placing a bypass capacitor on the printed board is performed (step S13). FIG. 6 is a flowchart showing details of a process for automatically arranging a bypass capacitor on a printed circuit board. In the present embodiment, it is assumed that the number of bypass capacitors (for example, 20) arranged on the substrate is preset by the user.

  When the process is started, the component extraction unit 33 reads the board data D1 recorded on the hard disk 23, and extracts data related to the electronic components arranged on the printed board from the board data D1 (step S21). Specifically, for example, data indicating the type of electronic component, data indicating the position of the electronic component on the printed circuit board, data indicating the type and position of the pin, and the like are extracted.

  When the extraction of the data regarding the electronic component is completed, the power supply pin and the ground pin are paired using the data extracted by the pairing unit 34 (step S22). Specifically, for example, as described with reference to FIG. 2, the power supply pin and the ground pin adjacent to each other are paired using the coordinate values on the printed circuit board of the power supply pin and the ground pin of the electronic component included in the extracted data. Is done. Here, the pairing is performed for one electronic component among a plurality of electronic components provided on the printed circuit board, and when a plurality of pairings are possible for one electronic component. Multiple pairings are performed.

  Next, the position calculator 35 calculates the position of the bypass capacitor that minimizes the ratsnest between the paired power supply pin and ground pin (step S23), and at the same time creates the ratsnest. (Step S24). When the above process is completed, the position determining unit 36 performs a process of changing the position of the bypass capacitor calculated by the position calculating unit 35 according to the situation around the position (step S25).

  Specifically, when there is a signal pin with a wiring restriction around the position calculated by the position calculation unit 35, the position of the bypass capacitor is set to a position that does not hinder the wiring of the signal pin, or FIG. As shown in FIG. 5, the back surface of the printed circuit board is changed to a position as close as possible to the paired signal pins and ground pins on the front surface. At this time, even if the position of the bypass capacitor is changed, the connection relation of the rats nest connected from the bypass capacitor to the power supply pin or the ground pin of the electronic component is maintained and is not changed.

  When the above processing is completed, the position determining unit 36 determines whether there is an unused bypass capacitor (step S26). That is, it is determined whether or not the number of bypass capacitors on the printed circuit board exceeds a preset number (for example, 20) of bypass capacitors. When it is determined that there is an unused bypass capacitor (the determination result is “YES”), the position determination unit 36 moves the unused bypass capacitor to the position calculated in step S23 or the position changed in step S25. Arrange (step S27).

  On the other hand, when it is determined that there is no unused bypass capacitor (when the determination result of step S26 is “NO”), the position determination unit 36 creates a new bypass capacitor (step S28). Then, the newly created bypass capacitor is arranged at the position calculated in step S23 or the position changed in step S25 (step S29).

  When the placement of the bypass capacitor is completed, the CPU 21 determines whether or not there is a remaining pair of the power supply pin and the ground pin (step S30). When the CPU 21 determines that there are remaining pairs (when the determination result is “YES”), the position calculation unit 35 calculates the position of the bypass capacitor with the shortest ratsnest for the pair. (Step S23).

  On the other hand, when it is determined in step S30 that there is no remaining pair (when the determination result is “NO”), the CPU 21 determines whether there is a remaining electronic component extracted in step S21 ( Step S31). When the CPU 21 determines that there are remaining electronic components (when the determination result is “YES”), the pairing unit 34 performs pairing for the remaining electronic components (step S22). On the other hand. When it is determined in step S31 that there are no remaining electronic components (when the determination result is “NO”), a series of processes for automatically disposing a bypass capacitor on the printed board shown in FIG. 6 ends.

  When the automatic placement process of the bypass capacitor is completed, a wiring determination process is performed (step S14). FIG. 7 is a flowchart showing details of the wiring determination process. When the processing is started, first, the wiring between pins connected by rats nest is corrected by a user operation (step S41). Specifically, the user operates the input device 12 while referring to the display contents of the display device 13, and connects the rats nest (the bypass capacitor to the power supply pin and the ground pin of the electronic component) where wiring is to be performed. The rat's nest).

  Then, the identified rats nest is brought into a stretchable state (rubber band state) by the wiring correction unit 37. In this state, when the user operates the input device 12 to expand or contract the rats nest and perform an operation of determining the position of one point or a plurality of points on the printed circuit board through which the rats nest passes, the wiring correction unit 37 performs the above operation. The wiring connecting the bypass capacitor and the power supply pin or the ground pin passes through the point determined by the above operation. By the above processing, the wiring (the rats nest that connects the bypass capacitor and the power supply pin and the ground pin of the electronic component) is corrected. The corrected wiring data is added to the board data D1 and recorded in the hard disk 23.

  When the above processing is completed, it is checked whether or not the connection order of the power supply pattern provided to supply power to the power pins of the electronic component, the bypass capacitor, and other electronic components is a predetermined connection order. In addition, the check unit checks whether or not the voltage drop exceeds a preset value (step S42). Specifically, the check unit 38 extracts data on the power pins of the electronic components, the bypass capacitors, and the wiring connecting them from the board data D1 recorded on the hard disk 23, and the power pins and power supply patterns of the electronic components are extracted. It is checked whether or not a bypass capacitor is connected between the power supply pin and the power supply pattern of the wiring connecting the two.

  Further, the check unit 38 calculates the voltage drop of the wiring by using the formula for obtaining the voltage drop V of the wiring from the above-described physical characteristics of the wiring and the time change rate of the current flowing in the wiring. Is read, and it is checked whether or not the calculated voltage drop exceeds the threshold. When the above check is completed, the check unit 38 determines whether there is an error (step S43).

  When it is determined that there is no error (when the determination result in step S43 is “YES”), the check unit 38 determines the wiring arranged in step S41, and data indicating the wiring is recorded in the hard disk 23. Is added to the substrate data D1. On the other hand, when it is determined that there is an error (when the determination result of step S43 is “NO”), the check unit 38 displays an error on the display device 13 (step S45). With the above processing, a series of wiring determination processing shown in FIG. 7 is completed.

  In FIG. 7, for the sake of simplicity, the wiring determination process is terminated after the error is displayed in step S45. However, if necessary, the process returns to step S41 again so that the wiring can be corrected. Is preferred. With the above processing, the printed circuit board design procedure using the substrate design apparatus 1 of this embodiment is completed. The printed circuit board designed by the above procedure is displayed on the display device 13.

  FIG. 8 is a diagram illustrating a display example of a printed circuit board designed using the substrate design apparatus 1 of the present embodiment, and FIG. 8A is a diagram illustrating a display example in the case of a QFP type electronic component, (B) is a figure which shows the example of a display in the case of a BGA type electronic component. As shown in FIG. 8A, in the case of the QFP type electronic component, it can be seen that the electrode of the bypass capacitor BP11 is disposed so as to be adjacent to both the power supply pin and the ground pin. Further, the bypass capacitor BP12 is disposed at a position separated from the ground pin by a certain distance, but it can be seen that the bypass capacitor BP12 is disposed at a position adjacent to the power supply pin as much as possible.

  Further, as shown in FIG. 8B, in the case of a BGA type electronic component, for example, the bypass capacitor BP21 has one electrode in a power supply pin group consisting of four power supply pins Q1 connected to each other by a wiring K1. It can be seen that they are arranged close to each other. Similarly, it can be seen that the bypass capacitor BP22 is arranged so that one electrode is close to the power supply pin group including the six power supply pins Q2 connected to each other by the wiring K2.

  FIG. 9 is a diagram showing another display example of the printed circuit board designed using the substrate design apparatus 1 of the present embodiment. In the display example shown in FIG. 9, a printed circuit board in which a board composed of four layers L11, L12, L13, and L14, and a SOP (Small Outline Package) type electronic component 50 and a bypass capacitor 60 are arranged on the surface side of the board. The top view and sectional drawing of are displayed. Note that the layer L12 of the substrate is a power plane B1, and the layer L13 is a ground plane B2.

  As shown in FIG. 9, the power supply pin 52 of the electronic component 50 is connected to one electrode 61 of the bypass capacitor 60 by the wiring 71, and the ground pin 51 of the electronic component 50 is connected to the ground plane through the via (via) H1. It can be seen that it is connected to B2. Further, it can be seen that one electrode 61 of the bypass capacitor 60 is connected to the via H2 by the wiring 72, and the other electrode 62 is connected to the via H3.

  In the present embodiment, in addition to the display indicating the arrangement and connection state of the electronic component 50 and the bypass capacitor 60 on the substrate described above, the current paths R11 and R12 on the substrate surface side and the inside of the substrate (vias H1 and H3 and ground solids). The current meter R21 on the plane B2) is displayed. By displaying a plan view and a cross-sectional view of the printed circuit board to which the current path illustrated in FIG. 9 is added, the current path can be intuitively and easily grasped, and the user can grasp the current path, the electronic component 50, and the bypass capacitor. The connection order of 60 can be easily confirmed in a short time.

  Here, when there is a hollow portion (a portion where the metal layer is not formed) in the power solid surface B1 or the ground solid surface B2, the current path passing through the power solid surface B1 or the ground solid surface B2 becomes a straight line. In some cases, the curved path avoids the hollow portion. Therefore, in addition to the plan view and the cross-sectional view of the printed circuit board shown in FIG. 9, it is preferable to enable display of current paths in the power supply plane B1 and the ground plane B2.

  FIG. 10 is a plan view showing an example of a current path in the ground plane B2. In the example shown in FIG. 10, vias H1 and H3 are displayed at both ends of the ground plane B2, and hollow portions Z1 to Z5 formed on the ground plane B2 are also displayed. Referring to FIG. 10, it can be seen that the current path R21 between the via H1 and the via H3 is a curved path that avoids the hollow portions Z1 to Z5. Further, when the gap G1 between the hollow portions Z3 and Z4 and the gap G2 between the hollow portions Z4 and Z5 are smaller than the minimum interval preset by the user, the current path R21 is a path that avoids them. I understand.

  As described above, in the present embodiment, data related to electronic components arranged on the printed circuit board is extracted from the board data D1, and the power supply pins and the ground focus of the electronic parts are paired using the extracted data. Then, the position where the rats nest is minimized is calculated between the paired power supply pin and the ground pin, and the current between the power supply pin and the ground pin and the bypass capacitor is calculated according to the situation around the calculated position. The position where the bypass capacitor should be arranged is changed so that the path becomes the shortest.

  For this reason, the bypass capacitor can be automatically arranged at a position that takes into consideration not only the length of the wiring between the electronic component but also the power supply pin and the ground pin of the electronic component. Noise can be further reduced. Specifically, the peak value of the radiation noise at a position 10 m away from the printed circuit board can be reduced by about 20 dB.

  In this embodiment, since the bypass capacitor is automatically arranged at a position where electromagnetic noise can be reduced, the time required for design can be shortened, and noise radiated from the printed circuit board can be reduced by the user ( It is also possible to prevent a situation that is greatly influenced by the skill of the board designer). Furthermore, since the designed printed circuit board can be displayed on the display device 13 in various forms such as displaying with the current path, an educational effect for the designer can be obtained.

  As described above, the substrate design apparatus according to the embodiment of the present invention has been described, but the present invention is not limited to the above embodiment, and can be freely changed within the scope of the present invention. For example, in the above-described embodiment, the case where the plan view and the cross-sectional view of the designed printed board are displayed on the display device 13 has been described as an example. However, any display method such as three-dimensional display can be used. . Further, as shown in FIG. 8B, when bypass capacitors are connected to a plurality of power supply pins, the connection relationship between the plurality of power supply pins and the bypass capacitors is many-to-many at the time of the check in step S42 in FIG. You may check if it is.

It is a block diagram which shows the principal part structure of the board | substrate design apparatus by one Embodiment of this invention. It is a figure which shows the example of pairing with a power supply pin and a ground pin. It is a figure which shows the example of the position change of a bypass capacitor. It is sectional drawing of a microstrip line. It is a flowchart which shows the outline | summary of the design procedure of a printed circuit board. It is a flowchart which shows the detail of the process which arrange | positions a bypass capacitor automatically on a printed circuit board. It is a flowchart which shows the detail of a wiring confirmation process. It is a figure which shows the example of a display of the printed circuit board designed using the board | substrate design apparatus 1 of this embodiment. It is a figure which shows the other example of a display of the printed circuit board designed using the board | substrate design apparatus 1 of this embodiment. It is a top view which shows an example of the electric current path in the ground plane B2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate design apparatus 13 Display apparatus 33 Component extraction part 34 Pairing part 35 Position calculation part 36 Position determination part 38 Check part D1 Board | substrate data D2 Check condition

Claims (6)

In board design equipment that automatically places bypass capacitors using board data, which is design information for printed circuit boards,
An extraction unit for extracting data on electronic components arranged on the printed circuit board from the board data;
A pin associating unit for associating a power supply pin and a ground pin of the electronic component using data related to the electronic component extracted by the extracting unit;
Position calculation for calculating the position where the ratsnest extending from the bypass capacitor to the power supply pin and the ground pin to the power supply pin and the ground pin is shortest between the power supply pin and the ground pin associated by the pin association unit And
The position of the bypass capacitor is changed according to the situation around the position calculated by the position calculation unit, and the position where the current path between the power supply pin and the ground pin and the bypass capacitor is shortest is the bypass capacitor. And a position determining unit that determines a position to be arranged.   The pin associating unit is configured based on pin names given to the power pins and the ground pins, coordinate information on the printed circuit board of the power pins and the ground pins, or correspondence information designated by a user. The board design apparatus according to claim 1, wherein a power supply pin and the ground pin are associated with each other.   The display unit for displaying at least a power supply pin and a ground pin of the electronic component and a position on the printed circuit board of a bypass capacitor whose position is determined by the position determination unit. Board design equipment,   When there is a signal pin whose wiring is limited around the power supply pin and the ground pin associated with each other by the pin association unit, the position determination unit is a position that does not hinder wiring extraction from the signal pin. 4. The substrate design apparatus according to claim 1, wherein a position of the bypass capacitor is determined.   Whether the connection order of the bypass capacitor whose position is determined by the position determination unit, the power supply pin and the ground pin of the electronic component, and the power supply pattern for supplying power to other electronic components is a predetermined connection order 5. The substrate design apparatus according to claim 1, further comprising a confirmation unit configured to confirm whether or not.   The confirmation unit obtains a voltage drop of a wiring to which the power supply pin of the electronic component and the bypass capacitor are connected using a physical characteristic of the wiring and a time change rate of a current flowing through the wiring, and the voltage drop 6. The substrate design apparatus according to claim 5, wherein it is confirmed whether or not exceeds a preset value.

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