JP4966838B2 - Clock wiring processing apparatus, clock wiring processing method, and program - Google Patents

Description

  The present invention relates to a clock wiring processing device, a clock wiring processing method, and a program, and more particularly to a clock wiring processing device, a clock wiring processing method, and a program for wiring from a final stage clock driver to a flip-flop.

  An example relating to clock wiring processing is described in Patent Document 1. The technology described in Patent Document 1 is such that the clock distribution system has a tree shape that branches toward the terminal circuit to which the clock is supplied, and the buffer circuits at each stage so that the wiring between the buffer circuits at each stage has the same length and the same capacity. The number of fan-outs is the same. However, the technique described in Patent Document 1 describes the delay time between the start point F / F end point F / F of the path and the clock skew between the final stage clock drivers that affects the delay time between the F / Fs. Absent.

  The technique described in Patent Document 2 is a configuration in which a clock signal is repeatedly wired from a main clock buffer in an H-shaped tree shape. However, a delay time between a path start point F / F end point F / F, and between the F / Fs. There is no description about the clock skew between the last stage clock drivers which affects the delay time.

JP-A-5-159080 JP 7-86416 A

  In the techniques of Patent Literature 1 and Patent Literature 2, consideration is not given to the delay between the path start point F / F end point F / F and the clock skew that affects the delay between the F / Fs. Therefore, there is a problem that the delay between the path start point F / F end point F / F cannot be minimized.

  An object of the present invention is to provide a clock wiring processing apparatus, a clock wiring processing method, and a program that solve the above-described problems.

  The clock wiring processing apparatus of the present invention extracts a start point F / F end point F / F list in a storage unit, searches for and selects a final stage clock driver candidate connected to the start point F / F and the end point F / F, The clock skew between the start / end point F / F processing unit stored in the storage unit and the final stage clock driver is extracted to the storage unit, and the final stage clock driver candidate connected to the start point F / F and the end point F / F is extracted. A clock skew processing unit that selects the last stage clock driver connected to the start point F / F and the end point F / F that minimizes the clock skew between the last stage clock drivers from a combination, and stores the selected clock driver in the storage unit; It is characterized by providing.

The clock wiring processing method of the present invention is a clock wiring processing method for connecting from the final stage clock driver to the start point F / F and the end point F / F,
The start point F / F end point F / F list is extracted in the storage unit, and the last stage clock driver candidate connected to the start point F / F and the end point F / F is searched and selected, and the start / end point F / stored in the storage unit is stored. F processing step and the clock skew between the final stage clock drivers are extracted to the storage unit, and from the combination of the final stage clock driver candidates connected to the start point F / F and the end point F / F, between the final stage clock drivers And a clock skew processing step of selecting and storing the final stage clock driver connected to the start point F / F and the end point F / F where the clock skew is minimized and storing the clock skew in the storage unit.

The program of the present invention is a program for connecting from the last stage clock driver to the start point F / F and the end point F / F,
The start point F / F end point F / F list is extracted in the storage unit, and the last stage clock driver candidate connected to the start point F / F and the end point F / F is searched and selected, and the start / end point F / stored in the storage unit is stored. The clock skew between the final stage clock drivers is extracted from the combination of the final stage clock driver candidates connected to the start point F / F and the end point F / F. A clock skew process for selecting the last stage clock driver connected to the start point F / F and the end point F / F that minimizes the queue and storing the selected clock driver in the storage unit is executed by a computer.

  The effect of the present invention is that the delay between the path start point F / F end point F / F can be minimized.

  Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram of a clock wiring processing apparatus (1) 100 according to the first embodiment of the present invention.

  The clock wiring processing apparatus (1) 100 includes a start / end point F / F processing unit 101 and a clock skew processing unit 102.

  The start / end point F / F processing unit 101 stores a start point F / F (actually, a name or identifier uniquely indicating the F / F) and an end point F / F list (for example, a memory, a hard disk, a register) The final stage clock driver connected to the start point F / F and the end point F / F (actually, a name or identifier that uniquely identifies the driver) is searched and selected, and stored in the storage unit described above To do.

  Next, the clock skew processing unit 102 extracts the clock skew between the final stage clock drivers to the above-described storage unit. In addition, the clock skew processing unit 102 determines the start point F / F and the end point F / F that minimize the clock skew between the last stage clock drivers from the combination of the last stage clock driver candidates connected to the start point F / F and the end point F / F. Select the final stage clock driver connected to. Thereafter, the clock skew processing unit 102 stores the selected final stage clock driver (in practice, a name or identifier uniquely indicating the driver) in the above-described storage unit.

  Therefore, the clock line processing apparatus (1) 100 according to the first embodiment of the present invention can minimize the delay between the path start point F / F end point F / F.

  The reason is that the clock from the final clock driver to the path start point F / F end point F / F is considered in consideration of the delay between the path start point F / F end point F / F and the clock skew that affects the delay between the F / Fs. This is because a configuration that performs wiring is employed.

  The start / end point F / F processing unit 101 and the clock skew processing unit 102 may be implemented by hardware or software.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

  Hereinafter, “extract F / F”, “store clock driver as a candidate”, “store F / F as a candidate”, and the like are actually “F / F or a name uniquely indicating a clock driver, Or, an identifier or the like is extracted or stored as a candidate.

    Here, a method of connecting wirings connecting from the final stage driver of the clock trunk line supplying the clock signal in the LSI to the flip-flop (hereinafter referred to as F / F) will be described.

  First, the arrangement and wiring status of the clock trunk line and its final stage driver will be described with reference to FIG.

  FIG. 10 shows an example in which a trunk line of a clock signal is supplied to the entire surface of the LSI by the H-Tree method.

  The clock signal supplied to the entire surface of the LSI is first supplied from the first-stage clock driver in the center of the LSI to the two second-stage clock drivers that are equidistant from the first-stage clock driver via the first-stage clock trunk wiring. The In the second and subsequent stages of the clock driver, the clock signal is supplied to the subsequent stage clock driver in a similar manner while maintaining the similar shape.

  FIG. 11 shows a clock trunk line based on the H-Tree system shown in FIG. 10 in a tree shape.

  In this example, the H-Tree method is described as an example. However, if the clock trunk line is made in advance, the clock mesh method in which the clock signal is distributed in a grid pattern, the clock signal in the shape of a fish bone. The same is true for the Fishbone method for distributing the image data.

  In FIG. 10, up to four final stage clock drivers existing in each area obtained by dividing the LSI into 16 areas, the clock trunk line is formed while maintaining the similar shape.

  The clock driver at each stage uses a driver having the same driving capability, and the wiring length and load are made uniform. As a result, the delay time until the clock distributed from the first stage of the clock driver reaches the final stage clock driver is almost the same value, differing only by slight variations due to manufacturing variations or wiring differences.

  As described above, after the clock trunk line is created in advance, the components (hereinafter referred to as instances) are arranged, the wiring between the instances is performed, and then the clock trunk line is supplied to supply the clock signal to the F / F. To the F / F clock input pin.

  After completion of the F / F arrangement, wiring is performed from the final stage clock driver, which is the end of the trunk line supplying the clock, to the F / F.

  Hereinafter, a method for automatically wiring from the final stage clock driver to the F / F will be described in detail.

  FIG. 12 is a diagram showing only the final stage clock driver and the F / F in the vicinity of the final stage clock driver after the clock trunk line is created in advance and the instances are arranged.

  It is assumed that there are seven F / Fs from F / F 511 to F / F 517 in the vicinity of a certain final stage clock driver 401 and final stage clock driver 402.

  These seven F / Fs are a clock supplyable range 621 which is an area where a clock can be supplied from the final stage clock driver 401 and a clock which is an area where a clock can be supplied from the final stage clock driver 402. It exists in the area of the supplyable range 622.

  The clock supply possible range in which this clock can be supplied is determined by how much variation in delay time from the last stage clock driver to the F / F is allowed. For example, since the latter is longer in the wiring length between the final stage clock driver 401 and the F / F 511 and the wiring length between the final stage clock driver 401 and the F / F 517, the delay time is also longer in the latter. Becomes larger. Therefore, the range in which the clock can be supplied is limited to a certain range with a certain final stage clock driver as the center.

  As shown in FIG. 13, the clock supplyable range 622 includes a clock supplyable basic range 623 and a clock supplyable adjacent range 624. As shown by the dot area in FIG. 13, the clock-suppliable basic range 623 is limited to a certain range with the final stage clock driver 402 as the center. Further, the clock-supplyable adjacent range 624 is adjacent to the outside of this clock-supplyable basic range, as indicated by the hatched area in FIG.

  In the clock supplyable adjacent range 624, a part of the clock supplyable range 621 and a part of the clock supplyable range 622 overlap (in FIG. 13, the overlapping of the left and right adjacent clockable ranges is shown, but the upper and lower adjacent ranges The clockable range is also overlapping).

  The reason for this overlap is as follows.

  As a state after the instance is arranged, there may be a case where a large amount of F / F exists in the vicinity of a certain final stage clock driver and only a small amount of F / F exists in the vicinity of a certain final stage clock driver. In that case, in a portion where a large amount of F / F exists, the number of F / Fs driven by the final stage clock driver increases, and the delay time from the final stage clock driver to the F / F due to an increase in load capacity deteriorates. Further, in a place where only a few F / Fs exist, the load capacity of the F / F driven by the final stage clock driver is small, and the delay time does not deteriorate greatly. In order to adjust the variation in delay time from the final stage clock driver to the F / F, the range of clock supply is overlapped for the purpose of making the number of F / Fs driven by the final stage clock driver uniform. ing.

  FIG. 14 is a flowchart of automatic wiring processing for supplying a clock from the final stage clock driver to the F / F.

  Referring to the flowchart of FIG. 14, first, the F / F existing in the basic clock supplyable range of the final stage clock driver is connected to the final stage clock driver. Accordingly, the F / F 511 and the F / F 512 within the clock supply possible basic range 623 shown in FIG. 12 are connected to the final stage clock driver 401.

  Further, the F / F 516 and the F / F 517 within the clock supply possible basic range 623 are connected to the final stage clock driver 402 (step S50).

  Next, the F / F existing in the adjacent range where the clock of the last stage clock driver can be supplied is changed to the last stage clock driver having the closest distance so that the number of F / Fs driven by the adjacent last stage clock driver becomes equal. Connected. Therefore, the connection destinations of the F / Fs 513, 514, and 532 in the adjacent range where the clock can be supplied shown in FIG. Since the number of F / Fs driven by adjacent final stage clock drivers is two, two of the three F / Fs have final stages so that the F / Fs driven by adjacent final stage clocks are equal. One clock driver 401 and one last stage clock driver 402 are connected. Further, the F / F 513 is connected to the final stage clock driver 401 having a short distance, and the F / F 532 is connected to the final stage clock driver 402 having a short distance (step S51).

  Finally, the F / F for which the final stage clock driver to be connected in all processes cannot be determined is connected to the final stage clock driver having the closest distance. Accordingly, the connection of the F / F 514 shown in FIG. 12 is determined. The F / F 514 is connected to the final stage clock driver 402 having the shortest distance (step S52).

  FIG. 15 shows a state after the wiring connection from the final stage clock driver to the F / F performed by the flowchart shown in FIG.

  Next, the problem of the connection method of the wiring connecting from the last stage driver of the clock trunk line described above to the F / F will be described in detail below.

  First, the clock skew between the final stage clock drivers resulting from the relationship of the final stage clock driver connected to the start / end point F / F of the inter-F / F path will be described.

  The clock skew between the final stage clock drivers is the difference in circuit delay time due to manufacturing variations of clock drivers on the clock trunk path, manufacturing variations in wiring delay time, and wiring delay time due to clock wiring when the clock trunk line is created. Caused by the difference.

  For example, even if an H-Tree structure as shown in FIG. 10 is adopted and a structure in which the relationship from the clock driver first stage to all final stage clock drivers is equal as shown in FIG. Clock skew occurs between the stage clock drivers.

  Further, since clock skew does not occur at the same path, the clock skew difference is small if there are many identical places in the path to the final stage clock driver, and the clock skew increases if the same places are small.

  The clock skew between final stage clock drivers when attention is paid to a certain final stage clock driver will be described with reference to FIG.

  The last stage clock driver to which the clock is supplied from the fifth stage of the same clock driver is considered as one group, and the seventh last stage clock driver group from the left is group A.

  Since the route to the fourth stage of the clock driver is the same as that of the last stage clock driver of the group B with respect to the last stage clock driver of the group A, the clock skew is caused by the difference in delay time after the fifth stage of the clock driver.

  The clock skew between the last stage clock driver of group A and the last stage clock driver of group C is caused by the difference in delay after the fourth stage of the clock driver. Therefore, the clock skew SKEW-AC between group A and group C is larger than the SKEW-AB with respect to the clock skew SKEW-AB between group A and group B.

Similarly, the clock skew relationship between each group for group A is
SKEW-AE>SKEW-AD>SKEW-AC> SKEW-AB
It becomes.

  FIG. 17 shows an example of the final stage clock driver and the inter-F / F path.

  The path delay time is estimated before the clock connection, and it is assumed that there is a path X having a long delay time. The F / F 531 that is the start point F / F of the path X can be supplied with a clock from the final stage clock driver of the group A, and the F / F 532 that is the end point F / F of the path X is the group B and the group E. It is assumed that the clock can be supplied from the final stage clock driver.

  Since the delay time of the path X is long and SKEW-AB is smaller than the SKEW-AE, in this case, the path delay time + SKEW-AE may exceed one clock. The clock should be supplied from the B final stage clock driver. However, in the automatic wiring processing method from the final stage clock driver to the F / F shown in the flowchart of FIG. 14, the F / F 532 shown in FIG. Therefore, the F / F 532 cannot be supplied with a clock from the final stage clock driver of the group B.

  Therefore, the automatic wiring processing method shown in the flowchart of FIG. 14 does not consider the delay time of the path between the F / Fs, and therefore the delay between the path start point F / F end point F / F cannot be minimized. There is.

  Next, a clock wiring processing apparatus (2) 200 according to the second embodiment of the present invention for solving the above-described problem will be described below.

  FIG. 2 is a configuration diagram of a clock wiring processing apparatus (2) 200 according to the second embodiment of the present invention.

  The clock wiring processing device (2) 200 is a device for wiring a clock signal from the last stage clock driver to the start / end point F / F after the clock trunk line is previously created by the H-Tree method, the clock mesh method, the Fishbone method, or the like. It is.

  The clock wiring processing device (2) 200 includes a storage unit 201, a clock wiring processing unit 202, a start point F / F end point F / F list database 210, an F / F final stage clock driver clock supplyable range database 211, and a final stage clock driver. An inter-clock skew database 212 and an input / output processing unit 213 are included.

  Here, the clock wiring processing unit 202 includes a data processing unit 203, a start / end point F / F processing unit 101, and a clock skew processing unit 102.

The start / end point F / F processing unit 101 includes a start point F / F processing unit 1010 and an end point F / F processing unit 1011.
Note that each unit may be described by a program, stored in the storage unit 201, and read out and executed by the processor and executed to execute each unit.

  The storage unit 201 is a storage device that stores information and processing results. The input / output processing unit 213 performs data input / output processing.

  The data processing unit 203 executes the entire processing of the clock wiring processing device (2) 200.

  The start point F / F end point F / F list database 210 stores a start point F / F end point F / F list of paths sorted in order of delay time.

  The start point F / F processing unit 1010 is a last-stage clock driver that connects the last-stage clock driver corresponding to the clock-supplyable basic range to the start-point F / F when the start-point F / F is in the clock-supplyable basic range. Select as a candidate. The start point F / F processing unit 1010, when the start point F / F exists in the adjacent range where the clock can be supplied, connects the last stage clock driver corresponding to the adjacent range where the clock can be supplied to the start point F / F. Select as a driver candidate.

  The end point F / F processing unit 1011 also connects the last stage clock driver corresponding to the clock supplyable basic range to the end point F / F when the end point F / F exists in the clock supplyable basic range. Select as a driver candidate. The end point F / F processing unit 1011 connects all the last stage clock drivers corresponding to the clock supplyable adjacent range to the end point F / F when the end point F / F exists in the clock supplyable adjacent range. Select as a driver candidate.

  The clock skew processing unit 102 extracts the clock skew between the final stage clock drivers to the storage unit 201. In addition, the clock skew processing unit 102 determines the start point F / F and the end point F / F that minimize the clock skew between the last stage clock drivers from the combination of the last stage clock driver candidates connected to the start point F / F and the end point F / F. Select the final stage clock driver connected to. Thereafter, the clock skew processing unit 102 stores the selected final stage clock driver in the storage unit 201.

FIG. 3 is a diagram illustrating an example of the start point F / F end point F / F list database 210.
The path start point F / F, end point F / F, and path delay time are shown in descending order of path delay time. (F / F531, F / F532, 2.35nS), (F / FS2, F / FE2, D2nS) corresponding to the paths with the first, second, third, and nth largest delay times of the path, (F / FS3, F / FE3, D3nS) and (F / FSn, F / FEn, DnnS) are shown.

  FIG. 4 is a diagram illustrating an example of the database in FIG. 15 that indicates in which last stage clock driver the clock supply range of each F / F exists.

  For example, the F / F 511 exists in the basic range in which the clock of the final stage clock driver 401 can be supplied. The F / F 513 exists in the adjacent range in which the clocks of the final stage clock drivers 401 and 402 can be supplied.

  FIG. 5 is a diagram illustrating an example of the clock skew database 212 between the final stage clock drivers. Corresponding to the configuration of the final stage clock driver shown in FIG. 16, an example of the clock skew of each group among the group A, group B, group C, group D, and group E of the final stage clock driver is shown. SKEW-AB (0.1 nS) as the clock skew of group A and group B, SKEW-AC as the clock skew of group A and group C, SKEW-AD as the clock skew of group A and group D, and group A and group E SKEW-AE (0.3 nS) is shown as the clock skew, and SKEW-XY is shown as the clock skew of group X and group Y.

  FIG. 6 is a diagram illustrating an example of the final stage clock driver candidate data stored in the storage unit 201. The start point F / F, the final stage clock driver candidate, the end point F / F, and the final stage clock driver candidate are illustrated. Has been. (F / F531, Group A, F / F532, Group B, Group E), (F / FS2, Group X2) corresponding to the paths with the first, second, third, and nth largest delay times. , F / FE2, group Y2), (F / FS3, group X3, F / FE3, group Y3) and (F / FSn, group Xn, F / FEn, group Yn) are shown.

  FIG. 7 is a diagram illustrating an example of an arrangement state of the start point F / F end point F / F when clock wiring is performed from the final stage clock driver to the F / F.

  FIG. 8 is a diagram illustrating an example of a wiring result in which clock wiring is performed from the final stage clock driver to the F / F.

  FIG. 9 is a flowchart showing the operation of the clock wiring processing apparatus (2) 200 according to the second embodiment of the present invention.

  Next, the operation of the clock wiring processing apparatus (2) 200 configured as described above will be described based on the flowchart of FIG. 9 by taking the F / F arrangement state shown in FIG. 7 as an example.

  First, the F / F arrangement state shown in FIG. 7 will be described. The starting point F / F 531 of the path X741 having the longest delay time after the automatic arrangement of the instances is the basic range 623 in which the group A final stage clock driver 413 can supply the clock. Is assumed to exist within.

  The end point F / F 532 of the path X741 exists in the clock supplyable adjacent range 624 where the clock supplyable range 621 of the group B final stage clock driver 411 and the clock supplyable range 622 of the group E final stage clock driver 412 overlap. I assume that.

  Referring to FIG. 9, first, the data processing unit 203 uses the start point F / F end point F / F list of paths sorted in order of delay time input from the input / output processing unit 213 as the start point F / F end point F / F list. Store in the database 210 (step S10). The path start point F / F end point F / F list sorted in the order of the delay times is obtained from the delay time estimation result. This delay estimation result is, for example, the result of timing-driven placement that gives RTL (Register Transfer Level) and delay time constraints (clock values) and performs F / F placement, combinational circuit generation and optimization. Obtained from. The delay estimation results are subjected to connection from the last stage clock driver to the F / F in order from the longest delay time, sorted in order of long delay time. FIG. 3 shows an example of the start point F / F end point F / F list database 210.

  In addition, the data processing unit 203 supplies data indicating in which last stage clock driver the clock supply range of each F / F input from the input / output processing unit 213 is within the F / F final stage clock driver clock supply range. Store in the database 211 (step S11).

  Next, the data processing unit 203 stores the list including the clock skew between the final stage clock drivers input from the input / output processing unit 213 in the final stage clock driver clock skew database 212 (step S12). The clock skew between the final stage clock drivers is created from the clock skew value estimated from the structure of the built-in clock trunk line. FIG. 5 shows an example of the clock skew database 212 between the final stage clock drivers.

  Next, the data processing unit 203 reads from the start point F / F end point F / F list database 210 the start point F / F and end point F / F of the F / F path with the longest delay time that has not been processed, Extracted in the storage unit 201 (step S13). Based on the extraction result, the data processing unit 203 first starts processing from the start point F / F.

  The data processing unit 203 obtains the start point F / F and the end point F / F of the inter-F / F path with the longest delay time that has not been processed from the start point F / F end point F / F list database 210 shown in FIG. It is determined that F / F 531 is the start point F / F and the end point F / F is F / F 532 as the processing target.

  Further, the data processing unit 203 reads the clock skew between the final stage clock drivers from the clock skew database 212 between the final stage clock drivers and stores it in the storage unit 201 (step S14).

  Next, the data processing unit 203 checks whether or not the clock connection to the start point F / F is already connected (step S15). The reason for performing this check is that when the loop portion of the flowchart shown in FIG. 9 is repeated, the start point F / F of one path is the end point F / F of another path, so that the clock may already be connected. Because there is. In the example shown in FIG. 7, the data processing unit 203 checks whether or not the clock has been wired to the start point F / F 531 (step S15). Since this is the first process in the loop portion of the flowchart, the clock is not yet connected.

  When the clock is already connected (YES in step S15), the data processing unit 203 uses the connected final stage clock driver as a candidate and stores it in the storage unit 201 (step S20). If the data processing unit 203 is not connected (step S15 / NO), the data processing unit 203 takes over the process to step S30.

  Next, the start point F / F processing unit 1010 refers to the F / F final stage clock driver clock supplyable range database 211 and determines whether or not the start point F / F is in the basic clock supplyable range. (Step S30).

  The start point F / F processing unit 1010 connects the last stage clock driver corresponding to the clock supplyable basic range to the start point F / F when the start point F / F exists in the clock supplyable basic range (step S30 / YES). The final stage clock driver candidate is stored in the storage unit 201 (step S31).

  Further, the start point F / F processing unit 1010, when the start point F / F exists in the adjacent range where the clock can be supplied (step S30 / NO), sets all the final stage clock drivers corresponding to the adjacent range where the clock can be supplied to the start point F / F. A candidate for the final stage clock driver connected to F is stored in the storage unit 201 (step S32).

  Referring to the example shown in FIG. 7, when the last stage clock driver capable of supplying the clock to the start point F / F 531 is searched, the start point F / F 531 exists in the clock supplyable basic range 623 of the group A last stage clock driver 413. Therefore, the final stage clock driver candidate for supplying the clock for the end point F / F 531 is the group A final stage clock driver 413.

  Next, the data processing unit 203 checks whether or not the clock connection to the end point F / F is already connected (step S21). Similar to the start point F / F, the data processing unit 203 checks whether the end point F / F of one path is the start point F / F of another path and a clock is already connected to the end point F / F. .

  In the example of FIG. 7, it is checked whether or not the clock has been wired to the end point F / F 531 (step S21). Since this is the first process in the loop portion of the flowchart, the clock is not yet connected.

  When the clock is already connected (YES in step S21), the data processing unit 203 uses the connected final stage clock driver as a candidate and stores it in the storage unit 201 (step S22). When the data processing unit 203 is not connected (step S21 / NO), the data processing unit 203 takes over the process to step S33.

  Next, the end point F / F processing unit 1011 refers to the F / F final stage clock driver clock supplyable range database 211 to determine whether or not the end point F / F exists in the basic clock supplyable range. (Step S33).

  The end point F / F processing unit 1011 connects the last stage clock driver corresponding to the clock supply basic range to the end point F / F when the end point F / F exists in the clock supply basic range (step S33 / YES). The final stage clock driver candidate to be stored is stored in the storage unit 201 (step S34).

  In addition, when the end point F / F exists in the adjacent range where the clock can be supplied (NO in step S33), the end point F / F processing unit 1011 sets all the final stage clock drivers corresponding to the adjacent range where the clock can be supplied as the end point F. The final stage clock driver connected to / F is stored in the storage unit 201 (step S35).

  In the example shown in FIG. 7, when a final stage clock driver that can supply a clock to the end point F / F 532 is searched, the end point F / F 532 overlaps with the group B final stage clock driver 411 and the group E final stage clock driver 412. Therefore, the group B final stage clock driver 411 and the group E final stage clock driver 412 are the candidates for the final stage clock driver that supplies the clock for the end point F / F 532.

  Next, the data processing unit 203 checks whether a clock has already been connected to the start point F / F and the end point F / F (step S23). If the clocks are already connected to both F / Fs (step S23 / YES), the data processing unit 203 skips the clock connection process.

  The data processing unit 203 performs clock connection processing when the clock is not connected to either the start point F / F, the end point F / F, or both F / Fs (step S23 / NO).

  In the example illustrated in FIG. 7, the data processing unit 203 performs the process of step S24 because clock wiring is not performed for both the start point F / F and the end point F / F.

  Next, the data processing unit 203 selects and stores the clock skew between the final stage clock drivers corresponding to the final stage clock driver of the start point F / F and the final driver of the end point F / F, which are candidates by the processes so far. Store in the unit 201 (step S24).

  Next, the clock skew processing unit 102 calculates the minimum skew from the final stage clock driver for each combination of the extracted final stage clock driver candidate of the start point F / F and the final stage clock driver candidate of the end point F / F. Select the skew between the last stage clock drivers. Then, the clock skew processing unit 102 connects the start point F / F and the end point F / F final stage clock driver corresponding to the minimum skew between the final stage clock drivers to the start point F / F and the end point F / F. The driver is selected and stored in the storage unit 201 (step S36).

  In the example shown in FIG. 7, the final stage clock driver candidate that supplies the clock for the start point F / F 531 is the group A final stage clock driver 413, and the final stage clock driver candidate that supplies the clock for the end point F / F 532. Are a group B final stage clock driver 411 and a group E final stage clock driver 412. For this reason, the clock skew processing unit 102 performs the clock skew SKEW-AB between the group A final stage clock driver 413 and the group B final stage clock driver 411, and between the group A final stage clock driver 413 and the group E final stage clock driver 412. The clock skew SKEW-AE is extracted.

  Next, as shown in FIG. 5, the clock skew processing unit 102 uses the group A final stage clock driver 413 as a final stage clock driver that supplies a clock for the start point F / F because SKEW-AB is smaller than SKEW-AE. select. Further, the clock skew processing unit 102 selects the group B final stage clock driver 411 as the final stage clock driver that supplies a clock for the end point F / F.

  Thereafter, the data processing unit 203 connects the final stage clock driver on the selected start point F / F side and the start point F / F, and connects the selected final stage clock driver on the end point F / F side and the end point F / F. (Step S25). For example, the data processing unit 203 includes “data indicating a set of the identifier of the final stage clock driver on the selected start point F / F side and the identifier of the start point F / F” and “the selected end point F / F side” The data indicating the set of the identifier of the last stage clock driver and the identifier of the end point F / F ”is stored in the storage unit 201.

  In the example illustrated in FIG. 7, the data processing unit 203 connects the wiring from the group A final stage clock driver 413 to the F / F 531 and from the group B final stage clock driver 411 to the F / F 532. Connect the wiring.

  Next, the data processing unit 203 determines whether or not the clock connection of all start points F / F and end points F / F has been completed (step S26). If the clock connection of all start points F / F and end points F / F is not completed (step S26 / NO), the processing is taken over to step S13.

  FIG. 8 is a diagram illustrating an example of a wiring result obtained by performing clock wiring as described above.

  The clock wiring shown in FIG. 8 is a case where a clock is to be supplied from the final stage clock driver having a long path delay time and a small clock skew. Connected to F.

Here, in FIG. 8 and FIG.
(1) Target delay time is 2.5nS
(2) The sum of the wiring delay time from F / F 31 to F / F 32, the circuit delay time, and the setup time of F / F 32 is 2.35 nS (shown in FIG. 3).
(3) SKEW-AB is 0.1 nS (shown in FIG. 5)
(4) Assume that SKEW-AE is 0.3 nS (shown in FIG. 5).

  In the case of FIG. 18 in which the last stage clock buffer connected to the F / F 532 is the group E, the delay time is 2.35 nS + 0.3 nS = 2.65 nS, which exceeds the target of 2.5 nS. In the case of FIG. 8, since the final stage clock buffer connected to the F / F 532 is determined to be group B, the delay time is 2.35 nS + 0.1 nS = 2.45 nS, which satisfies the target 2.5 nS.

  After the processing so far, the data processing unit 203 checks whether the clock connection of all the start points F / F end points F / F is completed (step S26). If it is not completed, the data processing unit 203 repeats the above processing for the next inter-F / F path (step S26 / NO). If all of the data processing unit 203 has been completed, the automatic connection processing ends (step S26 / YES).

  As described above, the clock wiring processing apparatus (2) 200 according to the second embodiment of the present invention affects the delay between the path start point F / F end point F / F and the delay between the F / Fs. Considering the clock skew, the clock wiring from the final clock driver to the path start point F / F end point F / F is performed, so that the delay between the path start point F / F end point F / F can be minimized.

It is a block diagram of the clock wiring processing apparatus (1) 100 which is the 1st Embodiment of this invention. It is a block diagram of the clock wiring processing apparatus (2) 200 which is the 2nd Embodiment of this invention. It is a figure which shows one example of the start point F / F end point F / F list database 210 which is the 2nd Embodiment of this invention. It is a figure which shows one example of the F / F last stage clock driver clock supply possible range database 211 which is the 2nd Embodiment of this invention. It is a figure which shows one example of the clock skew database 212 between the last stage clock drivers which is the 2nd Embodiment of this invention. It is a figure which shows an example of the last stage clock driver candidate data which is the 2nd Embodiment of this invention. It is a figure which shows an example of the arrangement | positioning state of the start point F / F end point F / F when implementing clock wiring in the clock wiring processing apparatus (2) 200 which is the 2nd Embodiment of this invention. It is a figure which shows one example of the wiring result which implemented the clock wiring in the clock wiring processing apparatus (2) 200 which is the 2nd Embodiment of this invention. It is a flowchart which shows operation | movement of the clock wiring processing apparatus (2) 200 which is the 2nd Embodiment of this invention. It is a figure which shows an example at the time of supplying a clock trunk line to the whole surface of LSI by the H-Tree system. It is a figure which shows what represented the clock trunk line by the H-Tree system shown in FIG. 10 in tree shape. It is a figure which shows one example of the last stage clock driver and F / F about the last stage clock driver vicinity after arrange | positioning an instance. It is a figure shown about a clock supply possible range. It is a figure which shows the flowchart of the automatic process which supplies a clock to F / F from the last stage clock driver. It is a figure which shows the state after the wiring from the last stage clock driver to F / F performed by the flowchart shown in FIG. It is the figure which represented the clock trunk line in the shape of a tree. It is a figure which shows one example of the connection of the last stage clock driver and the start point F / F end point F / F. It is a figure which shows the state after the wiring from the last stage clock driver to F / F performed by the flowchart shown in FIG.

Explanation of symbols

100 Clock wiring processor (1)
101 Start / End F / F Processing Unit 102 Clock Skew Processing Unit 200 Clock Wiring Processing Device (2)
DESCRIPTION OF SYMBOLS 201 Memory | storage part 202 Clock wiring process part 203 Data processing part 210 Start point F / F end point F / F list database 211 F / F last stage clock driver clock supplyable range database 212 Clock skew database between last stage clock drivers 213 Input / output processing part 401 Final stage clock driver 402 Final stage clock driver 411 Group B final stage clock driver 412 Group E final stage clock driver 413 Group A final stage clock driver 511 F / F
512 F / F
513 F / F
514 F / F
517 F / F
531 F / F
532 F / F
621 Clock supply range 622 Clock supply range 623 Clock supply basic range 624 Clock supply adjacent range 1010 Start point F / F processing unit 1011 End point F / F processing unit

Claims (15)

The start point F / F end point F / F list is extracted in the storage unit, and the last stage clock driver candidate connected to the start point F / F and the end point F / F is searched and selected, and the start / end point F / stored in the storage unit is stored. The clock skew between the F processing unit and the final stage clock driver is extracted to the storage unit, and the combination of the final stage clock driver candidates connected to the start point F / F and the end point F / F is determined between the final stage clock drivers. A clock skew processing unit for selecting the final stage clock driver connected to the start point F / F and the end point F / F that minimizes the clock skew and storing the selected clock driver in the storage unit. Processing equipment. The start / end point F / F processing unit selects a candidate for the final stage clock driver to be connected to the start point F / F, and connects to the start point F / F processing unit to be stored in the storage unit and the end point F / F The clock wiring processing device according to claim 1, further comprising: an end point F / F processing unit that selects a candidate for the final stage clock driver to be stored and stores it in the storage unit. The start point F / F processing unit connects the last stage clock driver corresponding to the clock supply basic range to the start point F / F when the start point F / F exists in the clock supply basic range. All the final stage clocks corresponding to the clock supplyable adjacent range are selected as candidates for the final stage clock driver, stored in the storage unit, and the start point F / F exists in the clock supplyable adjacent range. Selecting a driver as a candidate for the final stage clock driver to be connected to the start point F / F, and storing it in the storage unit;
The end point F / F processing unit connects the final stage clock driver corresponding to the clock supplyable basic range to the end point F / F when the end point F / F exists in the clock supplyable basic range. All the final stages corresponding to the clock supplyable adjacent range when selected as candidates of the final stage clock driver and stored in the storage unit, and the end point F / F exists in the clock supplyable adjacent range 3. The clock wiring processing apparatus according to claim 2, wherein a clock driver is selected as a candidate for the final stage clock driver connected to the end point F / F and stored in the storage unit. A start point F / F end point F / F list database for storing the start point F / F end point F / F list; and a final stage clock driver inter-clock skew database for storing the final stage clock driver inter-clock skew database. 4. The clock wiring processing apparatus according to claim 3, wherein: The start point F / F and the end point F / are sorted in descending order of path delay time from the start point F / F end point F / F list sorted in order of path delay time from the start point F / F to the end point F / F. 5. The clock wiring processing apparatus according to claim 1, further comprising: a start / end point F / F processing unit that extracts F. 6. A clock wiring processing method for connecting from a final stage clock driver to a start point F / F and an end point F / F,
The start point F / F end point F / F list is extracted in the storage unit, and the last stage clock driver candidate connected to the start point F / F and the end point F / F is searched and selected, and the start / end point F / stored in the storage unit is stored. F processing step and the clock skew between the final stage clock drivers are extracted to the storage unit, and from the combination of the final stage clock driver candidates connected to the start point F / F and the end point F / F, between the final stage clock drivers A clock skew selection processing step of selecting the final stage clock driver connected to the start point F / F and the end point F / F that minimize the clock skew and storing the selected clock driver in the storage unit. Wiring processing method. The start / end point F / F processing step selects a final stage clock driver candidate to be connected to the start point F / F and stores it in the storage unit, and connects to the end point F / F The clock wiring processing method according to claim 6, further comprising: an end point F / F processing step of selecting a candidate for the final stage clock driver to be stored and storing the candidate in the storage unit. In the start point F / F processing step, when the start point F / F exists in the clock supply basic range, the final stage clock driver corresponding to the clock supply basic range is connected to the start point F / F. All the final stage clocks corresponding to the clock supplyable adjacent range are selected as candidates for the final stage clock driver, stored in the storage unit, and the start point F / F exists in the clock supplyable adjacent range. A driver is selected as a candidate for the last stage clock driver to be connected to the start point F / F and stored in the storage unit. The end point F / F processing step includes a basic range in which the end point F / F can supply the clock. The last-stage clock driver that connects the last-stage clock driver corresponding to the clock-suppliable basic range to the end-point F / F. All the final stage clock drivers corresponding to the clock supplyable adjacent range when the end point F / F exists in the clock supplyable adjacent range. 8. The clock wiring processing method according to claim 7, wherein the clock wiring processing method is selected as a candidate for the final stage clock driver connected to the end point F / F and stored in the storage unit. Storing the start point F / F end point F / F list in a start point F / F end point F / F list database, and storing the clock skew between the last stage clock drivers in a clock skew database between the last stage clock drivers. 9. The clock wiring processing method according to claim 8, further comprising: The start point F / F and the end point F / are sorted in descending order of path delay time from the start point F / F end point F / F list sorted in order of path delay time from the start point F / F to the end point F / F. The clock wiring processing method according to claim 6, further comprising: a start / end point F / F processing step of extracting F. A program for connecting from the last stage clock driver to the start point F / F and the end point F / F,
The start point F / F end point F / F list is extracted in the storage unit, and the last stage clock driver candidate connected to the start point F / F and the end point F / F is searched and selected, and the start / end point F / stored in the storage unit is stored. The clock skew between the final stage clock drivers is extracted from the combination of the final stage clock driver candidates connected to the start point F / F and the end point F / F. A program that causes a computer to execute clock skew processing that selects and stores the final stage clock driver connected to the start point F / F and end point F / F that minimize the queue and stores the clock driver in the storage unit. . In the start / end point F / F process, the final stage clock driver candidate to be connected to the start point F / F is selected, and the start point F / F process to be stored in the storage unit and the end point F / F to be connected to the end point F / F are selected. 12. The program according to claim 11, further comprising: an end point F / F process for selecting a final stage clock driver candidate and storing it in the storage unit. In the start point F / F processing, when the start point F / F exists in the clock supply basic range, the final stage clock driver corresponding to the clock supply basic range is connected to the start point F / F. All the final stage clock drivers corresponding to the clock supplyable adjacent range when selected as candidates for the stage clock driver, stored in the storage unit, and when the start point F / F exists in the clock supplyable adjacent range Are selected as candidates for the final stage clock driver connected to the start point F / F, and stored in the storage unit,
In the end point F / F process, when the end point F / F exists in the basic range that can supply the clock, the final stage clock driver corresponding to the basic range that can supply the clock is connected to the end point F / F. All the final stage clocks corresponding to the clock supplyable adjacent range when selected as candidates of the final stage clock driver, stored in the storage unit, and the end point F / F exists in the clock supplyable adjacent range 13. The program according to claim 12, wherein a driver is selected as a candidate for the final stage clock driver connected to the end point F / F and stored in the storage unit. A process of storing the start point F / F end point F / F list in a start point F / F end point F / F list database and a process of storing the clock skew between the last stage clock drivers in the clock skew database between the last stage clock drivers. 14. The program according to claim 13, which is executed by a computer. The start point F / F and the end point F / are sorted in descending order of path delay time from the start point F / F end point F / F list sorted in order of path delay time from the start point F / F to the end point F / F. The program according to any one of claims 11 to 14, which causes a computer to execute the start / end point F / F processing for extracting F.

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