JP4965974B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP4965974B2
JP4965974B2 JP2006307700A JP2006307700A JP4965974B2 JP 4965974 B2 JP4965974 B2 JP 4965974B2 JP 2006307700 A JP2006307700 A JP 2006307700A JP 2006307700 A JP2006307700 A JP 2006307700A JP 4965974 B2 JP4965974 B2 JP 4965974B2
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Japan
Prior art keywords
cache
controller
semiconductor integrated
integrated circuit
circuit device
Prior art date
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JP2006307700A
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English (en)
Japanese (ja)
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JP2008123333A (ja
JP2008123333A5 (enExample
Inventor
真一 芝原
雅士 高田
達也 亀井
清 早瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2006307700A priority Critical patent/JP4965974B2/ja
Publication of JP2008123333A publication Critical patent/JP2008123333A/ja
Publication of JP2008123333A5 publication Critical patent/JP2008123333A5/ja
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2006307700A 2006-11-14 2006-11-14 半導体集積回路装置 Active JP4965974B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006307700A JP4965974B2 (ja) 2006-11-14 2006-11-14 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006307700A JP4965974B2 (ja) 2006-11-14 2006-11-14 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2008123333A JP2008123333A (ja) 2008-05-29
JP2008123333A5 JP2008123333A5 (enExample) 2009-12-24
JP4965974B2 true JP4965974B2 (ja) 2012-07-04

Family

ID=39508013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006307700A Active JP4965974B2 (ja) 2006-11-14 2006-11-14 半導体集積回路装置

Country Status (1)

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JP (1) JP4965974B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102906713A (zh) * 2010-05-27 2013-01-30 富士通株式会社 信息处理系统以及系统控制器
JP5360299B2 (ja) * 2010-06-14 2013-12-04 富士通株式会社 マルチコアプロセッサシステム、キャッシュコヒーレンシ制御方法、およびキャッシュコヒーレンシ制御プログラム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123151A (ja) * 1990-09-13 1992-04-23 Fujitsu Ltd システムバス
JP3340047B2 (ja) * 1997-03-11 2002-10-28 株式会社日立製作所 マルチプロセッサシステムおよび複製タグの制御方法
US6470437B1 (en) * 1999-12-17 2002-10-22 Hewlett-Packard Company Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design
JP4695367B2 (ja) * 2004-08-31 2011-06-08 富士通株式会社 情報処理装置，制御装置及び情報処理装置の制御方法
JP2006185284A (ja) * 2004-12-28 2006-07-13 Renesas Technology Corp データ処理装置
JP4848771B2 (ja) * 2006-01-04 2011-12-28 株式会社日立製作所 キャッシュ一貫性制御方法およびチップセットおよびマルチプロセッサシステム
JP4297968B2 (ja) * 2006-02-14 2009-07-15 富士通株式会社 コヒーレンシ維持装置およびコヒーレンシ維持方法

Also Published As

Publication number Publication date
JP2008123333A (ja) 2008-05-29

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