JP4963246B2 - Motor driving circuit, driving method, and disk device using them - Google Patents

Description

  The present invention relates to a motor drive circuit that controls a sensorless motor.

  In an electronic device using a disk-type medium such as a portable CD (Compact Disc) device or a DVD (Digital Versatile Disc), a brushless DC motor is used to rotate the disk. A brushless DC motor generally includes a rotor having a permanent magnet and a stator having a plurality of star-connected coils, and excites the coil by controlling the current supplied to the coil. Is driven relative to the stator. In order to detect the rotational position of the rotor, the brushless DC motor generally includes a sensor such as a Hall element or an optical encoder, and switches the current supplied to the coil of each phase according to the position detected by the sensor. And apply an appropriate torque to the rotor.

  In order to further reduce the size of the motor, a sensorless motor that detects the rotational position of the rotor without using a sensor such as a Hall element has also been proposed (for example, see Patent Documents 1 and 2). A sensorless motor, for example, monitors the potential of the midpoint wiring of the motor (hereinafter referred to as the midpoint voltage) and the back electromotive voltage (inductive voltage) generated at one end of the coil, and detects a zero cross point that is equal to the midpoint voltage. To obtain position information.

JP-A-3-207250 Japanese Patent Laid-Open No. 10-243865 Japanese Patent Laid-Open No. 11-75388

  FIGS. 1A to 1C are time charts showing how a zero-cross point is detected when pulse modulation driving is performed. FIG. 1A shows a pulse-modulated signal PWM, and FIG. 1B shows a phase voltage (hereinafter also referred to as a counter electromotive voltage Vu) and a midpoint voltage Vcom generated in a coil to be detected at a zero cross point. FIG. 6C shows a waveform diagram of the back electromotive force detection signal BEMF_EDGE. In FIGS. 1A to 1C, the voltage applied to the motor coil is controlled by pulse modulation in order to continuously change the current flowing in the motor coil in a sine wave shape or an arch shape. .

  As shown in FIG. 1B, the back electromotive voltage Vu generated in the coil that is the detection target of the zero cross point includes the timing of the transition from OFF to ON of the pulse-modulated signal shown in FIG. Alternatively, a noise component appears at the timing from on to off. Due to this noise component, the back electromotive force detection signal obtained by comparing the phase voltage Vu and the midpoint voltage Vcom repeats a high level and a low level, and the zero cross point is erroneously detected. The erroneous detection of the zero cross point is nothing but an erroneous detection of the rotor position, and causes problems such as deterioration in rotational accuracy and defective rotation.

  The present invention has been made in view of such circumstances, and a comprehensive object thereof is to provide a technique for accurately detecting a zero-cross point when a motor is driven by pulse modulation.

  One embodiment of the present invention relates to a motor drive circuit that drives a multiphase motor by supplying a drive current. This motor drive circuit is provided for each coil of a multi-phase motor, and has a plurality of switching circuits that apply a high-level or low-level voltage to one end of the connected coil, and a duty according to the target torque of the multi-phase motor. A pulse modulation signal generation unit that generates a pulse modulation signal whose ratio changes, and a counter electromotive voltage generated in at least one coil of a multiphase motor is compared with a midpoint voltage of the coil to detect a zero cross point, and a zero cross point Back electromotive force detection circuit that outputs a back electromotive force detection signal that reaches a predetermined level at the timing of, a pulse modulation signal from the pulse modulation signal generator, and a back electromotive detection signal from the back electromotive detection circuit, In addition to performing sequence control to switch the phase to be driven based on the signal, the high-speed signal included in the switching circuit to be driven is based on the pulse modulation signal. The phase of the two signals is compared by comparing the phase of the switching control unit that controls switching of at least one of the switch and the low-side switch, the back electromotive force detection signal from the back electromotive force detection circuit, and the reference signal that becomes a predetermined level at a predetermined timing. The phase adjustment unit that adjusts the duty ratio of the pulse modulation signal by feedback and the back electromotive force detection signal so that the error is minimized, and the frequency of the pulse modulation signal is an integral multiple of the frequency of the back electromotive detection signal. And a frequency adjusting unit for adjusting the frequency of the pulse modulation signal.

“Pulse modulation” uses a signal that changes the ratio between the high and low levels of the pulse, that is, the duty ratio, such as pulse width modulation (PWM), pulse frequency modulation (PFM), and pulse position modulation (PPM). Modulation.
According to this aspect, feedback is applied so that the frequency of the back electromotive detection signal and the frequency of the pulse modulation signal are integral multiples, and the timing of the zero cross point indicated by the back electromotive detection signal coincides with the timing of the reference signal. Therefore, by setting the timing at which the zero cross point is detected in the vicinity of the timing of the reference signal, the timing at the zero cross point can be accurately detected with a small delay.

The phase adjustment unit may include a phase error detection unit that detects a phase error between the reference signal and the back electromotive detection signal, and a torque adjustment unit that reflects the phase error detected by the phase error detection unit in the target torque. .
In this case, by adjusting the target torque so as to reduce the phase error, the duty ratio of the pulse modulation signal can be adjusted, and the timing at which the back electromotive signal becomes a predetermined level can be changed.

The pulse modulation signal generation unit may include a counter that repeats the count-up or count-down operation at a predetermined cycle shorter than the cycle of the back electromotive detection signal. The pulse modulation signal generation unit may generate a pulse modulation signal whose level changes according to the magnitude relationship between the count value of the counter and the value of the torque signal indicating the target torque. The frequency adjustment unit may set the counter so that the frequency of the pulse modulation signal is an integer multiple of the frequency of the back electromotive detection signal. “Setting a counter” means setting a count value to an initial value.
In this case, since the count value has a saw-tooth waveform, a pulse-modulated pulse-modulated signal can be generated by slicing with the torque signal value. Since the number of peaks of the sawtooth wave corresponds to the frequency of the pulse modulation signal, a desired operation can be realized by setting the counter so that an integer number of sawtooth waves are included in one cycle of the back electromotive force detection signal. .

  The frequency adjustment unit monitors a free-run counter that operates in the same cycle as the counter, and a count value P [i] of the free-run counter at a time when the back electromotive detection signal becomes a predetermined level for i (i is an arbitrary natural number). Then, the difference ΔP [i] = P [i] −P [with the count value P [i−1] of the free-run counter at the time when the back electromotive detection signal becomes a predetermined level for the (i−1) th time before that. i−1] is calculated each time, and the frequency error δF [i] indicated by the current difference ΔP [i] and the previous difference ΔP [i−1] = P [i−1] −P [i−2]. = A frequency error detector that calculates ΔP [i]-ΔP [i-1], and a counter set unit that sets a counter at a timing based on the frequency error δF [i] calculated by the frequency error detector. But you can.

The free-run counter repeats counting up or counting down at the same cycle without being set. When the motor rotates at a constant rotational speed, the time interval (that is, the frequency) at which the back electromotive force detection signal becomes a predetermined level is constant. Therefore, when the rotation speed of the motor is constant, the count value difference ΔP is constant. In other words, when the rotation speed of the motor changes, the monitored difference ΔP changes.
According to this aspect, it is possible to monitor fluctuations in the frequency of the back electromotive detection signal (the number of rotations of the motor), and the frequency of the pulse modulation signal is reversed by adjusting the timing at which the counter is set according to the fluctuation. It can be set to an integral multiple of the frequency of the origin detection signal.

In a motor drive circuit according to an aspect, a pulse modulation signal is reversed to a predetermined level during a detection period during an on period in which at least one of a high-side switch and a low-side switch included in the switching circuit is on. A mask signal generation unit that generates a mask signal that enables detection of the zero-cross point by the origin detection circuit, and a reference that generates a reference signal at a predetermined level during the detection period in which detection of the zero-cross point is enabled by the mask signal And a signal generation unit.
In this case, since the timing at which the back electromotive detection signal becomes a predetermined level can be shifted during a period in which the detection of the zero cross point is effective, the detection delay of the zero cross point can be reduced.

  The motor drive circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the motor drive circuit as one LSI, the circuit area can be reduced.

Another embodiment of the present invention is a disk device. This apparatus includes a spindle motor that rotates a disk and the above-described motor drive circuit that drives the spindle motor.
According to this aspect, since the zero cross point by the motor drive circuit can be detected with high accuracy, the spindle motor can be stably rotated.

  Yet another embodiment of the present invention is a motor driving method. This method is a motor driving method in which a driving current is supplied to a multiphase motor to drive the motor, and a step of generating a pulse modulation signal whose duty ratio changes according to a target torque of the multiphase motor, Comparing a back electromotive voltage generated in at least one coil with a midpoint voltage of the coil to detect a zero cross point, and generating a back electromotive detection signal having a predetermined level at the timing of the zero cross point; Performing sequence control for switching the phase to be driven based on the switching, controlling switching of at least one of the high-side switch and the low-side switch connected to the coil based on the pulse modulation signal, and within one cycle of the back electromotive detection signal Generating a reference signal at a predetermined level at a predetermined timing, a back electromotive detection signal and a reference signal The phase is compared and the duty ratio of the pulse modulation signal is adjusted by feedback so that the phase error between the two signals is minimized, and the frequency of the pulse modulation signal is an integer multiple of the frequency of the back electromotive detection signal Adjusting the frequency of the pulse modulated signal.

  According to the present invention, when the motor is driven by pulse modulation, the zero cross point can be accurately detected.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A and the member B are connected” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical connection. The case where it is indirectly connected through another member that does not affect the state is also included.

  FIG. 2 is a block diagram showing a configuration of the motor drive circuit 100 according to the embodiment. The motor drive circuit 100 controls the rotation by supplying a drive current to a sensorless brushless DC motor (hereinafter simply referred to as “motor 110”). In the present embodiment, the motor 110 to be driven is a three-phase DC motor including U-phase, V-phase, and W-phase coils Lu, Lv, and Lw.

  The motor driving circuit 100 includes switching circuits 10u, 10v, and 10w, which are collectively referred to as a switching circuit 10, a back electromotive force detection circuit 20, a switching control unit 30, and a pulse width modulation signal generation unit (hereinafter referred to as a PWM signal generation unit). 50. The motor drive circuit 100 is integrally integrated as a functional IC on one semiconductor substrate. For example, the motor drive circuit 100 PWM-drives the multiphase motor 110 so that a desired torque can be obtained. Furthermore, the duty ratio of the PWM drive may be changed so that the current flowing through the coil of each phase becomes an arch shape or a sine wave shape by the 180-degree energization method.

  The switching circuits 10u, 10v, and 10w are provided for each of the coils Lu, Lv, and Lw of the motor 110. The switching circuit 10u includes, for example, a high side switch and a low side switch (not shown) connected in series between a power supply voltage and a ground potential, and a connection point between the two switches is connected to one end of the coil Lu. The drive signal DRV_H (U) and the drive signal DRV_L (U) are input to the control terminals (gates) of the high side switch and the low side switch, respectively. The switching circuit 10u applies, to one end of the connected coil Lu, a high level voltage (Vdd) when the high side switch is on, and a low level voltage (0V) when the low side switch is on. . Further, the high-side switch and the low-side switch are simultaneously turned off to set the high impedance state. The same applies to the V phase and the W phase.

  The back electromotive force detection circuit 20 compares the back electromotive voltage generated in at least one coil of the motor 110 with the midpoint voltage of the coil to detect a zero cross point, and at a predetermined level at the timing of the zero cross point where the two voltages cross. A back electromotive force detection signal BEMF_EDGE that is (hereinafter referred to as high level) is output. In the present embodiment, the back electromotive force detection circuit 20 generates a back electromotive force detection signal BEMF_EDGE by monitoring the back electromotive voltage Vu and the midpoint voltage Vcom generated in the U-phase coil Lu. The generated back electromotive detection signal BEMF_EDGE is output to the drive timing generation unit 32, the window generation unit 40, and the PWM signal generation unit 50. Details of the back electromotive force detection circuit 20 will be described later.

  The PWM signal generation unit 50 generates a pulse width modulation signal (hereinafter referred to as a PWM signal Spwm) whose duty ratio changes at least according to the target torque of the motor 110. The PWM signal generation unit 50 compares the level of a triangular wave or sawtooth wave periodic signal Sosc with a signal TRQ indicating a torque (hereinafter referred to as a torque signal) TRQ, and the high level and low level of the PWM signal Spwm according to the magnitude relationship. Change the period. Note that the PWM signal generation unit 50 may be configured by either a digital circuit or an analog circuit. Hereinafter, a configuration using a digital circuit will be described as an example, but replacement with an analog circuit having an equivalent function is possible.

  The PWM signal generation unit 50 generates a PWM signal Spwm by synthesizing a target torque and a sinusoidal or arched control waveform in order to gently change the coil current flowing through the coils Lu, Lv, and Lw. Also good.

  The switching control unit 30 receives the PWM signal Spwm from the PWM signal generation unit 50 and the back electromotive detection signal BEMF_EDGE from the back electromotive detection circuit 20. The switching control unit 30 performs sequence control for switching driving phases (U, V, W) based on the back electromotive detection signal BEMF_EDGE. Further, switching control is performed on at least one of the high-side switch MH and the low-side switch ML included in the switching circuit 10 based on the PWM signal Spwm.

In order to realize this function, the switching control unit 30 includes a drive timing generation unit 32, a drive signal synthesis circuit 34, and a window generation unit 40.
The drive timing generation unit 32 receives the back electromotive detection signal BEMF_EDGE and generates a drive signal DRV for controlling an on / off state sequence of the plurality of switching circuits 10u, 10v, and 10w. For example, the drive signal DRV is a signal having a cycle that is 1/6 of the cycle Tp1 of the back electromotive detection signal BEMF_EDGE. The drive signal DRV may be generated according to a method such as 180 degree energization or 120 degree energization.

  The drive signal synthesis circuit 34 synthesizes the drive signal DRV and the PWM signal Spwm to output drive signals DRV_H (U, V, W) and DRV_L (U, V, W), and the switching circuits 10u, 10v, 10w. Control the state of Specifically, the drive signal synthesis circuit 34 performs switching control of at least one of the high-side switch MH and the low-side switch ML included in the plurality of switching circuits 10u, 10v, and 10w by the PWM method based on the PWM signal Spwm.

  Prior to the detection of the zero cross point by the back electromotive force detection circuit 20, the window generator 40 stops the switching of the switching circuit 10u connected to the coil Lu that is the target of back electromotive force detection and sets the window signal to high impedance. WINDOW is generated. In the present embodiment, the predetermined level is a high level. When performing 120-degree energization or the like, if there is a period during which no current flows in the coil Lu that is the target of back electromotive force detection, the window generator 40 can be omitted.

  The window signal WINDOW is output to the drive signal synthesis circuit 34. During the period when the window signal WINDOW is at a high level, the drive signal synthesis circuit 34 stops switching of the switching circuit 10u connected to the terminal where the back electromotive voltage Vu to be monitored for detection of the zero cross point is generated, and the high impedance Set to state. That is, during the period in which the window signal WINDOW is at a high level, a phase that is not intentionally driven is set in order to detect the zero cross point. In the present embodiment, in the non-driving period Tp3, the U phase is set to a phase that is not driven.

  The overall operation of the motor drive circuit 100 configured as described above will be described. 3A to 3L are time charts showing the operation of the motor drive circuit 100 according to the embodiment. The vertical and horizontal axes in FIGS. 1A to 1L are enlarged or reduced as appropriate for easy understanding, and the waveforms shown are also simplified for easy understanding. Yes. FIGS. 4A to 4C are waveforms showing driving states of the U-phase, V-phase, and W-phase coils Lu, Lv, and Lw by the switching circuits 10u, 10v, and 10w. FIG. 6D shows the back electromotive detection signal BEMF_EDGE detected by the back electromotive detection circuit 20, FIG. 5E shows the drive signal DRV generated by the drive timing generation unit 32, and FIG. The window signal WINDOW generated by the window generator 40 is shown. Further, (g) to (l) in the figure show drive signals DRV_H and DRV_L for the high-side switch MH and the low-side switch ML of the switching circuits 10u to 10w.

  As shown in FIGS. 3A to 3C, in the present embodiment, the drive current is driven so as to have an arch waveform. However, the present invention is not limited to this, and may be a sine wave as described above. Furthermore, the driving current may be constant. In the present embodiment, the back electromotive force detection signal BEMF_EDGE is generated for each zero cross point where the back electromotive voltage Vu intersects the midpoint voltage Vcom as shown in FIG. The drive timing generator 32 generates the drive signal DRV shown in FIG. 5E, which is 1/6 times the period Tp1 of the back electromotive detection signal BEMF_EDGE. As shown in the figure, the drive signal DRV may be given a delay Td with respect to the back electromotive force detection signal BEMF_EDGE. By adjusting the delay Td, the motor drive is optimized.

  The drive signal synthesizing circuit 34 is based on the drive signal DRV generated by the drive timing generation unit 32, and drives signals DRV_H (U, V, W), DRV_L (U, V) for controlling on / off of the switching circuits 10u to 10w. , W). This driving sequence is appropriately set according to the energization angle and the like.

  In the drive signal DRV_HU shown in FIG. 3G, the high level corresponds to the on state of the high side switch of the switching circuit 10u, and the low level corresponds to the off state. The same applies to the drive signals DRV_H (V, W) and DRV_L (U, V, W) shown in FIGS. Further, the ON state of at least one of the high side switch and the low side switch is pulse width modulated so as to obtain the drive waveforms shown in FIGS. The side switch or the low side switch alternately turns on and off at a high frequency based on the PWM signal.

  Each time the back electromotive detection signal BEMF_EDGE is output, the drive signal synthesis circuit 34 changes the on / off states of the drive signals DRV_H and DRV_L of the switching circuits 10u to 10w according to a predetermined drive sequence.

  The window signal WINDOW shown in FIG. 5F is set to the high level by the window generator 40 prior to the time when the zero cross point occurs. The drive signal synthesizing circuit 34 sets the drive signals DRV_HU and DRV_LU output to the switching circuit 10u to a low level while the window generation unit 40 is at a high level, and turns off the high-side switch and the low-side switch to a high impedance state. In the same figure (g) and (j), the period during which the high impedance state is set in order to detect the zero cross point is indicated by hatching. When the window signal WINDOW becomes high level and one end of the coil Lu is set to a high impedance state, the zero cross point can be detected, and the back electromotive detection signal BEMF_EDGE is generated.

The above is the general configuration and operation of the motor drive circuit 100. Next, the back electromotive detection circuit 20 and the PWM signal generation unit 50 will be described.
FIG. 4 is a block diagram illustrating configurations of the back electromotive force detection circuit 20 and the PWM signal generation unit 50 according to the embodiment. FIGS. 5A to 5H are time charts showing waveforms of signals generated by the back electromotive detection circuit 20 and the PWM signal generation unit 50. FIG.

  The back electromotive voltage Vu, the midpoint voltage Vcom, and the mask signal MSK are input to the back electromotive force detection circuit 20 according to the present embodiment. The mask signal MSK is a signal for setting a detection period Tdet in which detection of the zero cross point is valid, and detection of the zero cross point is valid only during a period in which the mask signal MSK is at a predetermined level (low level). The mask signal MSK is generated by a mask signal generation unit 66 described later.

  The back electromotive detection circuit 20 includes a comparator 22, an AND gate 23, and a flip-flop 24. The comparator 22 compares the back electromotive voltage Vu and the midpoint voltage Vcom, and outputs a comparison signal Scmp corresponding to the magnitude relationship. The AND gate 23 outputs a logical product of the comparison signal Scmp and the logical inversion (* MSK) of the mask signal MSK. The flip-flop 24 latches the output of the AND gate 23 based on the system clock CK. According to the back electromotive force detection circuit 20 configured as described above, when the mask signal MSK becomes Vu> Vcom in the low level detection period Tdet, the back electromotive force detection signal BEMF_EDGE becomes high level and the zero cross point is detected. Since Vu> Vcom other than the detection period Tdet is masked, the zero cross point is not detected.

  A signal TRQ instructing torque is input to the PWM signal generation unit 50. The PWM signal generation unit 50 generates a PWM signal Spwm whose pulse width (duty ratio) changes according to the torque signal TRQ. Further, the back electromotive force detection signal BEMF_EDGE generated by the back electromotive force detection circuit 20 is input to the PWM signal generation unit 50.

  The PWM signal generation unit 50 adjusts the duty ratio and phase of the PWM signal Spwm by feedback using the frequency and phase of the back electromotive detection signal BEMF_EDGE as feedback amounts. Hereinafter, this feedback will be described.

  The PWM signal generation unit 50 includes a frequency adjustment unit 52, a pulse generation unit 60, and a phase adjustment unit 70. Each block has the following functions.

  The pulse generator 60 generates three signals: a PWM signal Spwm, a mask signal MSK, and a reference signal REF. The pulse generator 60 includes a counter 62, a reference signal generator 64, a mask signal generator 66, and a torque controller 68.

  The torque control unit 68 generates a PWM signal Spwm having a duty ratio according to the torque signal TRQ input from the outside. The system clock CK is input to the counter 62. When the system clock CK is set at a certain timing, counting up (or counting down) is started, and this is repeated at a predetermined frequency (period). The count value CNT generated in this way is a sawtooth wave. The torque control unit 68 compares the count value of the counter 62 with the value of the target torque signal TRQ2, and generates a PWM signal Spwm that is high level when TRQ2> CNT and low level when TRQ2 <CNT. While the PWM signal Spwm is at a high level, the switching circuit 10 applies a power supply voltage or a ground voltage to one end of each of the coils Lu to Lw. Hereinafter, a period in which the PWM signal Spwm is at a high level is referred to as an on period Ton.

Further, the reference signal generation unit 64 generates a reference signal REF that becomes a predetermined level (high level) at every predetermined timing. The reference signal REF defines the timing at which the phase of the back electromotive detection signal BEMF_EDGE should match.
The mask signal generation unit 66 generates a mask signal MSK. As described above, the mask signal MSK is a signal for setting the zero-cross point detection period Tdet, and is at a low level during the detection period Tdet during the ON period Ton of the PWM signal Spwm. In order to generate the mask signal MSK, the mask signal generation unit 66 may include a counter (not shown) that starts counting when the PWM signal Spwm transitions to a high level. In this case, the mask signal MSK may be set to the low level when the count value reaches the first predetermined value, and then the mask signal MSK may be set to the high level when the count value reaches the second predetermined value.

  The phase adjustment unit 70 receives the back electromotive detection signal BEMF_EDGE from the back electromotive detection circuit 20 and the reference signal REF generated by the reference signal generation unit 64. The phase adjustment unit 70 compares the phases of the two signals, and adjusts the duty ratio of the PWM signal Spwm by feedback so that the phase error is minimized.

  In order to realize this function, the phase adjustment unit 70 includes a phase error detection unit 71 and a torque adjustment unit 72. The phase error detector 71 detects a phase error Δφ between the reference signal REF and the back electromotive detection signal BEMF_EDGE, and outputs a phase error signal PE indicating the phase error Δφ. The phase error signal PE may be a value obtained by counting the time of the phase error Δφ with the system clock CK.

  The torque adjustment unit 72 receives the phase error signal PE output from the phase error detection unit 71 and the torque signal TRQ input from the outside. The torque adjustment unit 72 reflects the phase error Δφ indicated by the phase error signal PE in the target torque signal TRQ2. For example, when the phase of the back electromotive detection signal BEMF_EDGE is delayed with respect to the reference signal REF, the torque adjustment unit 72 decreases the target torque signal TRQ2 in order to increase the torque. Conversely, when the phase of the back electromotive detection signal BEMF_EDGE advances with respect to the reference signal REF, the target torque signal TRQ2 is increased in order to decrease the torque. As a result of the feedback, the phase of the back electromotive detection signal BEMF_EDGE approaches the phase of the reference signal REF.

The torque adjusting unit 72 may be configured to be able to adjust parameters corresponding to the loop gain and the band of the loop filter in order to reflect the phase error signal PE in the target torque signal TRQ2. For example, when the torque adjustment unit 72 multiplies the phase error signal PE by a coefficient and adds it to the torque signal TRQ, it is desirable that the coefficient can be adjusted. This coefficient corresponds to the loop gain.
Further, when the phase error signal PE is delayed by a delay time and added to the torque signal TRQ by a predetermined time, it is desirable that the delay time or the predetermined time can be adjusted. These correspond to the band of the loop filter.

  The frequency adjustment unit 52 adjusts the frequency of the PWM signal Spwm so that the frequency of the PWM signal Spwm is an integral multiple of the frequency of the back electromotive detection signal BEMF_EDGE.

  The frequency adjustment unit 52 has a function of detecting the rotation speed of the motor 110, that is, the frequency of the back electromotive detection signal BEMF_EDGE. The frequency adjustment unit 52 includes a free-run counter 54, a frequency error detection unit 56, and a counter set unit 58. The detection of the frequency of the back electromotive detection signal BEMF_EDGE is executed by the free run counter 54 and the frequency error detector 56.

  The free-run counter 54 receives the system clock CK and operates at the same cycle as the counter 62. Unlike the counter 62, the free-run counter 54 repeats counting up or counting down in the same cycle without being set.

The frequency error detector 56 receives the back electromotive detection signal BEMF_EDGE and the count value FRCNT of the free-run counter 54. The frequency error detection unit 56 monitors the count value of the free-run counter 54 at the time when the back electromotive detection signal BEMF_EDGE becomes high level every time. The count value for the i-th (i is an arbitrary natural number) is written as P [i].
The frequency error detector 56 counts the current count value P [i] and the count value P [i−1] of the free-run counter 54 at the time when the back electromotive detection signal becomes a predetermined level for the previous (i−1) th time. The difference from
ΔP [i] = P [i] −P [i−1]
Is calculated every time. The difference ΔP of the count value P [i] is data indicating the fluctuation of the cycle time of the back electromotive detection signal BEMF_EDGE, that is, the fluctuation of the frequency.

The frequency error detection unit 56 determines the difference between the current difference ΔP [i] and the previous difference ΔP [i−1] = P [i−1] −P [i−2] δF [i] = ΔP [i ] -ΔP [i-1]
Is calculated. δF [i] is data indicating an error in frequency of the back electromotive detection signal BEMF_EDGE, in other words, an error in cycle time. Hereinafter, δF [i] is referred to as frequency error data. The counter setting unit 58 receives the frequency error data δF [i] and sets the counter 62 according to the value.

  When the motor 110 rotates at a constant rotational speed, the time interval at which the back electromotive detection signal BEMF_EDGE is at a high level is constant. Therefore, when the rotation speed of the motor 110 is constant, the count value P [i] increases (or decreases) with a predetermined width every rotation, and δF [i] = ΔP [i] −ΔP [i− 1] is a constant value. If the rotation speed of the motor 110 increases, δF [i] increases (or decreases), and if the rotation speed of the motor decreases, δF [i] decreases (or increases).

For example, four consecutive count values are P [i−2] = 8, P [i−1] = 12, P [i] = 16, P [i + 1] = 18, and P [i + 2] = 22. Suppose there was.
At this time, each difference is
ΔP [i−1] = 4
ΔP [i] = 4
ΔP [i + 1] = 2
ΔP [i + 2] = 4
And
δF [i] = 0
δF [i + 1] = − 2
δF [i + 2] = 2
It becomes.

When δF [i] is 0, the counter setting unit 58 sets the counter 62 at the same timing as the previous time. When δF [i] is negative, the counter setting unit 58 delays the setting timing from the previous time, and δF [i] is positive. At the time of, set timing earlier than the previous time.
More specifically, when δF [i] = 0, the counter setting unit 58 sets at the same timing as the previous time. When δF [i + 1] = − 2, the set timing is advanced by two system clocks CK from the previous set timing. When δF [i + 1] = 2, the set timing is delayed by two clocks from the previous set timing.

  Hereinafter, the operation of the motor drive circuit 100 will be described in detail with reference to FIGS. The vertical axis, the horizontal axis, and each waveform in the figure are simplified for easy understanding, and the frequency and amplitude are different from the actual waveform.

  Before the time t0 is a non-detection period, and the power supply voltage Vdd and the ground voltage are alternately applied to the U-phase coil. At time t0, detection of a zero cross point is instructed by the window generator 40, and the U-phase coil Lu is set to high impedance. In the time chart of the figure, time t0 and time t2 are the timing of setting the counter 62, and the section t0 to t2 is associated with one cycle of the back electromotive detection signal BEMF_EDGE.

  Reference is made to FIGS. The count value CNT by the counter 62 is a sawtooth wave having a period Tx. The torque control unit 68 compares the count value CNT with the value of the target torque signal TRQ2, and generates a PWM signal Spwm that is high when TRQ2> CNT and low when TRQ2 <CNT. The lower the target torque signal TRQ2, the larger the duty ratio (Ton / Tx) of the PWM signal Spwm, and the motor 110 is driven with higher torque.

  As shown in FIG. 6C, the mask signal MSK generated by the mask signal generator 66 is at a low level during the detection period Tdet of the on-time Ton of the PWM signal Spwm. As shown in FIG. 4D, the reference signal REF becomes high level after a predetermined time τ has elapsed after the counter 62 is set and starts counting up. FIGS. 5E to 5G show the generation of the back electromotive detection signal BEMF_EDGE by the phase adjustment unit 70. FIG. The back electromotive detection signal BEMF_EDGE becomes high level at time t1 and time t3.

  The phase error detector 71 detects a phase error Δφ between the back electromotive detection signal BEMF_EDGE and the reference signal REF, and generates a phase error signal PE corresponding to the phase error Δφ. The torque adjusting unit 72 combines the feedback amount corresponding to the phase error signal PE with the external torque signal TRQ to generate a target torque signal TRQ2. As shown in FIGS. 5D and 5G, when the back electromotive detection signal BEMF_EDGE is slower, feedback is applied so that the target torque signal TRQ2 is lowered, in other words, the torque is increased.

  When the torque increases, the counter electromotive voltage Vu rises earlier than the previous time when the zero cross point is detected in the next cycle. As a result, since the zero cross point occurs earlier in time, the timing of the back electromotive detection signal BEMF_EDGE approaches the timing of the reference signal REF.

  That is, the torque of the motor 110 is controlled by the phase adjusting unit 70 so that the timing of the zero cross point, that is, the phase error Δφ between the back electromotive detection signal BEMF_EDGE and the reference signal REF approaches zero.

  FIG. 5H shows the count value FRCNT of the free-run counter 54. The count values at times t1 and t3 when the back electromotive detection signal BEMF_EDGE becomes high level are indicated by P [i-1] and P [i], respectively. The frequency error detector 56 monitors the count value P [i] every cycle and calculates a difference ΔP [i] from the previous count value P [i−1]. The frequency error detector 56 calculates a frequency error δF [i] between the calculated difference ΔP [i] and the previous difference ΔP [i−1]. The counter setting unit 58 changes the timing for setting the counter 62 in the next cycle according to the frequency error δF [i].

  By the processing of the frequency adjusting unit 52, an integer number of sawtooth waves are included in the period from time t0 to time t2. The period of the sawtooth wave immediately before time t2 is smaller than Tx, but this is also one sawtooth wave. In other words, the state where the frequency of the PWM signal Spwm is an integral multiple of the frequency of the back electromotive detection signal BEMF_EDGE is realized by creating a state where there is no sawtooth wave increasing across the period.

  The configuration and operation of the motor drive circuit 100 according to the embodiment have been described above. According to the motor drive circuit 100 according to the present embodiment, the timing at which the back electromotive detection signal BEMF_EDGE becomes high level, that is, the timing at which the zero cross point occurs can be matched with the predetermined reference timing. Therefore, by providing the detection timing (in the embodiment, the detection period Tdet) in the time zone including the reference timing, the back electromotive detection can be performed reliably and with a small delay. By performing the back electromotive force detection with high accuracy, the rotation of the motor 110 can be controlled with high accuracy.

  From another point of view, the motor drive circuit 100 according to the present embodiment does not detect the back electromotive force in synchronization with the timing at which the zero cross point occurs, but causes the zero cross point to occur at the detection timing. Drive the motor. As a result, problems such as occurrence of a zero-cross point at an unintended timing and a delay in detection thereof can be solved, and high-precision detection can be realized.

  Finally, an example of application of the motor drive circuit 100 according to the present embodiment will be described. FIG. 6 is a block diagram showing a configuration of a disk device 200 on which the motor drive circuit 100 of FIG. 2 is mounted. The disk device 200 is a unit that performs recording and reproduction processing on an optical disk such as a CD or a DVD, and is mounted on an electronic device such as a CD player, a DVD player, or a personal computer. The disk device 200 includes a pickup 210, a signal processing unit 212, a disk 214, a motor 110, and a motor driving circuit 100.

  The pickup 210 writes desired data by irradiating the disk 214 with a laser, or reads the data written on the disk 214 by reading reflected light. The signal processing unit 212 performs necessary signal processing such as amplification processing, A / D conversion, or D / A conversion on data read and written by the pickup 210. The motor 110 is a spindle motor provided for rotating the disk 214. Since the disk device 200 as shown in FIG. 6 is particularly required to be downsized, a sensorless type that does not use a Hall element or the like is used as the motor 110. The motor drive circuit 100 according to the present embodiment can be suitably used to stably drive such a sensorless spindle motor.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  In the embodiment, the case of driving a three-phase motor has been described. However, the present invention can also be suitably used for driving a sensorless motor other than the three-phase motor. For example, a five-phase motor may be used. In the embodiment, the case where the zero-cross point is detected by comparing the U-phase counter electromotive voltage Vu with the midpoint voltage Vcom has been described, but the present invention is not limited to this. For example, the back electromotive force detection circuit 20 may be provided for each of the U phase, the V phase, and the W phase to generate the back electromotive force detection signal BEMF_EDGE.

  Further, when the rotation speed (torque) of the motor 110 in a steady state is fixed, it is not necessary to monitor the rotation speed of the motor, and therefore the free-run counter 54 and the frequency error detection unit 56 can be omitted. In this case, the counter setting unit 58 may set the timing for setting the counter 62 based on the value of the torque signal TRQ instructing the rotation speed of the motor 110.

  In the embodiment, the zero cross point is detected by detecting the state where Vu> Vcom in the process of increasing the phase voltage Vu, but the present invention is not limited to this, and the back electromotive force detection circuit 20 may detect the zero cross point by detecting a state where Vu <Vcom in the process of decreasing the phase voltage Vu.

  In the embodiment, the detection timing of the zero cross point is set by matching the detection period Tdet defined by the mask signal MSK with the timing of the reference signal REF. The present invention is not limited to this. For example, the AND gate 23 in FIG. 4 may be omitted without generating the mask signal MSK. In this case, the system clock CK input to the clock terminal of the flip-flop 24 of FIG. 4 may be input to the flip-flop 24 only near the reference signal REF.

  In the embodiment, the case where the motor is driven by the PWM method with 180 degree energization has been described. However, the present invention is not limited to this, and the present invention is widely used for a motor driving circuit that adopts a pulse modulation method. Can do.

  The high-level and low-level logic settings of the signals described in the embodiment are merely examples, and various modifications can be considered for the configuration of the logic circuit block, and such modifications are also included in the scope of the present invention.

  In the embodiment, the case where the present invention is realized by a digital circuit has been described, but part or all of the digital circuit may be replaced with an analog circuit having an equivalent function.

  Although the present invention has been described based on the embodiments, the embodiments merely illustrate the principle and application of the present invention, and the embodiments are intended to include the idea of the present invention defined in the claims. Many modifications and changes in arrangement are possible within the range not leaving.

FIGS. 1A to 1C are time charts showing how a zero-cross point is detected when pulse modulation driving is performed. It is a block diagram which shows the whole structure of the motor drive circuit which concerns on embodiment. 3A to 3L are time charts showing the operation of the motor drive circuit according to the embodiment. It is a block diagram which shows the structure of the back electromotive force detection circuit which concerns on embodiment, and a PWM signal generation part. FIGS. 5A to 5H are time charts showing waveforms of signals generated by the back electromotive force detection circuit and the PWM signal generation unit. FIG. 3 is a block diagram showing a configuration of a disk device on which the motor drive circuit of FIG. 2 is mounted.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 Motor drive circuit, 10 Switching circuit, 20 Back electromotive detection circuit, 22 Comparator, 23 AND gate, 24 Flip-flop, 30 Switching control part, 32 Drive timing generation part, 34 Drive signal synthetic | combination circuit, 40 Window generation part, 50 PWM Signal generating unit 52 frequency adjusting unit 54 free run counter 56 frequency error detecting unit 58 counter setting unit 60 pulse generating unit 62 counter 64 reference signal generating unit 66 mask signal generating unit 68 torque control unit 70 phase adjustment unit, 71 phase error detection unit, 72 torque adjustment unit, 110 motor, 210 pickup, 212 signal processing unit, 214 disk.

Claims (8)

A motor drive circuit that drives a multiphase motor by supplying a drive current,
A plurality of switching circuits that are provided for each coil of the multiphase motor and apply a high-level or low-level voltage to one end of the connected coils;
A pulse modulation signal generation unit that generates a pulse modulation signal whose duty ratio changes according to a target torque of the multiphase motor;
The counter electromotive voltage generated in at least one coil of the multiphase motor is compared with the midpoint voltage of the coil to detect a zero cross point, and outputs a counter electromotive detection signal that reaches a predetermined level at the timing of the zero cross point. A detection circuit;
While receiving the pulse modulation signal from the pulse modulation signal generation unit and the back electromotive detection signal from the back electromotive detection circuit, performing sequence control to switch the phase to be driven based on the back electromotive detection signal, A switching control unit that controls switching of at least one of a high-side switch and a low-side switch included in the switching circuit to be driven based on the pulse modulation signal;
The back electromotive detection signal from the back electromotive detection circuit is compared with the phase of a reference signal that becomes a predetermined level at a predetermined timing, and the pulse modulation signal is fed back by feedback so that the phase error between the two signals is minimized. A phase adjuster for adjusting the duty ratio;
A frequency adjusting unit that adjusts the frequency of the pulse modulation signal so that the frequency of the pulse modulation signal is an integral multiple of the frequency of the back electromotive detection signal;
A motor drive circuit comprising: The phase adjustment unit includes:
A phase error detector for detecting a phase error between the reference signal and the back electromotive detection signal;
A torque adjustment unit that reflects the phase error detected by the phase error detection unit in the target torque;
The motor drive circuit according to claim 1, comprising: The pulse modulation signal generation unit includes a counter that repeats count-up or count-down operations at a predetermined cycle shorter than the cycle of the back electromotive detection signal, and the magnitude relationship between the count value by the counter and the value of the torque signal indicating the target torque Generating the pulse modulated signal whose level changes in response,
2. The motor drive circuit according to claim 1, wherein the frequency adjustment unit sets the counter so that a frequency of the pulse modulation signal is an integral multiple of a rotation speed of the motor. The frequency adjusting unit includes:
A free-run counter that operates in the same cycle as the counter;
The count value P [i] of the free-run counter at the time when the back electromotive detection signal becomes a predetermined level is monitored i (i is an arbitrary natural number), and the back electromotive force is detected the previous (i-1). The difference ΔP [i] = P [i] −P [i−1] from the count value P [i−1] of the free-run counter at the time when the detection signal becomes a predetermined level is calculated every time, and the current difference ΔP is calculated. [I] and a frequency error δF [i] = ΔP [i] −ΔP [i−1] represented by the previous difference ΔP [i−1] = P [i−1] −P [i−2]. A frequency error detector to be calculated;
A counter setting unit that sets the counter at a timing based on the frequency error δF [i] calculated by the frequency error detection unit;
The motor drive circuit according to claim 3, comprising: The zero-crossing point by the back electromotive force detection circuit becomes a predetermined level during the detection period during the ON period in which the pulse modulation signal is a level indicating at least one of the high-side switch and the low-side switch included in the switching circuit. A mask signal generator for generating a mask signal for enabling detection of
A reference signal generation unit that generates the reference signal at a predetermined level during a detection period in which detection of a zero cross point is enabled by the mask signal;
The motor drive circuit according to claim 1, further comprising:   5. The motor drive circuit according to claim 1, wherein the motor drive circuit is integrated on a single semiconductor substrate. A spindle motor that rotates the disk;
The motor drive circuit according to any one of claims 1 to 4, which drives the spindle motor;
A disk device comprising: A motor driving method for driving by supplying a driving current to a multiphase motor,
Generating a pulse modulation signal whose duty ratio changes according to the target torque of the multiphase motor;
Comparing a back electromotive voltage generated in at least one coil of the multiphase motor with a midpoint voltage of the coil to detect a zero cross point, and generating a back electromotive detection signal having a predetermined level at the timing of the zero cross point; ,
Performing sequence control to switch the driving phase based on the back electromotive detection signal, and switching control of at least one of a high side switch and a low side switch connected to the coil based on the pulse modulation signal;
Generating a reference signal having a predetermined level at a predetermined timing within one cycle of the back electromotive detection signal;
Comparing the phase of the back electromotive detection signal and the reference signal and adjusting the duty ratio of the pulse modulated signal by feedback so that the phase error between the two signals is minimized;
Adjusting the frequency of the pulse modulated signal so that the frequency of the pulse modulated signal is an integral multiple of the frequency of the back electromotive detection signal;
A motor driving method comprising:

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