JP4955024B2 - Reference clock frequency adjusting method and relay device - Google Patents

Description

  The present invention relates to a reference clock frequency adjusting method and a relay device.

  Currently, Ethernet (registered trademark) technology is widely used. This Ethernet technology is used not only for communication but also for video distribution services. Furthermore, it is expected to realize a long-time distribution service for real-time video such as existing television broadcasting by using this Ethernet technology.

  In such a packet switching technique represented by Ethernet, natural packets are transmitted in bursts. However, in order to realize a video distribution service, it is necessary to reduce arrival jitter due to packet burstiness on the receiving side. The reason is that if the burst property is small, the buffer memory can be made small, and as a result, the possibility that real-time property can be realized increases.

  That is, when the receiving apparatus includes a large amount of buffer memory, burst tolerance is improved, but on the other hand, the packet transmission delay due to the buffer is increased, and the real-time property is lost.

  Therefore, in order to realize a video distribution service pursuing real-time characteristics, it is desirable to transmit packets including video information to the end user's home at a fixed packet rate with small jitter. As a result, the buffer amount can be reduced, and the delay time of the network is also reduced.

  On the other hand, Ethernet technology is normally used between devices that are not synchronized. For this reason, the reference clock frequency deviation between apparatuses is absorbed by adjusting the interval length between packets. The reference clock frequency deviation results in a transmission clock frequency deviation.

  For example, in 10 gigabit Ethernet (10 GbE), if the transmission rate range defined in the IEEE 802.3-2005 standard is satisfied, even if there is a difference in the reference clock frequency between devices, the interval length between packets is set. It is stipulated that it can be operated without discarding packets by adjusting in units of 4 bytes. In other words, as long as Ethernet technology is used in an asynchronous network, adjustment of the interval length between packets always occurs. In other words, the occurrence of packet arrival jitter due to the adjustment of the interval length between packets is inevitable, and it is difficult to realize real-time performance. The above transmission rate range is 10.3125 Gbps (Giga bit per second) ± 100 ppm (parts per million).

  However, even when using the Ethernet technology, the reference clock frequency or the transmission clock frequency (hereinafter, both are collectively referred to as a clock frequency) of each relay apparatus is synchronized so that adjustment of the interval length between packets does not occur. There is an increasing demand for reducing packet arrival jitter. This is because there is a movement to use the Ethernet technology even in a video distribution service with a high real-time requirement against the background of building a communication infrastructure by using an inexpensive Ethernet technology.

  As a clock frequency synchronization method, an existing telephone network employs a slave synchronization system in which a clock line is arranged throughout the country to transmit a clock signal and each transmission device pulls in the clock signal to synchronize the clock frequency. However, packet-switched networks such as Ethernet based on an asynchronous network are already widely used. Therefore, it is difficult to prepare a new clock line.

  In such an asynchronous network, as a method of adjusting the clock frequency deviation between the devices, a method of adjusting the clock frequency deviation between the devices by using a buffer memory provided in the device has been proposed (for example, Non-Patent Document 2).

  Specifically, a certain relay device and receiving device constantly monitor the amount of data stored in its own buffer memory. When the data amount exceeds a certain amount or exceeds a certain amount, it is determined that its own clock frequency is relatively slower than that of the transmission side device, and its own clock frequency is increased. On the other hand, if the amount of data is less than or equal to a certain amount or falls below a certain amount, it is determined that its own clock frequency is relatively fast compared to the transmitting side device, and its own clock frequency is lowered. .

IEEE Std802.3-2005

R. P. Singh and S. H. LEE, “ADAPTIVE CLOCK SYNCHRONIZATION SCHEMES FOR REAL-TIME TRAFFIC IN BROADBAND PACKET NETWORKS,” IEEE, 1988.

  As described above, in order to construct a low-delay and low-jitter video distribution network that pursues real-time characteristics using Ethernet technology, clock frequency synchronization between relay devices is indispensable.

  For example, the clock frequency adjusting method described in Non-Patent Document 2 can be realized by a relatively simple technical mechanism. However, according to the clock frequency adjusting method described in Non-Patent Document 2, packets are stored in a buffer memory in each device in principle for a certain period of time. For this reason, there is a problem that a delay time unrelated to the packet arrival burstiness reduction occurs.

  In other words, the clock frequency adjustment method described in Non-Patent Document 2 newly requires clock accumulation for clock frequency synchronization, which is irrelevant to reducing the burstiness of packet arrival in each device. As a result, there is a problem that it is difficult to realize real-time performance in spite of aiming at real-time video distribution using a packet switching network such as Ethernet.

  Therefore, in order to construct a low-delay and low-jitter video distribution network that pursues real-time performance using Ethernet technology, it is possible to achieve clock frequency synchronization between each relay device, and in each relay device A new method for reducing the amount of buffer is required.

  The present invention has been made under such a background, and an object of the present invention is to provide a reference clock frequency adjusting method and a relay device that can achieve clock frequency synchronization while suppressing a buffer amount to be small.

  A first aspect of the present invention is a reference clock frequency adjustment method. That is, the reference clock frequency adjusting method according to the present invention is the reference clock frequency adjusting method for a relay device that relays transmitted packets, and detects the interval length between packets arriving from a transmitting device upstream of the relay device. Detected by processing of an inter-packet interval length detecting step, an inter-packet interval length detecting step for detecting an inter-packet interval length detecting step, and an inter-arrival packet interval length detecting step. A clock adjustment step of adjusting the reference clock frequency of the relay device according to the difference between the interval length between packets and the interval length between packets detected by the processing of the interval length detection step between transmission packets.

  At this time, the number of parallels when the serial data of packets arriving at the relay device is processed in the relay device is L, and the interval between packets is used so that the relay device absorbs the deviation of the reference clock frequency from other devices. When the time interval between two adjacent time points whose lengths are adjusted is T seconds, and the total interval length between packets expanded in T seconds is N bits, the processing of the clock adjustment step is as follows. The step of adding (−N / LT) to the reference clock frequency can be executed in response to the adjustment of the interval length between packets at the latest time.

  Alternatively, the reference clock frequency adjusting method according to the present invention is a reference clock frequency adjusting method for a relay device that relays a packet to be transmitted. In the reference clock frequency adjusting method, an arrival time for detecting an interval length between packets arriving from a transmitting device upstream of the relay device is detected. An inter-packet interval length detecting step, an inter-transmit packet interval length detecting step for detecting an inter-packet interval length detecting step for a packet sent to a receiving side device downstream of the relay device, and a reference clock between the relay device and other devices within a predetermined time A step of counting the number of times the interval length between packets has been adjusted to absorb frequency deviation, and a clock adjustment step of adjusting the reference clock frequency of the relay device according to the counting result of the counting step It is.

  At this time, the parallel number when serial data of packets arriving at the relay apparatus is processed in the relay apparatus is L, the minimum expansion unit or minimum reduction unit of the interval length between packets is Nr bits, The time interval between two adjacent time points with the interval length adjusted is T seconds, the number of times that the interval length between packets is expanded in T seconds is Ma times, and the number of times that the interval length between packets is shortened in this T seconds is Md. The clock adjustment step processing is performed when the interval length between the packets at the latest time of the two time points is adjusted, and Nr × (Md−Ma) / LT is added to the reference clock frequency. Steps can be executed.

  In addition, a step of setting the same supply source of the driving clock frequency of the chip from the transmission side of the reception-side physical layer chip in the relay apparatus to the transmission side of the transmission-side physical layer chip in the relay apparatus can be included.

  A second aspect of the present invention is a relay device. That is, the relay device of the present invention is a relay device that relays transmitted packets, and an inter-arrival packet interval length detection means that detects an interval length between packets arriving from an upstream transmitting device, and a downstream receiving device. Interval length detection means for detecting an interval between packets to be sent to the side apparatus, an interval length between packets detected by an inter-arrival packet interval length detection means, and an interval length detection means for detecting an interval between outgoing packets Clock adjusting means for adjusting the reference clock frequency according to the difference from the interval length between packets.

  At this time, the number of parallels when processing the serial data of the arriving packet is L, and the time between two adjacent points in which the interval length between the packets is adjusted in order to absorb the deviation of the reference clock frequency from other devices The clock adjustment means adjusts the interval length between packets at the latest time of two time points when the interval is T seconds and the total interval length between the packets expanded in T seconds is N bits. (−N / LT) can be added to the reference clock frequency.

  Alternatively, the relay device according to the present invention includes an inter-arrival packet interval length detection unit that detects an interval length between packets arriving from an upstream transmission device and a downstream reception device in the relay device that relays transmitted packets. A transmission packet interval length detecting means for detecting an interval length between packets to be transmitted to the side device, and a number of adjustments of the interval length between packets in order to absorb a deviation of the reference clock frequency from other devices within a predetermined time. Means for counting and clock adjusting means for adjusting the reference clock frequency in accordance with the counting result of the means for counting are provided.

  At this time, the parallel number when serial data of packets arriving at the relay apparatus is processed in the relay apparatus is L, the minimum expansion unit or minimum reduction unit of the interval length between packets is Nr bits, The time interval between two adjacent time points with the interval length adjusted is T seconds, the number of times that the interval length between packets is expanded in T seconds is Ma times, and the number of times that the interval length between packets is shortened in this T seconds is Md. The clock adjustment means adds Nr × (Md−Ma) / LT to the reference clock frequency when the interval length between the packets is adjusted at the latest time of the two time points. Can do.

  Further, the supply source of the driving clock frequency of the chip from the transmission side of the reception side physical layer chip to the transmission side of the transmission side physical layer chip can be set to be the same.

  According to the present invention, clock frequency synchronization can be achieved while reducing the buffer amount.

It is a figure which shows the structure of the packet transmission system which concerns on 1st embodiment of this invention. It is a figure which shows the structure of the interface and hierarchy of the relay apparatus of FIG. It is a figure which shows the functional block structure of the relay apparatus of FIG. It is a figure showing the example of acquisition of the inter-packet interval length information in the inter-packet interval length comparison part in the functional block of the relay apparatus of FIG. 4 is a flowchart illustrating an operation procedure of an inter-packet interval length comparison unit in the functional block of the relay device of FIG. 3. It is a figure which shows the functional block structure of the relay apparatus which concerns on 2nd embodiment of this invention. It is a flowchart which shows the operation | movement procedure of the inter-packet interval length adjustment frequency count part in the functional block of the relay apparatus of FIG.

(Regarding the configuration of the packet transmission system 1 according to the first embodiment of the present invention)
The configuration of the packet transmission system 1 according to the first embodiment of the present invention will be described with reference to FIG. The packet transmission system 1 includes a relay device 2, a transmission side device 3, and a reception side device 4. The relay device 2 includes a clock transfer buffer 5. The position of the transmission side device 3 corresponds to a position upstream from the relay device 2. Further, the relay device 2 transfers the packet to the reception side device 4. The position of the receiving side device 4 corresponds to a downstream position as viewed from the relay device 2.

Here, the transmission rate of the physical layer of the transmission side apparatus 3 is 10 Gbps (for the sake of simplicity, 10 Gbps instead of 10.3125 Gbps. The same applies in the following embodiments) + α ppm, and the fixed-length packet is an Ethernet frame (hereinafter, The fixed length packet size is 1500 bytes, and the interval length between the fixed length packets is fixed at 500 bytes. The packet size is from the destination address excluding the preamble to the FCS (Frame Check Sequence). The interval between packets is IFG (Inter
(Frame Gap). In addition, the transmission speed of the transmission-side physical layer of the relay device 2 is 10 Gbps + β ppm. The absolute values of α and β are each 100 ppm or less. The interval length between packets is the length between the rear end of the former packet and the front end of the latter packet of the two packets.

(Regarding the interface and hierarchy structure of the relay device 2)
The configuration of the interface and hierarchy of the relay device 2 is shown in FIG. The relay device 2 includes MEDIUM (physical medium) 10, 11, MDI (Medium Dependent Interface) 12, 13, PMD (Physical Medium Dependent) 14, 15, and PMA (Physical Medium Connecting: Physical
Medium Attachment) 16, 17, XSBI (10 Gigabit 16-bit interface: 10Gigabit
Sixteen Blot Interface (18, 19), PCS (Physical Coding Sublayer: Physical
Coding Sub layer (20, 21), XGMII (10 Gigabit medium independent interface: 10Giga
bit Medium Independent Interface) 22, 23, 24, 25, XGXS (XGMII extender sublayer) 26, 27, 28, 29, XAUI (10 gigabit transceiver connection interface: 10 Gigabit Attachment Unit Interface) 30, 31 RS (Reconciliation Sublayer) 32, MAC (Media Access Control: Media
Access Control) 33 is provided.

  Further, the left side of the relay device 2 in FIG. 2 is the receiving side, and the right side is the transmitting side. The clock transfer buffer 5 in FIG. 1 is assumed to be in the XGXS 28, for example.

(About the operation of the interface and hierarchy of the relay device 2)
Next, the operation of the relay device 2 will be described. In FIG. 1, fixed-length packets are transmitted at a constant packet rate from the transmission-side device 3 that corresponds to the packet transmission side as viewed from the relay device 2. At this time, the transmission rate is assumed to be 10 Gbps.

  On the receiving side of the relay apparatus 2, a signal transition of an NRZ (Non Return to Zero) digital baseband signal is detected. Then, the clock is regenerated by adjusting the phase of the reference clock frequency inside the apparatus. That is, data is written into the clock transfer buffer 5 in the relay apparatus 2 at a speed of 10 Gbps + α ppm. On the other hand, data is read from the clock transfer buffer 5 in the relay apparatus 2 at a speed of 10 Gbps + β ppm.

  Therefore, due to the difference between α and β, unless the interval length between packets is adjusted, the data amount in the clock transfer buffer 5 will eventually overflow (when α> β), or the buffer will run out. (When α <β).

  In the relay apparatus 2, it is assumed that the reception side of the XGXS 28 having the clock transfer buffer 5 from the MEDIUM 10 is driven based on the “reception clock frequency” by clock recovery (CDR: Clock Data Recovery). Thereafter, it is assumed that driving from the transmission side of XGXS 28 to MEDIAUM 11 is performed at the “device clock frequency”.

  According to the IEEE 802.3-2005 standard, in the PCS 20, the first byte of the packet must be arranged in lane # 0 among the four lanes # 0, lane # 1, lane # 2, and lane # 3 of XGMII22. There is. For this reason, when “packet length + interval length between packets” is not a multiple of 4 bytes, the inter-packet interval length is changed at this point. In this embodiment, “packet length + inter-packet length” is 2000 bytes, which is a multiple of 4 bytes. For this reason, a change in the interval length between packets in the PCS 20 does not occur.

  Further, according to the IEEE 802.3-2005 standard, when the amount of data stored in the clock transfer buffer 5 exceeds a certain threshold in order to change the clock in the XGXS 28, the interval length between packets is set to the value of the XAUI 30. It is described that each column is increased or decreased. Note that “exceeding the threshold value” includes both the direction in which the accumulation amount increases or the direction in which the accumulation amount decreases. Further, “one column unit” is 4 bytes (when converted to 8B in 8B / 10B).

  Therefore, in FIG. 1, when there is a difference in clock frequency between the transmission side device 3 and the relay device 2, the interval length between packets of packets output from the relay device 2 is increased or decreased with a minimum resolution of 4 bytes. Is called.

  For example, when α <β, the transmission transmission rate of the transmission side device 3 is slower than the initial transmission transmission rate of the relay device 2. For this reason, the interval length between packets transmitted from the relay apparatus 2 is increased by a certain amount at certain time intervals. On the other hand, when α> β, the transmission transmission rate of the transmission side device 3 is faster than the initial transmission transmission rate of the relay device 2. For this reason, the interval length between packets transmitted from the relay apparatus 2 is reduced by a certain amount at certain time intervals.

  On the other hand, when the interval length between packets transmitted from the relay device 2 is always equal to the interval length between packets transmitted from the transmission side device 3 and no packet loss occurs in the relay device 2, the relay device 2 And the clock frequency of the transmission side apparatus 3 are equal.

  Therefore, the interval length information between packets before adjusting the interval length between packets is acquired before XGXS28, the interval length information between packets after adjusting the interval length between packets is acquired after XGXS28, and the difference between them is obtained. A comparison unit for comparison is provided separately. Then, the reference clock frequency of the relay device 2 itself is adjusted based on the information calculated by the comparison unit.

  Below, the structure and operation | movement are demonstrated about the functional block of the relay apparatus 2 based on such an idea.

(Regarding the functional block configuration of the relay device 2)
The configuration of functional blocks of the relay device 2 will be described with reference to FIG. FIG. 3 is a diagram illustrating a functional block configuration of the relay apparatus 2 of FIG. Also, the thick solid line arrows in FIG. 3 indicate the flow of data. In addition, thin solid arrows in FIG. 3 indicate the flow of control signals. Also, the dashed arrows in FIG. 3 indicate the flow of the clock signal.

  As a functional block configuration of the relay apparatus 2, a reception side processing unit 40, a data processing unit 41, a transmission side processing unit 42, an interpacket interval length comparison unit 43, a reference clock frequency adjustment unit 44, and a reference clock frequency generation unit 45 are provided. . The reception side processing unit 40 receives a packet from the transmission side device 3 (upstream side). The data processing unit 41 receives the output of the reception side processing unit 40 as input, performs data processing, and outputs the processed data to the transmission side processing unit 42. The transmission side processing unit 42 sends the packet to the reception side device 4 (downstream side).

  The reception side processing unit 40 includes a serial / parallel conversion unit 50, a transmission side clock operation unit 51, a clock transfer processing unit 52, and a reception side in-device clock operation unit 53. The transmission side processing unit 42 includes a reception side in-device clock operation unit 54 and a parallel / serial conversion unit 55.

  That is, the inter-packet interval length comparison unit 43 detects the inter-arrival packet interval detection means for detecting the inter-packet interval length from the transmission side device 3 and the transmission interval for detecting the interval length between the packets sent to the reception side device 4. Inter-packet interval detection means. Further, the inter-packet interval length comparing unit 43 detects the difference between the inter-packet interval length detected by the arrival inter-packet interval detecting means and the inter-packet interval length detected by the outgoing packet interval detecting means.

  The reference clock frequency adjusting unit 44 is a reference clock frequency generating unit 45 of the relay device 2 according to the difference between the interval length between arrival packets detected by the inter-packet interval length comparison unit 43 and the interval length between transmission packets. Clock adjustment means for adjusting the generated reference clock frequency is provided.

  Here, “detection” means that the interval length between packets is actually measured by the inter-packet interval length comparison unit 43, or the interval length between packets transmitted from the transmission side apparatus 3 is determined in advance. If it is determined that the value is used, or the interval length between packets is measured in advance by another device or another functional block different from the relay device 2, the value is directly notified to the relay device 2, This represents either an action recognized by the relay apparatus 2 or an action of reading the value when a value measured by another apparatus or another functional block is described in any field in the packet.

  The reference clock frequency adjustment unit 44 sets the number of parallels when serial data of the input packet is processed in the relay apparatus 2 to L, and the clock transfer processing unit 52 adjusts the interval length between the transmitted packets. The time interval between two adjacent time points is set to T seconds, and the interval length between packets that has been expanded by executing the adjustment of the interval length between transmitted packets by the clock transfer processing unit 52 in T seconds is set to N bits. In some cases, the reference clock frequency adjusting unit 44 is triggered by the adjustment of the interval length between transmitted packets by the clock transfer processing unit 52 at the latest time of the two time points. -N / LT) is added.

  Note that the time interval T seconds is actually calculated as a clock count based on the reference clock frequency in the relay apparatus 2. If the value for adjusting the reference clock frequency cannot be set to N / LT due to PLL (Phase Locked Loop) in the relay device 2, etc., set the value closest to the settable N / LT. Is preferred.

  Here, the operation of the reference clock frequency adjusting unit 44 will be described more easily. When the interval length between packets transmitted from the relay device 2 is larger than the interval length between packets arriving at the relay device 2. The reference clock frequency adjustment unit 44 lowers the reference clock frequency of the reference clock frequency generation unit 45. That is, it is assumed that the reference clock frequency of the relay device 2 is higher than the reference clock frequency of the transmission side device 3. In this case, the relay apparatus 2 transmits the data received from the transmission side apparatus 3 to the reception side apparatus 4 at a transmission rate faster than the transmission rate of the transmission side apparatus 3.

  Therefore, since the amount of data sent from the relay device 2 is larger in unit time than the amount of data reaching the relay device 2 from the transmission side device 3, the data sent from the relay device 2 will be exhausted as it is. become. In order to prevent this, when the clock transfer processing unit 52 detects such a situation, the clock transfer processing unit 52 tries to extend the interval length between the transmitted packets by adding a predetermined byte sequence between the packets. This is a conventional Ethernet technology. Thereby, in the Ethernet, data exchange can be realized regardless of the asynchronous network. This predetermined byte string is equal to the inter-packet interval and has no meaning as data.

  In such a case, the reference clock frequency adjustment unit 44 determines that the reference clock frequency of the reference clock frequency generation unit 45 of its own relay device 2 is higher than that of the transmission side device 3 and determines the reference clock frequency of its own relay device 2. The reference clock frequency of the generator 45 is lowered.

  On the other hand, when the interval length between packets sent from the relay device 2 is smaller than the interval length between packets arriving at the relay device 2, the reference clock frequency adjusting unit 44 generates the reference clock frequency. The reference clock frequency of the unit 45 is increased. That is, it is assumed that the reference clock frequency of the relay apparatus 2 is lower than the reference clock frequency of the transmission side apparatus 3. In this case, the relay apparatus 2 transmits the data received from the transmission side apparatus 3 to the reception side apparatus 4 at a transmission rate slower than the transmission rate of the transmission side apparatus 3.

  Therefore, since the data amount transmitted from the relay device 2 is smaller in unit time than the data amount reaching the relay device 2 from the transmission side device 3, the data transmitted from the relay device 2 overflows as it is. Become. In order to prevent this, when the clock transfer processing unit 52 detects such a situation, the clock transfer processing unit 52 tries to shorten the interval length between the transmitted packets by deleting a predetermined byte sequence between the packets. This is a conventional Ethernet technology.

  In such a case, the reference clock frequency adjustment unit 44 determines that the reference clock frequency of the reference clock frequency generation unit 45 of its own relay device 2 is lower than that of the transmission side device 3 and determines the reference clock frequency of its own relay device 2. The reference clock frequency of the generation unit 45 is increased.

  Normally, the clock transfer processing unit 52 itself does not report the status of addition or deletion of a predetermined byte sequence to the control unit (not shown) of the relay device 2. This is because, until now, the Ethernet technology is normally used between devices that are not synchronized, and the processing for adjusting the interval length between packets autonomously performed by the clock transfer processing unit 52 is relayed. This is because there was no need for the device 2 to be involved.

  The clock change processing unit 52 is realized by using a commercially available general-purpose MAC chip. It is difficult to add a function for reporting to the control unit of the relay apparatus 2 whether or not a predetermined byte string has been added or deleted to such a general-purpose MAC chip. Therefore, the relay device 2 does not directly monitor the processing contents of the clock transfer processing unit 52, but the clock transfer processing unit 52 adds or deletes a predetermined byte sequence in the inter-packet interval length comparison unit 43. It is detected whether or not. Thereby, the control unit of the relay device 2 can indirectly monitor whether or not the clock transfer processing unit 52 has added or deleted a predetermined byte string.

  Here, the correspondence between the interface and hierarchy configuration of the relay device 2 shown in FIG. 2 and the functional block configuration of the relay device 2 shown in FIG. 3 will be described. The reception side processing unit 40 in FIG. 3 corresponds to the MEDIAUM 10 to XGMII 24 in FIG. The data processing unit 41 in FIG. 3 corresponds to the RS 32 and the MAC 33 in FIG. 3 corresponds to XGMII25 to MEDIUM11 in FIG.

  More specifically, the serial / parallel converter 50 in FIG. 3 corresponds to the PMA 16 in FIG. The transmission side clock operation unit 51 of FIG. 3 corresponds to the MEDIAUM 10 to the reception side of the XGXS 28 of FIG. The clock transfer processing unit 52 in FIG. 3 corresponds to the XGXS 28 in FIG. 2 and the clock transfer buffer 5 in the XGXS 28. 3 corresponds to the transmission side of the XGXS 28 and the XGMII 24 in FIG. The in-device clock operation unit 54 in FIG. 3 corresponds to XGMII 25 to MEDIUM 11 in FIG. The parallel / serial converter 55 in FIG. 3 corresponds to the PMA 17 in FIG.

(Operation of functional block of relay device 2)
Next, the operation of the functional blocks of the relay device 2 will be described. The reference clock frequency of the relay device 2 is CHz, the reference clock frequency of the transmission side device 3 with respect to the relay device 2 is C′Hz, and the clock transfer processing unit 52 adjusts the interval length between packets every 10 packets. And Note that the interval length between every 10 packets corresponds to time T seconds. The interval length between packets to be adjusted is N bits.

  At this time, a packet having a data amount of C′L bits (= 10 G bits + α ppm) per second is input to the serial / parallel converter 50 in FIG. 3. These packets are processed in parallel, and as a result, data having a transmission capacity of L C'bps is transferred from the serial / parallel conversion unit 50 to the transmission side clock operation unit 51.

  On the other hand, the output side of the clock change processing unit 52 operates at a reference clock frequency of CHz. As a result, L Cbps of transmission capacity data, that is, a total of CL bits (= 10 Gbit + β ppm) per second is transferred to the receiving apparatus 4 at the subsequent stage. In this manner, the clock transfer processing unit 52 adjusts the interval length between packets by adding or deleting a predetermined byte sequence.

  The inter-packet interval length comparison unit 43 compares the inter-packet interval lengths on the input side and output side of the clock transfer processing unit 52. The reference clock frequency adjusting unit 44 adjusts the reference clock frequency according to the comparison result.

  That is, the inter-packet interval length comparison unit 43 calculates a difference of N bits in T seconds, and CL−C′L = N / T is established. However, N> 0 when α <β, and N <0 when α> β. Therefore, the reference clock frequency adjustment unit 44 adjusts so that −N / T, which is the difference between the reference clock frequency of the transmission side device 3 and the reference clock frequency of the relay device 2, is added to the reference clock frequency. Thereby, the reference clock frequency of the transmission side apparatus 3 and the relay apparatus 2 can be made to correspond. The timing for adjusting the reference clock frequency is preferably performed immediately after the interval length between packets is changed or at a time close thereto.

  FIG. 4 shows an example of acquisition of inter-packet interval length information in the inter-packet interval length comparison unit 43 in the relay apparatus 2. The range in which the interval length extension between packets is positive is a case where the interval length between packets is extended as a result of passing through the relay device 2. Further, the range in which the interval length extension between packets is negative is a case where the interval length between packets is shortened as a result of passing through the relay device 2. The N bit is the result of adding all these positive and negative values.

  Here, it demonstrates using a numerical value concretely. α = −100 ppm (10 GHz + α ppm = 9999000000 Hz), β = −100 ppm (10 GHz + β ppm = 10001,000,000 Hz). According to this, the relay apparatus 2 transmits 10 G bits + β ppm− (10 G bits + α ppm) = 2000000 bits = 250,000 bytes per second as compared with the transmission side apparatus 3. Therefore, if a predetermined byte sequence is inserted and the insertion length is a unit of 4 bytes, the number of predetermined code words inserted per second is 250,000 / 4 = 62500.

  There are (10 Gbit + αppm) / {(1500 + 500) × 8 bits} = 6244937.5 packet intervals within 10 Gbit + αppm. Therefore, on average, the calculation is such that a predetermined code word is inserted at a rate of once every 624937.5 / 62500 = 9.999 times. Assuming that the time for transmitting 9.999 times “packet length + inter-packet length” is T seconds, T = 9.999 × (1500 + 500) × 8 / (10 Gbps + αppm) = 0.000016 seconds. As a result, N / T = 32 / 0.000016 = 2000000 Hz. Therefore, the relay apparatus 2 may add the clock frequency by −N / T, that is, 10 GHz + βppm−N / T = 10001000000−2000000 = 9999000000Hz (= 10 GHz + αppm). As a result, the clock frequencies of the transmission side device 3 and the relay device 2 are synchronized.

  In the above description, N and T are obtained and then the clock frequency adjusted by the relay apparatus 2 is calculated. If the values of α and β are known in advance, 10 G bits + β ppm− (10 G bits + α ppm) = 2000000 bits Therefore, the clock for 2000000 bits = 2000000 Hz per second may be adjusted. In this case, since the clock frequency adjustment amount is calculated when T is 1 second, unlike the clock frequency adjustment based on the interval length adjustment between individual packets, when a fixed periodic clock adjustment is desired. Suitable for

(Regarding the flowchart showing the operation procedure of the inter-packet interval length comparison unit 43)
Next, the operation procedure of the inter-packet interval length comparison unit 43 will be described with reference to the flowchart of FIG. The inter-packet interval length comparison unit 43 detects the inter-packet interval length that arrives at the input side of the clock transfer processing unit 52 (step S1). Subsequently, the inter-packet interval length comparison unit 43 detects the inter-packet interval length transmitted from the output side of the clock transfer processing unit 52 (step S2).

  Next, the inter-packet interval length comparing unit 43 determines the interval length between packets arriving at the input side of the clock transfer processing unit 52 and the interval length between packets transmitted from the output side of the clock transfer processing unit 52. Is detected (step S3).

  Next, the inter-packet interval length comparison unit 43 determines that the interval length between packets transmitted from the output side of the clock transfer processing unit 52 is the input side of the clock transfer processing unit 52 according to the detection result of step S3. If it is larger than the interval length between packets arriving at (Yes in step S4), the reference clock frequency adjusting unit 44 is instructed to lower the reference clock frequency of the reference clock frequency generating unit 45 (step S5).

  Further, the inter-packet interval length comparison unit 43 arrives at the input side of the clock transfer processing unit 52 in accordance with the detection result of step S3. If it is smaller than the interval length between packets to be transmitted (No in step S4 and Yes in step S6), the reference clock frequency adjusting unit 44 is instructed to increase the reference clock frequency of the reference clock frequency generating unit 45 (step S7). ).

  Further, the inter-packet interval length comparing unit 43 determines the interval length between packets sent from the output side of the clock transfer processing unit 52 and the packet arriving at the input side of the clock transfer processing unit 52 according to the detection result of step S3. If there is no difference from the interval length (No in step S4 and No in step S6), no instruction is given to the reference clock frequency adjusting unit 44 (step S8).

(Regarding the configuration of the relay device 2A according to the second embodiment of the present invention)
The configuration of the relay device 2A according to the second embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram illustrating a configuration of functional blocks of the relay device 2A. Also, the thick solid arrows in FIG. 6 indicate the flow of data. In addition, thin solid arrows in FIG. 6 indicate the flow of control signals. Also, the broken-line arrows in FIG. 6 indicate the flow of the clock signal.

  The relay device 2A is partially different from the relay device 2. Hereinafter, the same or similar members as those of the relay device 2 will be described using the same or the same reference numerals, the description thereof will be omitted or simplified, and different members will be mainly described. The relay apparatus 2A is mainly different from the relay apparatus 2 in that an inter-packet interval length adjustment count counter 43A in FIG. 6 is provided instead of the inter-packet interval length comparison section 43 in FIG.

(About operation of relay device 2A)
Next, the operation of the relay device 2A will be described. The reference clock frequency adjusting unit 44A of the relay device 2A sets the number of parallels when processing the serial data of the packet arriving at the relay device 2A in the relay device 2A as L, and sets the interval length between packets as the minimum expansion unit. The minimum addition unit of the predetermined byte sequence or the minimum deletion unit of the predetermined byte sequence as the minimum shortening unit of the interval length between packets is Nr bits, and the reference clock frequency adjusting unit 44A is adjacent to the reference clock frequency adjusted. The time interval between the two points in time is T seconds, the interval length between packets is expanded, that is, the number of byte sequences added during this T seconds is Ma times, and the interval length between packets is shortened in this T seconds, that is, the byte sequences are deleted. When the number of times is Md, the clock transfer processing unit 52A adjusts the interval length between packets at the latest time of the two time points. It is triggered by, adding Nr × (Md-Ma) / LT with respect to the reference clock frequency.

(Specific example of operation of relay device 2A)
Next, a specific example of the operation of the relay device 2A will be described. The reference clock frequency of the relay device 2A is CHz, the reference clock frequency of the transmission side device 3 with respect to the relay device 2A is C'Hz, and the interval length between packets is adjusted every 100 packets (time is T seconds). I will do it. The resolution of the interval length between packets adjusted at this time is Nr bits. At this time, the data amount of C′L bits (= 10 G bits + α ppm) is input to the serial / parallel converter 50 in FIG. 6 per second, and these are processed in parallel. As a result, L C′bps data is transferred from the serial / parallel conversion unit 50 to the transmission side clock operation unit 51.

  On the other hand, the output side of the clock transfer processing unit 52A operates at the reference clock frequency of CHz, and the data of the Cbps speed for L lines, that is, the total CL bits (= 10G bits + βppm) per second is the receiving side in the subsequent stage. It is transferred to the device 4. Consider a case where a predetermined byte sequence is added or deleted in the clock transfer processing unit 52A.

  The inter-packet interval length adjustment count counting unit 43A adjusts the reference clock frequency of the relay apparatus 2A based on the number of additions (Ma) and the number of deletions (Md) of the predetermined byte sequence. Specifically, if Ma = 10, Md = 0, and Nr = 32 in T seconds, the difference in output data amount between the transmission side device 3 and the relay device 2A is 32 × (10−0) = T seconds. It is 320 bits, and the relay device 2A has a faster reference clock frequency. Therefore, the clock frequency adjustment amount required per second can be calculated, and the reference clock frequency adjusting unit 44A can adjust the reference clock frequency of the relay apparatus 2A.

  Now, since T = 100 × (1500 + 500) × 8 bits / (10 Gbps + α ppm) = 0.000160016 seconds, it is only necessary to adjust 320 / 0.000160016 = 1999800 bits = 1999800 Hz per second. That is, 10 Gbps + β ppm−1999800 = 10001000000−1999800≈9999000000 bps (= 10 Gbps + αppm), and the reference clock frequency of the relay apparatus 2A is almost equal to the reference clock frequency of the transmission side apparatus 3.

(Regarding the flowchart showing the operation procedure of the inter-packet interval length adjustment count section 43A)
Next, the operation procedure of the inter-packet interval length adjustment count section 43A will be described with reference to the flowchart of FIG. The inter-packet interval length adjustment count counting unit 43A counts the number of packet interval expansion processing (that is, addition processing of a predetermined byte sequence) performed by the clock transfer processing unit 52A (step S10). Subsequently, the inter-packet interval length adjustment count counting unit 43A counts the number of packet interval shortening processes (that is, a predetermined byte string deletion process) performed by the clock transfer processing unit 52A (step S11).

  Next, the inter-packet interval length adjustment count counting unit 43A detects a difference between the number of packet interval expansion processes performed by the clock transfer processing unit 52A and the number of packet interval shortening processes performed by the clock transfer processing unit 52A. (Step S12).

  Next, the inter-packet interval length adjustment count counting unit 43A performs the packet interval shortening process performed by the clock transfer processing unit 52A in accordance with the detection result of step S12. (Yes in step S13), the reference clock frequency adjustment unit 44A is instructed to lower the reference clock frequency of the reference clock frequency generation unit 45 (step S14).

  In addition, the inter-packet interval length adjustment count counting unit 43A performs the packet interval shortening process performed by the clock transfer processing unit 52A according to the detection result of step S12. If it is smaller than the number of times (No in step S13 and Yes in step S15), it instructs the reference clock frequency adjusting unit 44A to increase the reference clock frequency of the reference clock frequency generating unit 45 (step S16).

  Further, the inter-packet interval length adjustment count counting unit 43A determines the number of packet interval expansion processes performed by the clock transfer processing unit 52A and the number of packet interval shortening processes performed by the clock transfer processing unit 52A according to the detection result of step S12. If there is no difference (No in step S13 and No in step S15), no instruction is given to the reference clock frequency adjusting unit 44A (step S17).

(Modification)
The embodiment of the present invention can be variously modified without departing from the gist thereof. For example, in the embodiment of the present invention, it is assumed that an Ethernet frame is used, but the present invention can also be applied to packet transmissions other than Ethernet.

  Further, although the interval length between packets is represented by the number of bytes or the number of bits, it may be a “clock count number” instead of the number of bits.

  Further, instead of comparing the interval length between one transmission packet and arrival packet in the relay device 2, the interval lengths between a certain number of packets may be compared. According to this, the adjustment timing of the reference clock frequency is smoothed. Therefore, it is suitable for the case where the relay apparatus 2 has a function with low tolerance against frequent adjustment of the reference clock frequency.

  In this case, when the sum of the interval lengths between the packets transmitted from the relay device 2 is larger than the sum of the interval lengths between the packets arriving at the relay device 2, the relay device 2 sets its own reference clock frequency. Lower. Further, when the sum of the interval lengths between the packets transmitted from the relay device 2 is smaller than the sum of the interval lengths between the packets arriving at the relay device 2, the relay device 2 increases its reference clock frequency.

(About the program embodiment)
Each unit of the relay devices 2 and 2A is a general-purpose information processing device (CPU (Central
Processing Unit), DSP (Digital Signal Processor), microprocessor (microcomputer), and the like. For example, a general-purpose information processing apparatus has a memory, a CPU, an input / output port, and the like. The CPU of the general-purpose information processing apparatus reads and executes a control program as a predetermined program from a memory or the like. Thereby, the function of each part of relay apparatus 2 and 2A is implement | achieved in a general purpose information processing apparatus. As for other functions, functions that can be realized by software can be realized by a general-purpose information processing apparatus and a program.

  Even if the control program executed by the general-purpose information processing apparatus is stored in the memory or the like of the general-purpose information processing apparatus before shipment of the relay apparatus 2 or 2A, the control program executed after the relay apparatus 2 or 2A is shipped. Alternatively, it may be stored in a memory of a general-purpose information processing apparatus. Further, a part of the control program may be stored in a memory of a general-purpose information processing apparatus after shipment of the relay apparatuses 2 and 2A. The control program stored in the memory of a general-purpose information processing apparatus after shipment of the relay apparatuses 2 and 2A is, for example, an installed version stored in a computer-readable recording medium such as a CD-ROM. Or what was downloaded via transmission media, such as the internet, may be installed.

  The control program includes not only a program that can be directly executed by a general-purpose information processing apparatus, but also a program that can be executed by being installed on a hard disk or the like. Also included are those that are compressed or encrypted.

(Effects according to embodiments of the present invention)
It is estimated how much the delay time is suppressed as compared with the method described in Non-Patent Document 2. If the storage buffer amount of data is monitored in units of 10 ms using Linux and it is determined whether or not a certain threshold has been exceeded and clock frequency processing is started, at least an initial storage of 10 ms is performed. That is, a delay of at least 10 ms is required separately per device.

  Software for monitoring a buffer is generally installed on Linux, and monitoring in units of 10 ms is appropriate as a unit time resolution considering interrupt processing and the like. Therefore, when 10 units of this apparatus are relayed, a delay of maximum 10 ms × 10 = 100 ms is necessary for monitoring the buffer amount. On the other hand, this delay time is unnecessary in the relay apparatuses 2 and 2A, and the delay time can be reduced accordingly.

  Further, the clock transfer buffer 5 of the relay devices 2 and 2A is always provided in a processing chip that handles the Ethernet technology. Since it suffices to store several packets, usually only an order of several kilobytes is prepared. Therefore, if 10 packets are accumulated, a delay of the order of μs occurs. This is also necessary time in the technique of Patent Document 1. In the reference clock frequency generation unit 45 of the relay devices 2 and 2A, the supply source of the drive clock frequency of all the chips can be set to the same reference clock frequency generation unit 45 for such processing chips. As a result, the drive clock frequencies in all the chips in the relay devices 2 and 2A can be unified.

  On the other hand, when the supply sources of the driving clock frequencies of all the chips are not set to be the same, the inter-packet interval length comparison unit 43 includes the output part of the transmission side clock operation part 51 and the part immediately before the parallel / serial conversion part 55. What is necessary is just to compare the interval length between these packets. However, in this case, the interval length between packets may be adjusted for each functional block. Therefore, in this case, it is preferable to obtain the sum of the interval lengths between a certain number of packets and compare the sum.

  As described above, clock frequency synchronization can be achieved between the relay apparatuses 2 and 2A. As a result, the buffer amount between the relay apparatuses 2 and 2A can be reduced as much as possible. That is, it is possible to construct a video distribution network with low delay and low jitter in pursuit of real-time characteristics.

  For example, in the conventional adaptive clock method described in Non-Patent Document 2, both a clock adjustment buffer (several KB) and an adaptive clock method buffer (several MB) are required. On the other hand, in the relay apparatuses 2 and 2A, the clock frequency synchronization can be realized only by the clock adjustment buffer (several KB). Further, unlike the buffer for the adaptive clock method in which the buffer amount is monitored one by one, the clock adjustment buffer only determines whether the threshold value is exceeded or not exceeded. Therefore, in the relay apparatuses 2 and 2A, it is possible to reduce the necessary buffer amount and delay amount as compared with the conventional adaptive clock method.

DESCRIPTION OF SYMBOLS 1 ... Packet transmission system 2, 2A ... Relay device, 3 ... Transmission side device, 4 ... Reception side device, 5 ... Clock transfer buffer, 10, 11 ... MEDIUM, 12, 13 ... MDI, 14, 15 ... PMD 16, 17 ... PMA, 18, 19 ... XSBI, 20, 21 ... PCS, 22, 23, 24, 25 ... XGMII, 26, 27, 28, 29 ... XGXS, 30, 31 ... XAUI, 32 ... RS, 33 ... MAC, 40, 40A ... Reception side processing unit, 41 ... Data processing unit, 42 ... Transmission side processing unit, 43 ... Inter-packet interval length comparison unit (inter-arrival packet interval length detection means, outgoing packet interval length detection means) 43A ... Inter-packet interval length adjustment count counter (counting means), 44, 44A ... Reference clock frequency adjusting section (clock adjusting means), 45 ... Reference clock frequency generating section DESCRIPTION OF SYMBOLS 50 ... Serial / parallel conversion part, 51 ... Transmission side clock operation part, 52, 52A ... Clock transfer process part, 53 ... Reception side apparatus clock operation part, 54 ... Reception side apparatus clock operation part, 55 ... Parallel / Serial converter

Claims (6)

In a reference clock frequency adjustment method for a relay device that relays a packet to be transmitted,
And arriving packet spacing length detection step of detecting the spacing length between packets arriving from the transmitting device at the upstream of the front Symbol repeater,
And sending the packet spacing length detection step of detecting the spacing length between packets to be sent to the receiving apparatus downstream of the pre-Symbol repeater,
Corresponding to the difference between the spacing length between before SL packets detected by the processing interval length and the previous SL outbound packet spacing length detection step between before Symbol arrival packet spacing length detection step before SL packets detected by the processing and clock adjustment step of adjusting the reference clock frequency before Symbol repeater Te,
I have a,
The parallel number when processing serial data of packets arriving at the relay device in the relay device is L,
The time interval between two adjacent time points in which the relay device adjusts the interval length between packets in order to absorb the deviation of the reference clock frequency from other devices is T seconds,
When the total interval length expanded in T seconds is N bits,
The process of the clock adjustment step is executed by adjusting (−N / LT) to the reference clock frequency when the interval length between packets is adjusted at the latest time of the two time points .
And a reference clock frequency adjusting method. In a reference clock frequency adjustment method for a relay device that relays a packet to be transmitted,
And arriving packet spacing length detection step of detecting the spacing length between packets arriving from the transmitting device at the upstream of the front Symbol repeater,
And sending the packet spacing length detection step of detecting the spacing length between before SL packets to be sent to the receiving apparatus downstream of the pre-Symbol repeater,
A step for counting the number of times of adjusting the spacing length between packets to absorb the reference clock frequency deviation of the previous SL relay apparatus other devices within a predetermined time period,
And clock adjustment step of adjusting the reference clock frequency before the SL relay device according to the counting result of the step of the count,
I have a,
The parallel number when processing serial data of packets arriving at the relay device in the relay device is L,
The minimum extension unit or minimum shortening unit of the interval length is Nr bits,
The time interval between two adjacent time points adjusted for the interval length between packets is T seconds,
The number of times the interval length is extended in T seconds is Ma times,
When the number of times the interval length is shortened in T seconds is Md,
The process of the clock adjustment step includes a step of adding Nr × (Md−Ma) / LT to the reference clock frequency when the interval length between packets at the latest time of the two time points is adjusted. Run ,
And a reference clock frequency adjusting method. The reference clock frequency adjustment method according to claim 1 or 2 ,
Setting the same supply source of the driving clock frequency of the chip from the transmission side of the reception-side physical layer chip in the relay apparatus to the transmission side of the transmission-side physical layer chip in the relay apparatus,
And a reference clock frequency adjusting method. In a relay device that relays transmitted packets,
An inter-arrival packet interval length detecting means for detecting an interval length between packets arriving from an upstream transmitting device;
A transmission packet interval length detection means for detecting an interval length between packets to be transmitted to a downstream receiving device;
Reference clock frequency according to the difference between the distance length between before SL packets detected by the distance length and before Symbol outbound packet spacing length detection means between before SL packets detected by the previous SL arrival packet spacing length detecting means Clock adjusting means for adjusting
Equipped with a,
Let L be the parallel number when processing the serial data of the arriving packet,
The time interval between two adjacent time points with the interval length between packets adjusted to absorb the deviation of the reference clock frequency from other devices is T seconds,
When the total interval length expanded in T seconds is N bits,
The clock adjustment means is triggered by adjusting the interval length between packets at the latest time of the two time points, and adds (−N / LT) to the reference clock frequency.
A relay device characterized by that. In a relay device that relays transmitted packets,
An inter-arrival packet interval length detecting means for detecting an interval length between packets arriving from an upstream transmitting device;
And sending the packet spacing length detecting means for detecting the spacing length between before SL packets to be sent to the receiving device downstream,
Means for counting the number of times the interval length between packets is adjusted in order to absorb the deviation of the reference clock frequency with other devices within a predetermined time;
Clock adjusting means for adjusting the reference clock frequency according to the counting result of the counting means;
Equipped with a,
The parallel number when processing serial data of packets arriving at the relay device in the relay device is L,
The minimum extension unit or minimum shortening unit of the interval length is Nr bits,
The time interval between two adjacent time points adjusted for the interval length between packets is T seconds,
The number of times the interval length is extended in T seconds is Ma times,
When the number of times the interval length is shortened in T seconds is Md,
The clock adjustment means is triggered by adjusting the interval length between packets at the latest time of the two time points, and adds Nr × (Md−Ma) / LT to the reference clock frequency .
A relay device characterized by that. The relay device according to claim 4 or 5 ,
Set the same supply source of the driving clock frequency of the chip from the transmitting side of the receiving physical layer chip to the transmitting side of the transmitting physical layer chip,
A relay device characterized by that.

Images