CN114499728A - Associated clock jitter suppression method and device for E1 link and electronic equipment - Google Patents
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Abstract
The application provides a method, a device and electronic equipment for suppressing associated clock jitter of an E1 link, wherein the method is applied to an FPGA and comprises the following steps: after reading data of preset bytes from a data queue to a register, acquiring a signal representing the data quantity of the data stored in the data queue; determining a corresponding clock frequency according to the signal; and stably shifting the data in the register out of the register according to the corresponding clock frequency, thereby solving the problems that the shifting-out speed of the data is changed randomly and continuously and the change amplitude is large due to the very large channel associated clock jitter of the E1 link analyzed from the SDH in the prior art.
Description
Technical Field
The present application relates to the field of data communication technologies, and in particular, to a method and an apparatus for suppressing channel associated clock jitter of an E1 link, and an electronic device.
Background
In data communication, especially in a CPOS wide area card of a router SDH OC 3155M interface, there are 63 low-speed E1 physical channels of 2048Khz in the CPOS wide area card. The clock of the E1 link is a channel associated clock (the clock is hidden in the data), while the channel associated clock of the E1 link extracted from the SDH has very large jitter, that is, the clock frequency of the channel associated clock changes randomly and continuously, and the change amplitude is large, which in turn causes the shift-out rate of the data in the register corresponding to each E1 link to change randomly and continuously, and the change amplitude is very large, thereby requiring jitter suppression.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a method, an apparatus and an electronic device for suppressing the channel associated clock jitter of an E1 link, so as to solve the above problems.
In a first aspect, an embodiment of the present application provides a method for suppressing a channel associated clock jitter of an E1 link, which is applied to an FPGA, and the method includes: after reading data of preset bytes from a data queue to a register, acquiring a signal representing the data quantity of the data stored in the data queue; determining a corresponding clock frequency according to the signal; and shifting the data in the register out of the register according to the corresponding clock frequency.
In the implementation process, after reading the data of the preset bytes from the data queue to the register, the corresponding clock frequency is determined according to the signal representing the data amount of the data stored in the data queue, and it can be understood that the clock frequency is in a certain relationship with the data amount of the data stored in the data queue, and then the data in the register can be stably shifted out of the register at a rate corresponding to the corresponding clock frequency according to the corresponding clock frequency, so that the problems that the shifting-out rate of the data is randomly and constantly changed and the change amplitude is extremely large due to the fact that the channel associated clock jitter of an E1 link carried by the SDH is very large in the prior art are solved.
Based on the first aspect, in a possible design, the determining, according to the signal, a corresponding clock frequency includes: determining the data volume according to the signal; determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size; and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
Because the data size of the data stored in the data queue may change continuously, if the different clock frequencies corresponding to the different data sizes are not reasonable, the problem of large jitter of the data shifting-out rate cannot be solved well, therefore, in order to be able to determine the clock frequency corresponding to the signal quickly, accurately and reasonably and to better solve the problem of large jitter of the data shifting-out rate, in the implementation process, the data range corresponding to the data size is determined accurately according to the data size determined by the signal and the range division rule of the data size and the predetermined data size by establishing the corresponding relationship between the data range and the clock frequency in advance, so that the clock frequency corresponding to the corresponding data range can be found out quickly and accurately from the corresponding relationship between the data range and the clock frequency, it can be understood that, since a range of data amount corresponds to a clock frequency, even if the data amount of the data stored in the data queue changes continuously, the data stored in the data queue can be guaranteed not to be read empty or overflow, and the data can be guaranteed to be smoothly shifted out of the register.
Based on the first aspect, in one possible design, before the finding out the clock frequency corresponding to the corresponding data range, the method further includes: and determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
Although the jitter of the slave clock of the E1 link carried by the SDH is relatively large, the slave clock of the E1 link conforms to the standard clock of the E1 link before entering the SDH, and therefore, in the implementation process, the clock frequency in the corresponding relationship is determined according to the predetermined size of the standard clock of the E1 link, and since each clock frequency in the corresponding relationship is related to the standard clock, the rationality of the clock frequency in the corresponding relationship can be ensured.
Based on the first aspect, in a possible design, the determining the correspondence according to a predetermined standard clock size of the E1 link includes: and determining the corresponding relation according to the size of the standard clock and the size of a predetermined reference clock.
In the implementation process, the clock with each clock frequency in the corresponding relation can be obtained by utilizing the size of the reference clock and the size of the standard clock, so that the data shifting-out speed in the register is not required to be controlled by utilizing an additional clock, and the design difficulty of the FPGA is simplified.
Based on the first aspect, in one possible design, before reading a preset byte of data from a data queue to a register, the method further includes: and when the data is determined not to be stored in the register, reading the data of the preset byte from the data queue to the register.
In the implementation process, when it is determined that no data is stored in the register, the data of the preset byte is read from the data queue to ensure that the data of the preset byte can be read into the register at one time, so that the data which is not shifted out from the register is prevented from being covered, and the data of the preset byte is also uniformly shifted out according to a certain selected clock frequency.
In a possible design based on the first aspect, the method further includes: after data written in or read from the data queue is detected each time, determining the data quantity of the data stored in the data queue at the current moment; and updating the signal according to the data quantity.
In the implementation process, the signal for representing the data quantity in the data queue can be updated in time in such a way to ensure that the data stored in the register can be shifted out at an accurate clock frequency in the following process.
In a second aspect, an embodiment of the present application provides a device for suppressing channel associated clock jitter of an E1 link, which is applied to an FPGA, and the device includes: the device comprises a signal acquisition unit, a register and a data storage unit, wherein the signal acquisition unit is used for acquiring a signal representing the data quantity of data stored in a data queue after reading data of preset bytes from the data queue to the register; the clock frequency determining unit is used for determining the corresponding clock frequency according to the signal; and the shifting-out unit is used for shifting out the data in the register from the register according to the corresponding clock frequency.
Based on the second aspect, in a possible design, the clock frequency determining unit is specifically configured to determine the data amount according to the signal; determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size; and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
Based on the second aspect, in one possible design, the apparatus further includes: and the corresponding relation determining unit is used for determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
Based on the second aspect, in a possible design, the correspondence determining unit is specifically configured to determine the correspondence according to a size of the standard clock and a size of a predetermined reference clock.
Based on the second aspect, in one possible design, the apparatus further includes: and the reading unit is used for reading the data of the preset byte from the data queue to the register when the register is determined not to store the data.
Based on the second aspect, in one possible design, the apparatus further includes: the updating unit is used for determining the data quantity of the data stored in the data queue at the current moment after the data written in the data queue or the data read out from the data queue is detected each time; and updating the signal according to the data amount.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor and a memory connected to the processor, where a computer program is stored in the memory, and when the computer program is executed by the processor, the electronic device is caused to perform the method of the first aspect.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute the method of the first aspect.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic flowchart of a method for suppressing a channel associated clock jitter of an E1 link according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a device for suppressing a channel associated clock jitter of an E1 link according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Icon: a channel associated clock jitter suppression device of the 200-E1 link; 210-a signal acquisition unit; 220-a clock frequency determination unit; 230-a removal unit; 300-an electronic device; 301-a processor; 302-a memory; 303-register.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, fig. 1 is a flowchart of a method for suppressing a channel associated clock jitter of an E1 link according to an embodiment of the present application, where the method is applied to an FPGA, and the flowchart shown in fig. 1 will be described in detail below, and the method includes the steps of: s11, S12, and S13.
S11: after reading a predetermined byte of data from a data queue to a register, a signal is obtained that characterizes a data amount of data stored in the data queue.
S12: and determining the corresponding clock frequency according to the signal.
S13: and shifting the data in the register out of the register according to the corresponding clock frequency.
The above method is described in detail below.
As an embodiment, the method further comprises: after acquiring an SDH signal each time, analyzing the SDH signal according to the frame structure of the SDH signal to obtain 63 data of E1 links, where the data of each E1 link includes: 8bit of E1 data, write enable signal and channel number; wherein, the corresponding channel numbers of different E1 links are different, and the E1 link and the channel number are in one-to-one correspondence; and writing the E1 data in the E1 link into a data queue corresponding to the channel number according to the channel number and the write enable signal in the data of the E1 link aiming at the data of each E1 link, wherein the channel number and the data queue are in one-to-one correspondence.
Wherein the write enable signal may be understood as a hint indicating the time to write E1 data into the data queue.
For each data queue, a signal indicative of the amount of data stored in the data queue is used to characterize the state of the data queue.
The information carried in the signal may be the data volume, or water level information representing the size of the data volume; wherein, the water level information has at least two types; in this embodiment, the water level information includes three types, i.e., a low water level, a medium water level, and a high water level, and in other embodiments, the water level information may also include two types, four types, and the like, and is set according to actual requirements.
As one of the values, the water level information is determined according to a predetermined water level information determination criterion.
In this embodiment, the water level information determination criterion may be: when the data volume is determined to be smaller than or equal to a first preset value, determining that the water level information is a low water level; when the data volume is larger than the first preset value and smaller than or equal to a second preset value, determining that the grade information is a middle water level; and when the data volume is determined to be larger than the second preset value, determining that the grade information is a high water level.
The first preset value, the second preset value and the third preset value are set according to actual requirements, and are not limited herein.
In other embodiments, the water level information determination criterion may be other.
As an embodiment, the method further comprises the steps of: a1 and a 2.
A1: and after detecting that data is written into or read from the data queue each time, determining the data quantity of the data stored in the data queue at the current moment.
In practical implementation, a1 may be implemented in such a way that, after each detection of at least one byte of data being written or at least one byte of data being read in the data queue, the data amount of the data stored in the data queue at the current time is obtained.
A2: and updating the signal according to the data quantity.
In an actual implementation process, a2 may be implemented in such a manner that, using the data size, the data size information carried in the signal corresponding to the data queue is updated.
As an implementation manner, when the water level information is carried in the signal, the water level information corresponding to the data volume is determined according to the data volume and the water level information determination criterion.
As an embodiment, before S11, the method further includes the steps of: B1.
b1: and when the data is determined not to be stored in the register, reading the data of the preset byte from the data queue to the register.
One data queue corresponds to at least one register, and one register corresponds to one data queue.
In an actual implementation process, B1 may be implemented in such a manner that, for each register, the state information of the register is obtained in real time, and when the state information of the register is determined to be in an idle state, it is characterized that no data is stored in the register, and at this time, data of preset bytes is read in parallel from a data queue corresponding to the register according to a first-in first-out principle into the register.
In other embodiments, the preset byte may also be two bytes, three bytes, or the like, and the preset byte is determined according to the size of the data amount that can be stored in the register, where the preset byte is less than or equal to the size of the data amount that can be stored in the register.
S11: after reading a predetermined byte of data from a data queue into a register, a signal is obtained that characterizes a data amount of data stored in the data queue.
The number of the data queues may be one, two or more, as long as the number of the data queues is guaranteed to be consistent with the number of the E1 links. In the present embodiment, the number of data queues is 63.
The information carried in the signal may be the data volume, or may be water level information representing the size of the data volume.
It will be appreciated that as data in the data queue is continually read or written, the signal indicative of the amount of data stored in the data queue is continually updated.
In practical implementation, S11 may be implemented in such a way that, when the number of data queues is at least two, after reading a predetermined byte of data from the data queue to the register, for each data queue, a signal corresponding to the data queue and indicating the amount of data stored in the data queue is found, so as to ensure that the subsequent shift-out rate for shifting out the predetermined byte of data from the register can be accurately determined.
As an embodiment, S11 may be implemented by directly obtaining a signal representing the data amount of the data stored in the data queue after reading a predetermined byte of data from the data queue to a register when the data queue is one, so as to ensure that the shift-out rate of the predetermined byte of data from the register can be accurately determined subsequently.
After the signal is acquired, step S12 is executed.
S12: and determining the corresponding clock frequency according to the signal.
As an embodiment, S12 includes the steps of: c1, C2, and C3.
C1: and determining the data volume according to the signal.
In an actual implementation process, C1 may be implemented in such a manner that, when information carried in the signal is a data amount, the data amount is extracted from the signal.
C2: and determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size.
In practical implementation, C2 may be implemented by comparing the data amount with at least two data ranges divided according to the range division criterion, to determine the data range in which the data amount is located, i.e., the data range corresponding to the data amount.
The range division criterion is set according to actual requirements, and the data range divided according to the range division criterion is consistent with the data range in the corresponding relation between the predetermined data range and the clock frequency.
As an embodiment, the step of determining the correspondence includes: and determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
Determining at least two data ranges according to a predetermined data range division criterion, and determining a one-to-one correspondence relationship between the data ranges and the clock frequencies according to the size of the standard clock and the at least two data ranges, wherein the clock frequency corresponding to the data range with a larger mean value in the data ranges is larger than the clock frequency corresponding to the data range with a smaller mean value; the number of data ranges is consistent with the number of clock frequencies;
wherein, the difference between the magnitude of each clock frequency in the corresponding relation and the standard clock is less than or equal to a preset value; the preset value is set according to actual requirements, in this embodiment, the preset value is 0.054, in other embodiments, the preset value may be 0.001, 0.002, 0.008, and the like, wherein the smaller the preset value is, the closer the clock frequency is to the standard clock.
For example, when the standard clock is 2.048Mhz, the clock frequencies may be 1.99Mhz, 2.046Mhz, and 2.102Mhz, respectively, assuming that the number of the at least two data ranges is three; the clock frequencies may also be 2.033Mhz, 2.048Mhz, and 2.101Mhz, respectively.
As another embodiment, the step of determining the correspondence includes: and determining the corresponding relation according to the size of the standard clock and the size of a predetermined reference clock.
Determining at least two data ranges according to a predetermined data range division criterion, and determining a one-to-one correspondence relationship between the data ranges and the clock frequencies according to the size of the standard clock, the size of the reference clock and the at least two data ranges, wherein the clock frequency corresponding to the data range with a larger mean value in the data ranges is larger than the clock frequency corresponding to the data range with a smaller mean value; the number of data ranges is consistent with the number of clock frequencies;
wherein, the difference between the magnitude of each clock frequency in the corresponding relation and the standard clock is less than or equal to a preset value; the preset value is set according to actual requirements, in this embodiment, the preset value is 0.054, in other embodiments, the preset value may be 0.001, 0.002, 0.008, and the like, wherein the smaller the preset value is, the closer the clock frequency is to the standard clock.
For example, when the standard clock is 2.048Mhz and the reference clock is 77.76Mhz, assuming that the number of the at least two data ranges is three, 1/39, 1/38 and 1/37 of the reference clock can be used to obtain clocks with clock rates of 1.99Mhz, 2.046Mhz and 2.102Mhz, respectively, and then the clock frequencies in the correspondence relationship are determined to be 1.99Mhz, 2.046Mhz and 2.102Mhz, respectively.
After the corresponding data range is determined, step C3 is performed.
C3: and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
In practical implementation, C3 may be implemented in such a way that, according to the corresponding data range, the clock frequency corresponding to the corresponding data range is found from the predetermined correspondence between the data range and the clock frequency.
When the information carried in the signal belongs to water level information, as one embodiment, S12 includes the steps of: d1, D2 and D3.
D1: and determining water level information according to the signal.
In practical implementation, D1 may be implemented as follows, and the target water level information is extracted from the signal.
D2: and searching the clock frequency corresponding to the target water level information from the corresponding relation between the predetermined water level information and the clock frequency.
In practical implementation, D2 may be implemented in such a way that, according to the target water level information, the clock frequency corresponding to the target water level information is found from the predetermined correspondence between the water level information and the clock frequency.
As an embodiment, the step of determining the correspondence between the water level information and the clock frequency includes: and determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
According to the size of a standard clock of a predetermined E1 link and the number of the types of the predetermined water level information, at least two different clock frequencies which are the same as the number of the types are determined, and then according to the types of the water level information, a one-to-one correspondence relation between the water level information and the clock frequencies is determined, wherein the clock frequency corresponding to the water level information with a high water level is greater than the clock frequency corresponding to the water level information with a low water level.
The difference between each clock frequency in the corresponding relationship between the water level information and the clock frequency and the standard clock is less than or equal to a preset value, wherein the preset value is set according to actual requirements, in this embodiment, the preset value is 0.054, and in other embodiments, the preset value may be other.
For example, when the standard clock is 2.048Mhz, the clock frequencies may be 1.99Mhz, 2.046Mhz, and 2.102Mhz, respectively, assuming that the types of the water level information are three; the clock frequencies may also be 2.033, 2.048, and 2.101Mhz, respectively.
As another embodiment, the step of determining the correspondence between the water level information and the clock frequency includes: and determining the corresponding relation according to the size of the standard clock and the size of a predetermined reference clock.
Determining a one-to-one correspondence relationship between water level information and clock frequency according to the size of the standard clock, the size of the reference clock and the type of the predetermined water level information, wherein the clock frequency corresponding to the water level information with a high water level is greater than the clock frequency corresponding to the water level information with a low water level;
the difference value between each clock frequency in the corresponding relation between the water level information and the clock frequency and the standard clock is smaller than or equal to a preset value; the preset value is set according to actual requirements, in this embodiment, the preset value is 0.054, in other embodiments, the preset value may be 0.001, 0.002, 0.008, and the like, wherein the smaller the preset value is, the closer the clock frequency is to the standard clock.
For example, when the standard clock is 2.048Mhz, and the reference clock is 77.76Mhz, assuming that the number of types of water level information is three, clocks with clock rates of 1.99Mhz, 2.046Mhz, and 2.102Mhz can be obtained using 1/39, 1/38, and 1/37 of the reference clock, and then the clock frequencies in the correspondence relationship between the water level information and the clock frequencies are determined to be 1.99Mhz, 2.046Mhz, and 2.102Mhz, respectively.
After the corresponding clock frequency is determined, step S13 is performed.
S13: and shifting the data in the register out of the register according to the corresponding clock frequency.
And serially shifting the data in the register out of the register by using a clock with the clock frequency corresponding to the clock frequency and taking bit as a unit, wherein the data of 1 bit in the register is only shifted out of the register at one time.
Referring to fig. 2, fig. 2 is a block diagram of a device 200 for suppressing a channel associated clock jitter of an E1 link according to an embodiment of the present disclosure, where the device is applied to an FPGA. The block diagram of fig. 2 will be explained, and the apparatus shown comprises:
a signal obtaining unit 210, configured to obtain a signal representing a data amount of data stored in a data queue after reading data of a preset byte from the data queue to a register;
a clock frequency determining unit 220, configured to determine a corresponding clock frequency according to the signal;
a shifting unit 230, configured to shift the data in the register out of the register according to the corresponding clock frequency.
As an embodiment, the clock frequency determining unit 220 is specifically configured to determine the data amount according to the signal; determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size; and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
As an embodiment, the apparatus further comprises: and the corresponding relation determining unit is used for determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
As an embodiment, the correspondence determining unit is specifically configured to determine the correspondence according to a size of the standard clock and a size of a predetermined reference clock.
As an embodiment, the apparatus further comprises: and the reading unit is used for reading the data of the preset byte from the data queue to the register when the register is determined not to store the data.
As an embodiment, the apparatus further comprises: the updating unit is used for determining the data quantity of the data stored in the data queue at the current moment after the data written in the data queue or the data read out from the data queue is detected each time; and updating the signal according to the data amount.
For the process of implementing each function by each functional unit in this embodiment, please refer to the content described in the embodiment shown in fig. 1, which is not described herein again.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an electronic device 300 according to an embodiment of the present disclosure, where the electronic device 300 may be a Personal Computer (PC), a tablet PC, a smart phone, a Personal Digital Assistant (PDA), or the like.
The electronic device 300 may include: memory 302, processor 301, registers 303, and a communication bus for enabling communications of the connections of these components.
The Memory 302 is used for storing various data such as a computer program instruction corresponding to the method and the device for suppressing the Random Access clock jitter of the E1 link provided in the embodiment of the present application, where the Memory 302 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like.
The processor 301 is configured to obtain a signal representing a data amount of data stored in a data queue after reading a preset byte of data from the data queue to a register; determining a corresponding clock frequency according to the signal; and shifting the data in the register out of the register according to the corresponding clock frequency.
The processor 301 may be an integrated circuit chip having signal processing capabilities. The Processor 301 may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
A register 303 for storing data.
In addition, an embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute the method provided in any embodiment of the present application.
In summary, according to the method, the apparatus, and the electronic device for suppressing the channel associated clock jitter of the E1 link provided in the embodiments of the present application, when reading the data of the preset byte from the data queue to the register, the corresponding clock frequency is determined according to the signal representing the data amount of the data stored in the data queue, and it can be understood that the clock frequency is in a certain relationship with the data amount of the data stored in the data queue, and then the data in the register can be stably shifted out of the register according to the corresponding clock frequency, so that the problem in the prior art that the shift-out rate jitter of the data is very large due to the very large channel associated clock jitter of the E1 link carried by the SDH is solved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based devices that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
Claims (10)
1. A method for suppressing the channel associated clock jitter of an E1 link is applied to an FPGA (field programmable gate array), and comprises the following steps:
after reading data of preset bytes from a data queue to a register, acquiring a signal representing the data quantity of the data stored in the data queue;
determining a corresponding clock frequency according to the signal;
and shifting the data in the register out of the register according to the corresponding clock frequency.
2. The method of claim 1, wherein determining the corresponding clock frequency from the signal comprises:
determining the data volume according to the signal;
determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size;
and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
3. The method of claim 2, wherein prior to said finding a clock frequency corresponding to said corresponding data range, said method further comprises:
and determining the corresponding relation according to the size of the standard clock of the predetermined E1 link.
4. The method according to claim 3, wherein the determining the correspondence according to the predetermined standard clock size of the E1 link comprises:
and determining the corresponding relation according to the size of the standard clock and the size of a predetermined reference clock.
5. The method of claim 1, wherein prior to reading the predetermined byte of data from the data queue to the register, the method further comprises:
and when the data is determined not to be stored in the register, reading the data of the preset byte from the data queue to the register.
6. The method of claim 1, further comprising:
after data written in or read from the data queue is detected each time, determining the data quantity of the data stored in the data queue at the current moment;
and updating the signal according to the data quantity.
7. A device for suppressing the jitter of the associated clock of the E1 link, which is applied to the FPGA, and is characterized in that the device further comprises:
the device comprises a signal acquisition unit, a register and a data storage unit, wherein the signal acquisition unit is used for acquiring a signal representing the data quantity of data stored in a data queue after reading data of preset bytes from the data queue to the register;
the clock frequency determining unit is used for determining the corresponding clock frequency according to the signal;
and the shifting-out unit is used for shifting out the data in the register from the register according to the corresponding clock frequency.
8. The apparatus according to claim 7, wherein the clock frequency determining unit is specifically configured to determine the data amount according to the signal; determining a data range corresponding to the data volume according to the data volume and a predetermined range division criterion of the data size; and searching the clock frequency corresponding to the corresponding data range from the corresponding relation between the predetermined data range and the clock frequency.
9. An electronic device comprising a memory and a processor, the memory having stored therein computer program instructions that, when read and executed by the processor, perform the method of any of claims 1-6.
10. A computer-readable storage medium having stored thereon computer program instructions which, when read and executed by a computer, perform the method of any one of claims 1-6.
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