CN111741235A

CN111741235A - Multi-channel video switching method based on FPGA

Info

Publication number: CN111741235A
Application number: CN202010825524.XA
Authority: CN
Inventors: 刘政春; 龙波
Original assignee: Chengdu Zhimingda Electronic Co ltd
Current assignee: Chengdu Zhimingda Electronic Co ltd
Priority date: 2020-08-17
Filing date: 2020-08-17
Publication date: 2020-10-02
Anticipated expiration: 2040-08-17
Also published as: CN111741235B

Abstract

The invention discloses a multi-channel video switching method based on an FPGA (field programmable gate array): collecting video data to form a plurality of paths of video data streams and inputting the video data streams to a chip; normal sampling and processing are carried out on the rising edge; and using a high-frequency-multiplication clock to compare the relative positions of the register of each path of video data and the high-frequency-multiplication sampling register. Switching the clock domain of the path of video data from the associated clock domain to a high frequency multiplication clock domain; and each path of output is designed with an asynchronous FIFO, video data streams under multiple paths of high frequency multiplication clock domains are selected, and the video streams are output. The invention uses FIFO resources in the chip to combine with the clock domain crossing circuit to obtain a novel switching method.

Description

Multi-channel video switching method based on FPGA

Technical Field

The invention relates to the technical field of video processing, in particular to a multi-channel video switching method based on an FPGA (field programmable gate array).

Background

At present, the video sensor is widely applied in the military field and is widely used on military equipment such as photoelectric reconnaissance, accurate guidance, intelligent monitoring and the like. Video sensors are commonly used as data sources for video image processing, providing image data of various specifications and sizes. With the development and progress of military technology, the number of video sensors on equipment is continuously increased, and the requirements on volume, power consumption and cost are more and more strict.

The traditional multi-channel video sensor equipment is especially embedded equipment, the cost, the volume and the power consumption are severely limited, and the common implementation scheme is as follows: adding high-speed caches such as DDR3, DDR4 and the like; a dedicated video signal switching chip is employed.

However, the above schemes have application limitations, for example, selecting a professional chip greatly increases the cost and area of the system, and increasing the cache memory increases both the area and the power consumption of the system.

Disclosure of Invention

The present invention aims to solve the above problems and provide a method for switching multiple videos based on an FPGA.

The invention realizes the purpose through the following technical scheme:

a multi-channel video switching method based on FPGA comprises the following steps:

s1, collecting video data by a plurality of paths of video sensors, forming a plurality of paths of video data streams and inputting the video data streams to the FPGA;

s2, carrying out normal sampling and processing on the video stream data of each input path on the rising edge;

s3, adopting a high frequency multiplication clock, restraining the relative position of the register of each path of video data and the high frequency multiplication sampling register to the adjacent position by using the FPGA position, and switching the clock domain of the path of video data from the associated clock domain to the high frequency multiplication clock domain when the high frequency multiplication sampling register samples;

s4, switching the multi-channel video data to a high-frequency multiplication clock domain by using the clock domain crossing device defined by the S3;

s5, according to the output requirement, each path of output corresponds to an asynchronous FIFO, video data streams under multiple paths of high frequency multiplication clock domains are selected, and the asynchronous FIFOs are used for stable switching;

and S6, reading the video stream data from the asynchronous FIFO of the output path, and finishing the switching output of the multi-path video.

Specifically, in steps S3 and S4, the input video streams of multiple different clock domains are switched to the same high-magnification clock domain by the position constraint of the high-magnification clock and the register in the FPGA.

Specifically, in step S5, the high-frequency-multiplication clock and the output clock are both input to the asynchronous FIFO, which is used as a buffer between the high-frequency-multiplication clock domain and the output clock domain to complete the conversion from the high-frequency-multiplication clock domain to the output clock domain, and at the same time, the design of the upper and lower waterlines is adopted to allow the waterline to float within a set range.

The invention has the beneficial effects that:

the invention relates to a multi-channel video switching method based on FPGA, which uses FIFO resources in an FPGA chip to be combined with a clock domain crossing circuit to obtain a novel switching method with less resource consumption and settable video data number.

Drawings

FIG. 1 is a use scenario in accordance with the present invention;

FIG. 2 is a switching relationship of clock domains according to the present invention;

FIG. 3 is a block diagram of a cross-clock domain design according to the present invention;

FIG. 4 is a cross-clock domain timing relationship according to the present invention;

FIG. 5 is a cache design according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

To make the objects, technical solutions and advantages of the present invention clearer, the present invention is further described below with reference to the accompanying drawings:

taking a system in which the video data stream is a 27M clock domain signal and there are multiple inputs and outputs, where the number of inputs is N and the output is X, as shown in fig. 1, multiple input video streams and their associated clocks are simultaneously input to the multiple video switching circuit, and one or multiple of the output video streams to the X outputs can be selected according to the output requirement, and the multiple outputs all need to be output and switched simultaneously.

As shown in fig. 2, taking the X-th output video stream as an example, the difficulty is that there are N possible input video sources for each output. For FPGA digital circuit design, the video stream data of N clock domains needs to be switched to the clock domain of the X path. The overall system, if there are X outputs, then a total of N times X clock domains need to be switched. Although the clock frequency of the video streams is the same in a general multi-channel video system, the influence of frequency offset can be removed even by adopting a homologous design. However, since both the clock switch and the selector in the FPGA have path delay, the internal physical routing of the clock N and the output clock are different, which causes a phase difference between the output clock domain and the input clock domain except for the frequency difference. Therefore, in a common video switching scheme, an asynchronous FIFO or an external buffer is used as a method for crossing clock domains, for a video system with N-way input and X-way output, N times X asynchronous FIFOs or corresponding external buffer spaces are required, the scale is very large, and once the number of N and X of the system is large, the cost and the power consumption of the system are very unacceptable.

s1, collecting video data by a plurality of paths of video sensors, forming a plurality of paths of video data streams to be input to the FPGA, and assuming that N paths of input video data streams and X paths of output video streams exist;

s3, as shown in fig. 3, using a high-frequency-multiplication clock, constraining the relative positions of the D flip-flop (channel associated clock domain) and the high-frequency-multiplication sampling D flip-flop (high-frequency-multiplication clock domain) of each channel of video data to adjacent positions using FPGA position constraint.

And S4, converting the N video streams into a high-magnification clock domain by using the clock domain crossing device defined by the S3 and the N clock domain crossing devices defined by the S3. At the moment, the problem of multiple clock domains does not exist, simple sequential logic can be designed according to the selection relation of output, and the formulated input video stream is selected to a required output channel;

the clock frequency of the video stream is assumed to be 27MHz, and the high frequency multiplication clock selected is 200 MHz. Physical constraints are adopted for registers crossing clock domains, and the positions of two stages of flip-flops are constrained within adjacent FPGASLICE resource space, so that the delay from a first stage D flip-flop to a second stage D flip-flop is far less than 1 ns. When the channel associated clock is at the rising edge, the video data stream is normally processed in the logic, and when the cross clock detects the falling edge of the channel associated clock, the video data stream is forwarded to the cross clock domain; when the falling edge of the associated clock is detected by adopting 200MHz, the time which is more than 10ns away from the rising edge of the clock is already passed, at the moment, the data can be considered to be stable and reliable, the establishment and the retention time of the second-stage D trigger are met, and the time sequence relation is shown in figure 4.

S5, as shown in fig. 5, each of the X outputs is correspondingly configured with an asynchronous FIFO, and only X asynchronous FIFOs are needed. The write-in end of each asynchronous FIFO adopts 0-N paths of video streams selected according to the output requirement in S5, the read-out end adopts an output associated clock to read, and the signals are output through sequential logic, so that the signal stability is improved. Because of the particularity of video stream, the speed is generally stable, therefore, each asynchronous FIFO is designed as an elastic buffer, an upper water level line and a lower water level line are arranged, and the water level lines are only allowed to float in a set range, so as to prevent read-write collision. When a certain path of input source is selected for output, the read-write clock of the elastic cache corresponding to the path of input signal only has phase difference, and the water level line is constant after the read-write clock is stable.

The multi-channel video switching method designed by the invention can complete the random switching and the simultaneous output of N-channel input video streams and X-channel output video streams only by using X groups of asynchronous FIFO, ensures the stability and the reliability of the system to the maximum extent, and reduces the requirements on cost and power consumption.

Extra external cache is not needed, switching is completed only by using FPGA internal resources, and cache resources only use X-path asynchronous FIFO, so that the resource utilization rate is greatly reduced.

In the description above, references to "one embodiment," "an embodiment," "one example," "an example," etc., indicate that the embodiment or example so described may include a particular feature, structure, characteristic, property, element, or limitation, but every embodiment or example does not necessarily include the particular feature, structure, characteristic, property, element, or limitation. Moreover, repeated use of the phrase "in accordance with an embodiment of the present application" although it may possibly refer to the same embodiment, does not necessarily refer to the same embodiment.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-channel video switching method based on FPGA is characterized in that: the method comprises the following steps:

2. The FPGA-based multi-channel video switching method according to claim 1, wherein: in steps S3 and S4, the input video streams of multiple different clock domains are switched to the same high-magnification clock domain by the position constraint of the high-magnification clock and the register in the FPGA.

3. The FPGA-based multi-channel video switching method according to claim 1, wherein: in step S5, the high-frequency-multiplication clock and the output clock are both input to the asynchronous FIFO, which is used as a buffer between the high-frequency-multiplication clock domain and the output clock domain to complete the conversion from the high-frequency-multiplication clock domain to the output clock domain, and at the same time, the design of an upper and a lower waterline is adopted to allow the waterline to float within a set range only.