JP4947088B2 - Method and apparatus for driving plasma display - Google Patents

Method and apparatus for driving plasma display Download PDF

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JP4947088B2
JP4947088B2 JP2009095532A JP2009095532A JP4947088B2 JP 4947088 B2 JP4947088 B2 JP 4947088B2 JP 2009095532 A JP2009095532 A JP 2009095532A JP 2009095532 A JP2009095532 A JP 2009095532A JP 4947088 B2 JP4947088 B2 JP 4947088B2
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voltage
reset
subfield
voltage value
discharge
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JP2009151345A (en
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一隆 中
健夫 増田
通孝 大沢
広 大高
尊久 水田
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株式会社日立製作所
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  The present invention relates to a plasma display driving method and apparatus, and more particularly to a control voltage driving method and apparatus for controlling discharge of discharge cells in a plasma display.

  In recent years, flat panel display devices sealed with liquid crystal or plasma, which are thin and light, have little screen distortion, and are less susceptible to geomagnetism, are becoming popular in place of conventional cathode ray tube (CRT) display devices. .

  Among these, in particular, a plasma display device that is self-luminous, has a wider viewing angle, and is relatively easy to produce a large panel is attracting attention as a next-generation color image display device.

  In such a plasma display device, as shown in FIG. 9, pixels 900 serving as a minimum unit of display are two-dimensionally arranged corresponding to horizontal and vertical resolutions. Further, one pixel 900 includes three discharge cells, a red (R) discharge cell 901, a green (G) discharge cell 902, and a blue (B) discharge cell 903. Color display is realized by controlling the amount of light emitted from the discharge cells 901, 902, and 903.

  Next, FIG. 10 shows an outline of the electrode structure of each discharge cell of a general three-electrode AC plasma display.

  In FIG. 10, 901, 902, and 903 are red (R), green (G), and blue (B) discharge cells, 910 is a common sustain electrode, 911 is an independent sustain electrode in units of lines, 907, Reference numerals 908 and 909 denote address electrodes.

  In order to cause the discharge cells 910, 902, and 903 to emit light, an environment in which discharge easily occurs in the discharge cell by address discharge between the address electrodes 907, 908, and 909 and the independent sustain electrode 911, and the common sustain electrode during the sustain pulse period. A sustain pulse is applied between 910 and the independent sustain electrode 911. As a result, the cells designated by the address discharge are discharged during the address control period.

  The phosphors 904, 905, and 906 applied in the cell emit light by ultraviolet rays generated by this discharge, and R, G, and B light are emitted.

  Note that the emission intensity is substantially proportional to the number of sustain pulses.

  In the plasma display device, a so-called subfield method is employed as a method for displaying the intermediate gradation by controlling the light emission amount of each of the R, G, and B discharge cells. In this sub-field method, as shown in FIG. 11, one field is divided into a plurality of sub-fields on the time axis, a specific light emission weight is assigned to each sub-field, and the presence / absence of light emission in each sub-field is controlled. Thus, the luminance gradation is expressed.

  FIG. 11 shows an example in which one field is divided into six subfields SF0 to SF5. In the example shown in FIG. 11, in the subfield SF0 at the head of the field, an all reset period 90a in which reset discharge is unconditionally performed on all the discharge cells, and an address period 92a following this period 90a, And a sustain period 93a.

  Subfields SF1 to SF5 other than subfield SF0 are configured by SF reset periods 91b to 91f, address periods 92b to 92f, and sustain periods 93b to 93f that selectively reset discharge only the discharge cells emitted in the previous subfield. Has been.

  The number of sustain pulses is such that the ratio of the luminance emitted in each of the sustain periods 93a, 93b, 93c, 93d, 93e, and 93f from the subfields SF0 to SF5 is 1: 2: 4: 8: 16: 32. Is set. Then, depending on the combination of the number of pulses in these subfields, the gradation “0” at which none of the subfields SF0 to SF5 emits light to the gradation “63” at which all of the six subfields SF0 to SF5 emit light (= 1 + 2 + 4 + 8 + 16 + 32). 64 gradations can be expressed.

  In the subfield reset periods 91b to 91f provided in these subfields SF1 to SF5, only the discharge cells that have emitted light in the previous subfield are selectively reset and initialized, and thus light emission due to unnecessary reset discharge is caused. Display with high contrast can be suppressed.

  A driving method using a combination of the two types of reset discharges of the total reset period and the subfield reset period as described above is described in detail in, for example, Patent Document 1 and Patent Document 2.

JP-A-8-278766 Japanese Patent Laid-Open No. 10-3281

  However, if the voltage value of the subfield reset pulse for initializing the discharge cell is high, discharge occurs only at the rising edge of the reset pulse, and wall charges are formed. When such wall charges are formed, even in a discharge cell that does not perform address discharge, light emission is caused by a sustain pulse, and a bright spot is generated in an originally black image region, thereby degrading image quality.

  In addition, if the voltage value of the reset pulse is high, a discharge due to the rising edge of the reset pulse is likely to occur due to charge leakage in the vicinity of the light emitting discharge cell. Occurs, and the image quality deteriorates remarkably.

  Conversely, if the voltage value of the subfield reset pulse is set low, there is a problem that the reset discharge is not performed correctly even if the immediately preceding subfield is lit and malfunctions.

  Generally, the above-mentioned problems can be avoided by setting the voltage of the subfield reset pulse to a voltage value at which a desired reset operation can be performed without causing bright spots or line blurring in the black region. It is.

  However, if the interval between the discharge cells is made narrower in order to increase the definition and resolution of the display panel, it becomes more susceptible to charge leakage from the adjacent discharge cells, and the edge Bleeding is likely to occur in parts and lines. For this reason, in order not to generate bright spots and line blurs in the black region, it is necessary to set the voltage value of the subfield reset pulse to be lower.

  On the other hand, in order to perform a desired reset discharge without malfunction, the voltage value of the reset pulse needs to be equal to or higher than a predetermined voltage value, does not cause blurring of bright spots and lines in the black region, and is desired without malfunction. There has been a problem that the width of the set voltage that satisfies the conditions for performing the reset discharge becomes narrow, or there is no voltage that satisfies the conditions. This makes it difficult to drive the display panel stably without malfunction.

  As described above, in a high-definition / high-resolution plasma display device, it is easily affected by the discharge of adjacent cells, so that only a few cells on the display panel emit light and most cells on the display panel emit light. In this case, the discharge environment of each discharge cell changes greatly.

  For this reason, the optimal voltage value of the control pulse varies depending on the number of light emitting cells in the screen and the number of light emitting cells is small, and the operation margin becomes small (or the margin disappears) at a fixed voltage setting. It is difficult to increase the image quality by reducing the interval between the display panel and the display panel with high definition and high resolution.

  An object of the present invention is to drive a plasma display capable of stably driving a display panel without malfunction and displaying high-quality images even when the interval between discharge cells is narrowed. Implementing a method and apparatus.

  In order to achieve the above object, the present invention is configured as follows.

  (1) In a plasma display driving method that includes a plurality of discharge cells and displays a video signal by a control pulse for controlling discharge and a driving pulse for emitting light from the discharge cell, the voltage of the control pulse is determined according to the display content of the video signal. To control.

  (2) Preferably, in the above (1), the voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen.

  (3) Preferably, in the above (1) or (2), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse initializes the discharge cell for each subfield. This is a subfield reset pulse.

  (4) Preferably, in the above (1) or (2), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is emitted from each discharge cell for each subfield. This is an address control pulse for controlling presence or absence.

  (5) Preferably, in the above (1), (2), (3) or (4), the plasma display is a three-electrode AC type.

  (6) Further, in a plasma display driving apparatus that is constituted by a plurality of discharge cells and displays a video signal by a control pulse for controlling discharge and a driving pulse for causing the discharge cell to emit light, a control pulse according to the display content of the video signal The control means which controls the voltage of is provided.

  (7) Preferably, in (6) above, the voltage of the control pulse is controlled based on the number of cells or pixels that emit light at a certain luminance or higher in the screen.

  (8) Preferably, in (6) above, the one-field image is divided into a plurality of subfields, and the voltage-controlled control pulse is a subfield reset pulse for initializing discharge cells for each subfield. It is.

  (9) Preferably, in the above (6) or (7), one field image is divided into a plurality of subfields, and the voltage-controlled control pulse is emitted from each discharge cell for each subfield. This is an address control pulse for controlling presence or absence.

  (10) Preferably, in the above (6), (7), (8) or (9), the plasma display is a three-electrode AC type.

  If it is configured to control the voltage of the control pulse according to the display content of the video signal, the display image is appropriately displayed depending on whether only a few discharge cells emit light or most discharge cells emit light. The image quality can be improved by control.

  Further, when the black display area is large and the priming effect from the adjacent discharge cells is small, the address discharge can be surely performed by increasing the address application voltage.

  Since the present invention is configured as described above, it has the following effects.

  The subfield reset pulse voltage is controlled in accordance with the ratio of light emitting pixels in one screen, and when the light emission ratio is high, the subfield reset pulse voltage is increased, so the interval between the discharge cells is narrowed. Even in this case, it is possible to prevent bright spots and lines from blurring on a dark screen, reliably execute reset discharge on a bright screen, and drive the display panel stably without malfunction. A plasma display driving method and apparatus capable of displaying high-quality images can be realized.

It is a block diagram which shows schematic structure of the display drive apparatus of the plasma display which is one Embodiment of this invention. It is a wave form diagram of the drive signal of the 1st subfield (SF0). It is a wave form diagram of the drive signal of the 2nd subfield (SF1). It is a characteristic view which shows the control characteristic of the subfield reset voltage with respect to the light emission pixel ratio. FIG. 2 is a block diagram illustrating a configuration of a detection circuit 4 illustrated in FIG. 1. It is a block diagram which shows the structure of the voltage control part of the control pulse power supply shown in FIG. It is a characteristic view which shows the other control characteristic of the subfield reset voltage with respect to the light emission pixel ratio. It is a block diagram which shows the structure of the amplitude limiting circuit provided in the inside of a control pulse power supply. It is explanatory drawing explaining the pixel and discharge cell of a display panel. It is explanatory drawing explaining the electrode arrangement | positioning of a discharge cell. It is explanatory drawing which shows arrangement | positioning of the subfield in 1 field.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a display driving device of a plasma display which is an embodiment of the present invention.

  In FIG. 1, 1 is an A / D conversion circuit that converts a red (R) signal into digital data, 2 is an A / D conversion circuit that converts a green (G) signal into digital data, and 3 is a blue (B) signal. It is an A / D conversion circuit for converting into digital data. Reference numeral 7 denotes a signal processing circuit. The signal processing circuit 7 is a circuit that performs processing necessary for display on the R, G, and B digital signals from the A / D conversion circuits 1, 2, and 3.

  Reference numeral 8 denotes a drive circuit. The drive circuit 8 inserts a control pulse necessary for panel display into the signal from the signal processing circuit 7 and converts it into a voltage or current necessary for lighting the display panel. Circuit. Reference numeral 9 is a display panel using a plasma display, and 4 is a detection circuit that detects the light emission ratio of the video signal based on the R, G, and B digital data from the A / D conversion circuits 1, 2, and 3. Reference numeral 5 denotes a control pulse power source for determining voltage values of various control pulses inserted by the drive circuit 8, and reference numeral 6 denotes a drive power source for supplying a sustain pulse to the display panel 9.

  The detection circuit 4 is a pattern in which a display image is an image including a lot of black levels, a signal that is easily noticeable in lines, or a pixel having a certain luminance or more emits light over a wide range from R, G, and B digital data. A light emitting pixel ratio (described later) indicating whether or not there is detected.

  The light emitting pixel ratio detected by the detection circuit 4 is input to the control pulse power supply 5 as a signal Vcont, and the control pulse power supply 5 controls the voltage value of the control pulse according to the light emitting pixel ratio. That is, the control pulse power supply 5 controls the subfield reset voltage to be low for an image with a small number of light emitting cells and a low light emitting pixel ratio, and the subfield reset voltage to be high for an image with a high light emitting pixel ratio.

  The control pulse power supply 5 sets the address voltage high for an image with a small light emitting pixel ratio and a low light emitting pixel ratio, and sets the address voltage low for an image with a high light emitting pixel ratio.

  With the above configuration, control pulses such as subfield reset and address can be set to an optimum voltage in accordance with the ratio of light-emitting pixels of a display image, and thus stable display with few malfunctions can be performed. .

  In the plasma display, the main light emission of the panel is performed by applying a sustain pulse, so that the power consumption by the sustain pulse is the largest. For this reason, the drive power supply 6 for generating the sustain pulse is also a circuit corresponding to high power.

  Compared to this, the control pulse power source 5 is a power source for generating control pulses other than sustain pulses such as all resets, subfield resets, and addresses, and is a small circuit for small power compared to the drive power source 6. is there. In the display driving device of the present invention, since the power supply voltage of the control pulse power supply 5 with low power consumption is controlled, it is not necessary to control a large power supply control element, and a stable and high-quality display is achieved by adding a small and simple circuit. It can be performed.

  In the general three-electrode AC system as the plasma display system, a relatively high voltage signal is applied to the sustain electrode, and a low voltage is applied to the address electrode. Therefore, a sustain pulse contributing to light emission can be supplied from the drive power supply 6 to the sustain electrode, and the address voltage can be supplied independently from the control pulse power supply 5 to the address electrode.

  Further, the sub-field reset pulse and all reset pulses are obtained by superimposing and adding the voltage from the control pulse power source 5 to the sustain pulse voltage from the drive power source 6, thereby making the control pulse power source 5 a lower voltage and lower power source. Clearly separable. As described above, in the three-electrode AC type plasma display, the advantage of the present invention for controlling the voltage of the small and small power control pulse power supply 5 becomes remarkable.

  Further, when an image with a large number of lit cells and a high ratio of light emitting pixels is displayed, the power consumption of the sustain pulse for light emission increases. At this time, by controlling the address voltage to be low, Power consumption can be suppressed, and there is an effect of reducing power consumption of the entire display driving device.

  In the configuration example shown in FIG. 1, digital data immediately after A / D conversion is input to the detection circuit 4, and is preceded in time by an amount corresponding to the processing delay in the signal processing circuit 7. Thus, the light emitting pixel ratio can be detected. For this reason, the processing delay time in the signal processing circuit 7 can be assigned to the time delay accompanying the averaging of the detection signals and the control pulse power supply control.

  Therefore, even when the image content changes suddenly, the control pulse voltage can be quickly changed to the optimum value. Moreover, the structure which detects a light emission pixel ratio from the analog signal before A / D conversion may be sufficient.

  In the configuration example shown in FIG. 1, both the subfield reset voltage and the address voltage are controlled. However, either one may be controlled by the light emitting pixel ratio and the other may be a fixed voltage.

  In addition, the configuration is not limited to the subfield reset voltage and address voltage, and the configuration is such that the discharge voltage changes depending on the number of lighting cells, and the voltage of the control pulse that causes the optimum voltage to fluctuate accordingly is controlled by the ratio of light emitting pixels. Thus, it is in line with the spirit of the present invention.

  Hereinafter, specific details of the operation will be described, but for the sake of simplicity, a method and apparatus for controlling only the subfield reset voltage according to the content of the displayed image will be described.

  A driving signal waveform of the display driving apparatus according to the embodiment of the present invention will be described with reference to FIGS.

  FIG. 2 shows an outline of the signal waveform of the first subfield SF0 located at the head of one field, and is composed of three periods of an all reset period 90a, an address period 92a, and a sustain period 93a.

  In the total reset period 90a, a total reset pulse Rpm having a time width of about 10 μs is applied from the common sustain electrode. All reset pulses Rpm are fixed at voltage VR = 340 V, and discharge is generated between the common sustain electrode and the independent sustain electrode. A large amount of wall charge is accumulated between the two sustain electrodes due to the discharge at the rising edge of the previous reset pulse Rpm, but self-erase discharge occurs due to the wall charge between the two sustain electrodes at the falling edge of the total reset pulse Rpm. Is reset.

  A voltage is also applied to the address electrode in accordance with this all reset pulse Rpm, but this is an auxiliary to prevent discharge between the common sustain electrode and the address electrode.

  In the address period 92a, the scan pulse Scp is sequentially applied to the independent sustain electrodes, and line scanning is performed. By applying the address pulse Adp to the line to which the scan pulse Scp is applied during the line scanning, a discharge occurs between the address electrode and the independent sustain electrode. This discharge triggers a transition between the independent sustain electrode and the common sustain electrode, and wall charges are formed.

  By repeating the above operation and performing line scanning, wall charges are formed in desired cells in the display panel.

  In the sustain period 93a following the address period 92a, the sustain pulse Sup is alternately applied to the common sustain electrode and the independent sustain electrode, and the sustain discharge is performed only in the cells in which the wall charges are formed in the address period 92a.

  In the subfields of the second subfield SF1 to the sixth subfield SF5 following the first subfield SF0 shown in FIG. 2, a subfield reset period 91b is provided instead of the all reset period 90a. As an example, the configuration of the second subfield period SF1 is shown in FIG. As shown in FIG. 3, the second subfield SF1 includes three periods of an SF (subfield) reset period 91b, an address period 92b, and a sustain period 93b.

  In the subfield reset period 91b, a subfield reset pulse Rps having a time width of about 1 μs is applied from the common sustain electrode. Since this reset pulse Rps has a short time width of 1 μs compared to all reset pulses Rpm, all cells cannot be discharged unconditionally, and the sustain discharge is performed in the previous subfield, and only the cells are discharged. The discharge is performed.

  This is because in the cells that are lit in the previous subfield, wall charges generated by the sustain discharge remain, so the discharge is performed at a high speed with voltage application, but in the cells that are not lit in the previous subfield, Since it takes time from charge separation to discharge, the fact that discharge does not start with a pulse having a time width of about 1 μs is utilized.

  The configuration of the address period 92b and the sustain period 93b after the subfield reset period 91b is the same as that of the first subfield SF0 shown in FIG. Further, the subsequent subfields SF2 to SF5 are also realized by the same configuration as the first subfield SF0, although the number of repetitions of the sustain pulse for realizing the respective emission weights is different in each subfield. .

  As described above, by selectively causing the reset discharge by the subfield reset pulse Rps, black floating caused by unnecessary reset discharge can be prevented and high-quality display can be performed.

  However, in order to realize a high-definition and high-resolution display panel, when the interval between the discharge cells is narrowed, the space charge from the peripheral light-emitting cells leaks, and is weak at the rising portion of the subfield reset pulse Rps. Discharge may occur and wall charges may be formed. Unlike the correct reset operation, this wall charge is not reset by the self-erasing discharge, so that the subfield that does not emit light originally emits light due to the remaining wall charge.

  When such erroneous light emission occurs, a bright spot on a black screen and blurring of a line cause remarkable image quality deterioration. This erroneous light emission can be avoided by lowering the voltage VRS of the subfield reset pulse Rps. However, if the voltage of VRS is lowered, the original reset discharge cannot be performed correctly, causing a malfunction.

  In the display driving method and apparatus of the present invention, the voltage VRS of the subfield reset pulse Rps is changed according to the content of the display signal. That is, the voltage VRS of the subfield reset pulse Rps is lowered for an image with a small number of light emitting pixels that is easily noticeable in bright spots and lines on a black screen, and the voltage VRS of the subfield reset pulse Rps for an image with a large number of light emitting pixels. By raising the value, a malfunction is prevented and a stable and high-quality display is performed.

  An example of a specific control characteristic of the voltage VRS of the subfield reset pulse Rps is shown in FIG.

  FIG. 4 shows the ratio of how many cells emit light with a specific luminance or more among all discharge cells of one screen on the horizontal axis, and how the subfield reset pulse voltage VRS is plotted on the vertical axis. It shows what to control. The light emitting pixel ratio 0% indicates an all black screen, and the light emitting pixel ratio 100% indicates all white.

  As shown in FIG. 4, in the case of all white display in which all the discharge cells are lit, the subfield reset pulse voltage VRS = 290V is set. In the case of all black display in which all the discharge cells are not lit, The field reset pulse voltage VRS is set to be 250V. Then, as the light emitting pixel ratio is changed from 0% to 100%, the subfield reset pulse voltage VRS is ramped up from 250V and controlled so as to have a linear characteristic of 290V.

  In this way, by controlling the subfield reset pulse voltage VRS according to the light emitting pixel ratio, it is possible to prevent bright spots on the black screen and line blurring, and to accurately perform the reset discharge, and to display a high image quality. Can be realized.

  Next, a specific configuration of the detection circuit 4 shown in FIG. 1 will be described with reference to FIG.

  In FIG. 5, 401, 402, and 403 are 2-input OR circuits that perform an OR operation, 404 is a 3-input OR circuit, 405 is a resistor, and 406 is a capacitor. To the input of the OR circuit 401, the most significant bit signal R7 of the R signal converted into a digital signal and the next weight signal R6 are input.

  Further, the most significant bit signal G7 of the G signal converted into the digital signal and the next weight signal G6 are input to the OR circuit 402. Further, the most significant bit signal B7 of the B signal converted into the digital signal and the next weight signal B6 are inputted to the input of the OR circuit 403.

  The output signals of the OR circuits 401, 402, and 403 are further input to a three-input OR circuit 404, and the OR circuit 404 performs a logical sum operation. The output signal of the OR circuit 404 is smoothed by a CR integration circuit including a resistor 405 and a capacitor 406, and is output as a control signal Vcont.

  The most significant bit signal R7 when digitally converted to an 8-bit signal from 0 to 255 level is "H" level when the level of the R signal is 128 levels or more. The next weight signal R6 becomes “H” level when the level of the R signal is in the range of 64 to 127 and 192 to 255.

  By performing an OR operation of R7 and R6 by the OR circuit 401, a signal that is at “H” level when the level of the R signal is 64 or more can be obtained. Similarly, the output of the OR circuit 402 is a signal that becomes “H” level when the level of the G signal is 64 or more, and the output of the OR circuit 403 is a signal that becomes “H” level when the level of the B signal is 64 or more. It is.

  Further, the output signals of the OR circuits 401, 402, and 403 are logically summed with the three-input OR circuit 404, so that when any of the R, G, and B signals is 64 or higher, the “H” level is set. Can be obtained.

  The signals R7, R6, G7, G6, B7, and B6 are sequentially input to the OR circuits 401, 402, and 403 for all the pixels in one screen, and the output signal of the OR circuit 404 is smoothed by the CR integration circuit. By performing the conversion processing, it is possible to obtain a temporal ratio at which any level of R, G, B signals in one screen is 64 or more as a voltage value, and this voltage value is used as the control signal Vcont. Output.

  By the detection circuit 4 that executes the above-described processing, a signal indicating the ratio of light emitting pixels (64 levels or more) in one display screen can be obtained as an analog voltage value.

  Note that, by setting the time constant of the integrating circuit formed by the resistor 405 and the capacitor 406 to 10 to 20 ms, it is possible to output an average light emitting pixel ratio for one field period. Further, when the output logic level of the OR circuit 404 is “L”, 0V, and when it is “H”, the voltage is 4V. When the pixel ratio is 0%, Vcont = 0V and the pixel ratio is 100%. Since Vcont = 4V, a control voltage substantially proportional to the light emitting pixel ratio can be obtained.

  Next, the control of the control pulse voltage inside the control pulse power supply 5 shown in FIG. 1 will be specifically described. FIG. 6 is a diagram showing a main part of the subfield reset voltage control circuit of the control pulse power supply 5.

  In FIG. 6, 500 is an output control transistor, 501 is an error amplifier, 502 and 503 are resistors having a resistance ratio of 9: 1, 504 is a voltage adding circuit, and 505 is a reference power supply with a reference voltage of 25V.

  The control voltage Vcont from the detection circuit 4 is added to the reference potential 25V of the reference power source 505 by the voltage addition circuit 504 and input to the positive input terminal of the error amplification circuit 501. The output signal of the error amplifier 501 is input to the base of the output control transistor 500, and a subfield reset voltage controlled to a predetermined voltage is output from the emitter of the transistor 500.

  In addition, an unstable voltage of 300 V is applied to the collector of the transistor 500, and the emitter is grounded via resistors 502 and 503. The subfield reset voltage, which is the output of this subfield reset control circuit, is divided into tenths by resistors 502 and 503 and input to the negative input terminal of error amplifier 501.

  With this configuration, the error amplifier 501 controls the output control transistor 500 so that the potential difference between the positive input and the negative input becomes zero. Therefore, the potential obtained by dividing the subfield reset voltage by 1/10 is always an error. Amplifier 501 operates to equal the positive input voltage.

  That is, feedback control is performed so that the subfield reset voltage has a voltage value 10 times the positive input voltage of the error amplifier.

  The operation of the subfield reset voltage control circuit shown in FIG. 6 will be described below.

  When the light emitting pixel ratio is 0% and the control voltage Vcont from the detection circuit 4 is 0V, the voltage value added by the reference voltage 25V of the reference power supply 505 and the voltage addition circuit 504 is 25V and is output. The subfield reset voltage is 10 times 250 V by feedback control.

  When the light emitting pixel ratio is 50%, the control voltage Vcont from the detection circuit 4 is about 2V, and the voltage value added by the reference voltage 25V of the reference power source 505 and the voltage addition circuit 504 is about 27V. . As a result, the output subfield reset voltage is about 270V.

  Next, when the light emitting pixel ratio becomes 100%, the control voltage Vcont from the detection circuit 4 becomes 4V, and the voltage value added by the reference voltage 25V of the reference power supply 505 and the voltage addition circuit 504 becomes 29V. . As a result, the output subfield reset voltage is 290V.

  With the configuration of the subfield reset voltage control circuit as described above, it is possible to control the SF reset voltage with respect to the ratio of the luminescent pixels having the characteristics shown in FIG.

  According to the first embodiment of the present invention described above, the subfield reset pulse voltage is controlled in accordance with the light emitting pixel ratio in one screen, and the subfield reset pulse voltage is increased as the light emission ratio increases from 0%. Because it is configured to increase, even if the interval between discharge cells is narrow, it prevents bright spots and lines from blurring on dark screens and reliably performs reset discharge on bright screens. Thus, it is possible to realize a plasma display driving method and apparatus capable of stably driving a display panel without malfunction and displaying high-quality images.

  Next, a second embodiment of the present invention will be described.

  The second embodiment of the present invention is an example in which the control characteristic of the subfield reset voltage VSR with respect to the light emitting pixel ratio is a non-linear characteristic as shown in FIG. Since the second embodiment is the same as the first embodiment except for the configuration of the subfield reset voltage control circuit, the illustration and detailed description thereof are omitted.

  In FIG. 7, the subfield reset voltage VSR increases linearly with a slope from 250 V when the light emitting pixel ratio exceeds 0% to 25% and exceeds 250%, and increases linearly at 50% to 290 V. Up to 100% is controlled to be 290V.

  In the second embodiment, when the light emission ratio is 0% to 25%, it is possible to reliably prevent bright spots and lines from blurring on a dark screen, and when the light emission ratio is 50% to 100%. Therefore, reset discharge on a bright screen can be executed reliably.

  In the example of FIG. 7, the subfield reset voltage VSR is set to 250 V when the light emission ratio is 0% to 25%. However, the voltage VSR may be set to 250 V up to other light emission ratios. . For example, when the light emission ratio is 0% to 10% and the voltage VSR exceeds 250V and 10%, the voltage increases linearly with an inclination from 250V, reaches 290V at 50%, and reaches 290V from 50% to 100%. It is also possible to control so that

  The non-linear characteristic of the subfield reset voltage as shown in FIG. 7 can be realized by limiting the amplitude of the positive input voltage of the error amplifier circuit 501 by the amplitude limiting circuit as shown in FIG.

  In the amplitude limiting circuit of FIG. 8, reference numerals 506 and 507 denote diodes, and reference numerals 508 and 509 denote limiting voltage sources for determining voltages for limiting the amplitude, and generate voltages V1 and V2 (V1 <V2).

  The terminal A ′ of the amplitude limiting circuit is connected to the anode of the diode 507, and the cathode of the diode 507 is grounded from the positive electrode of the limiting voltage source 509 through the negative electrode. The terminal A ′ of the amplitude limiting circuit is connected to the cathode of the diode 506, and the anode of the diode 506 is grounded from the positive electrode of the limiting voltage source 508 through the negative electrode.

  For ease of explanation, it is assumed that the diodes 506 and 507 perform an ideal operation.

  By connecting the terminal A connected to the positive input terminal of the error amplifier 501 of the subfield reset voltage control circuit shown in FIG. 6 to the terminal A ′ of the amplitude limiting circuit shown in FIG. 8, a diode 507 and a voltage source are connected. 509 is limited so that the voltage of the terminal A does not become higher than the voltage V2, and the diode 506 and the voltage source 508 are limited so that the voltage of the terminal A does not become lower than the voltage V1.

  Specific operations of the subfield reset voltage control circuit and the amplitude limiting circuit are as follows.

  The ratio of the resistance values of the resistors 502 and 503 in FIG. 6 is set to be 39: 1. As a result, the subfield reset voltage, which is the output voltage, is divided by 1/40 by the resistors 502 and 503 and fed back to the negative input terminal of the error amplifier 501. Therefore, a voltage 40 times the positive input voltage of error amplifier 501 is output as the subfield reset voltage.

  The reference voltage of the reference voltage source 505 is set to 5.25V, the amplitude upper limit voltage V2 of the voltage source 509 of the amplitude limiting circuit shown in FIG. 8 is set to 7.25V, and the amplitude upper limit voltage V1 of the voltage source 508 is set to 6.25V. Has been. Further, the detection circuit 4 shown in FIG. 1 outputs a voltage of 0 to 4 V in proportion to the light emitting pixel ratio.

  The control voltage Vcont takes a value of 0 to 1V during the period in which the light emitting pixel ratio is 0 to 25%, and the value added to the voltage 5.25V of the reference voltage 505 by the adding circuit 504 is 5.25 to 6.25V. However, in this range, it is limited to the lower limit voltage 6.25V of the amplitude limiting circuit of FIG.

  As a result, the potential of the terminal A is 6.25V during the period in which the light emitting pixel ratio is 0 to 25%, and the subfield reset voltage is 250V, which is 40 times this, and this voltage 250V is output from the subfield reset voltage control circuit. Is done.

  In a period in which the light emitting pixel ratio is 25 to 50%, the control voltage Vcont becomes a value of 1V to 2V, and a value added by the voltage 5.25V of the reference voltage 505 by the adding circuit 504 becomes 6.25 to 7.25V. Therefore, it is within the amplitude limit range, and 250 (= 6.25 × 40) to 290 (= 7.25 × 40) V corresponding to this voltage is output as the subfield reset voltage.

  Further, when the pixel ratio increases to 50% or more and the control voltage Vcont becomes 2V or more, the voltage added to the voltage 5.25V of the reference voltage source 505 by the adding circuit 504 becomes 7.25V or more. Therefore, the voltage is limited to 7.25V.

  Accordingly, 290 (= 7.25 × 40) V is output in the region where the light emitting pixel ratio is 50% or more.

  By the operation as described above, the control characteristic of the subfield reset voltage with respect to the light emitting pixel ratio shown in FIG. 7 can be realized.

  By realizing the control characteristics of the subfield reset voltage with respect to the light emitting pixel ratio as shown in FIG. 7, the subfield reset voltage is reduced to 250 V in an image with a wide black display region having a light emitting pixel ratio of about 25%. In a bright screen with a light-emitting pixel ratio of 50% or more, the subfield reset voltage can be set to the normal 290 V, and it is possible to reliably prevent malfunctions on a bright screen and to ensure that bright spots and lines are blurred on a dark screen. Can be prevented.

  That is, according to the second embodiment, as in the first embodiment, even when the interval between the discharge cells is narrowed, the bright spots and lines are blurred on the dark screen. To realize a plasma display driving method and apparatus capable of preventing and performing reset discharge on a bright screen, driving a display panel stably without malfunction, and displaying high-quality images Can do.

  In the specific configuration examples shown in FIGS. 2 to 8 described above, the subfield reset voltage is controlled in accordance with the luminescent pixel ratio. However, as shown in the example of FIG. The address voltage may be controlled accordingly. At this time, the voltage VA of the address pulse Adp shown in FIGS. 2 and 3 may be controlled.

  When the light emitting pixel ratio is small and the priming effect from the surrounding pixels is small, the address voltage VA is set high (for example, 75V), and when the light emitting pixel ratio is large, the address voltage VA is set low (for example, 55V). What is necessary is just composition. With such a configuration, the address discharge can be optimally controlled, and there are effects of preventing malfunction and saving power.

  Further, the address voltage control circuit of the control pulse power supply 5 emits light by subtracting the control voltage Vcont from the reference voltage source 505 by replacing the adder circuit 504 of the subfield reset voltage control circuit shown in FIG. The control pulse voltage can be increased when the pixel ratio is low, and the control pulse voltage can be decreased when the pixel ratio is high.

  Further, with respect to the voltage range to be controlled, etc., desired control characteristics are obtained by setting the feedback resistors 502 and 503 and the reference voltage source 505 of the circuit shown in FIG. 6 and the reference voltage sources 506 and 507 shown in FIG. Can be set.

  Note that the voltage of the control pulse is not limited to the subfield reset voltage and address voltage, and the discharge voltage changes due to the influence of adjacent discharge cells depending on the number of light emitting pixels, and the optimum voltage fluctuates accordingly. It is also possible to control so as to be controlled by the ratio of the light emitting pixels.

1, 2, 3 A / D conversion circuit 4 Detection circuit 5 Control pulse power supply 6 Panel drive power supply 7 Signal processing circuit
8 drive circuit 9 display panel 90a total reset period 91b to 91f subfield reset period 92a to 92f address period 93a to 93f sustain period 401, 402 2 input OR gate 403 2 input OR gate 404 3 input OR gate 405, 502 resistance 406 capacitor 500 Output control transistor 501 Error amplifier 503 Resistor 504 Addition circuit 505, 508 Reference voltage source 506, 507 Diode 509 Reference voltage source 900 Display pixel 901 R discharge cell 902 G discharge cell 903 B discharge cell 904 R phosphor 905 G phosphor 906 B phosphor 907, 908 Address electrode 909 Address electrode 910 Common sustain electrode 911 Independent sustain electrode

Claims (2)

  1. A method of driving a plasma display apparatus comprising a plurality of discharge cells, wherein one field image is displayed by a plurality of subfields, and the subfield has a reset period,
    The reset period is a period in which all reset pulses for causing reset discharge to be applied to a plurality of discharge cells constituting one screen, or a subfield reset for causing reset discharge to be performed on discharge cells that have emitted light in the previous subfield. In the period in which the pulse is applied, and in the period in which the subfield reset pulse is applied, the subfield reset is performed when the ratio of discharge cells that emit light at a predetermined luminance or higher with respect to the plurality of discharge cells is a first ratio. When the voltage value of the pulse is the first voltage value and the ratio is a second ratio smaller than the first ratio, the voltage value of the subfield reset pulse is lower than the first voltage value , the driving method of a plasma display apparatus characterized by a second voltage value capable of generating a set discharge
  2. A driving method of a plasma display device according to claim 1,
    The first voltage value and the second voltage value are generated by adding a voltage value corresponding to a ratio of the discharge cells to a voltage value from a first power source having a fixed voltage value,
    A voltage value corresponding to the ratio of the discharge cells is added to the voltage value of the first power supply by lowering the voltage value when generating the second voltage value than when generating the first voltage value. A driving method of a plasma display device, characterized in that:
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