JP4947027B2 - Microcomputer - Google Patents

Description

  The present invention relates to a microcomputer in which a CPU can execute a periodic task and an aperiodic task in a time-sharing manner in parallel and has an ICE interface unit.

The applicant causes one CPU to alternately switch and execute two tasks in synchronization with the control clock, and allows one task to always perform processing at a constant cycle without accepting interrupt processing. A microcomputer configured to accept and process interrupt processing has been proposed (see, for example, Patent Document 1).
Then, as a development of the task processing form of the microcomputer, the execution of the instruction to be executed by the periodic task within that period is completed based on the execution of the periodic task that always performs processing at a constant period. A microcomputer configured to execute a periodic task has also been proposed (see Patent Document 2).
JP-A-6-250857 JP 2008-77294 A

  Here, regarding the microcomputer disclosed in Patent Document 2, assuming that development work is performed using ICE, there are the following problems. FIG. 5 is a timing chart showing the operation of the CPU when a break instruction is issued during the execution of the A task, which is an aperiodic task. The task timer in (a) is a timer for the CPU to measure the execution cycle of the periodic task, and the address in (b) indicates the execution addresses A0, A2, A4,.

  Here, during a break process (not shown), when the user sets a breakpoint at address A4 on the ICE, the data in the emulation memory on the microcomputer is rewritten to the specific data “FA00” corresponding to the break instruction by the ICE interface unit. It has been. Therefore, the CPU recognizes the issuance of the break instruction by fetching the data “FA00” at the time of fetching the data of the address A4 (NMI: treated as an unmaskable interrupt), and the task timer of (a) The timer stops at the timer value “C”.

  Then, in order to inhibit the acceptance of further breaks, (e) the break mask is activated (high), and (f) the break signal is activated. In addition, the address A6 of the A task where the processing is interrupted is stored as a return destination address in the break register of (h), and (i) a flag indicating that a break has occurred by issuing a break instruction is set. Then, the CPU branches to a vector for processing a break instruction after address A8, and executes a break time process (break processing routine).

  FIG. 6 is a flowchart showing only a processing part performed before returning from the break time processing to the A task. Since the break instruction is issued at the address A4 of the A task, it is necessary to start the processing of the A task from the address A4 when returning. Therefore, "1" is added to the timer value of the task timer that has stopped timing (step S11), and the return destination address (return address) is set by subtracting "2" from the break register (step S12). Then, at the time of return, the processing is resumed from the timer value “D” and the address A4.

  FIG. 7 is a timing chart when the task is switched from the A task that is an aperiodic task to the L task that is a periodic task. The task switching start register is set to “4”. When the value of the task timer reaches “4”, the task switching period signal in (d) becomes active and the break (NMI) mask in (e). The signal is activated and break acceptance during the task switching period is prohibited. During this period, the L task processing address L0 stored in the task switching address register is stored in the program counter as the L task return destination address, and the A task processing address A6 is the next A task return destination address. Is stored in the task switching address register (g). Thereafter, at the same time as the task timer value becomes “0”, the task timer stops the time counting operation, and the execution of the L task starts.

  FIG. 8 is a timing chart when reception of a break instruction in FIG. 6 and task switching from an aperiodic task to a periodic task in FIG. 7 occur simultaneously. Since the acceptance of a break is prohibited during the switching period from the A task to the L task, if a break instruction is issued immediately before the task switching period, the break instruction is accepted after the task switching is completed. Then, for example, even if the A task is originally targeted for a break, the execution target of the CPU is switched to the L task, so that there is a problem that the return address is wrong when returning from the break instruction.

  In the case of FIG. 5, when the break instruction is issued, the processing address A6 of the A task is stored in the break register, and after that, it is “−2” and the return address becomes A4. In the case of FIG. When the execution target address becomes L0, the break instruction is accepted and processed, so the address L0 is stored in the break register (see (h)) and the return address becomes (L0-2). .

  The present invention has been made in view of the above circumstances, and a purpose of the present invention is to make it possible to appropriately process reception of a break instruction issued by the ICE even when the CPU executes a periodic task and an aperiodic task in parallel. To provide a computer.

  According to the microcomputer of claim 1, when switching between execution of the periodic task and the non-periodic task, the task switching register for storing the return destination address and the break instruction are issued to the CPU. And a break register for storing a return destination address. When the coincidence detection means detects that the switching of the periodic task and aperiodic task by the CPU and the reception of the break instruction occur at the same time, the address exchange means detects the address and break stored in the task switching register. Replace the address stored in the register.

  With this configuration, even if the task that was the execution target of the break instruction is switched to a different task by task switching, the address stored in the task switching register is stored in the break register. Accordingly, it is possible to set so that the return address after the processing corresponding to the break instruction is the address on the task side that was being executed when the break instruction was issued.

  According to the microcomputer of the second aspect, since the address changing means is realized in the break processing routine when the CPU executes the break instruction, the address input means can be changed by slightly modifying the break processing routine program. Can be replaced.

  According to the microcomputer of the third aspect, since the address exchange means is realized by a logic circuit built in the CPU, the address exchange can be executed without changing the software.

  According to the microcomputer of claim 4, the task timer performs a time measuring operation during a period in which the CPU executes the non-periodic task, and the task switching start register indicates a task indicating a timing at which the CPU starts task switching. A predetermined value of the timer value is stored. Therefore, the CPU can maintain the periodicity of the periodic task by starting the task switching when the value of the task timer matches the predetermined value set in the task switching start register. In the periodic task, the task timer value is stopped at “0”, and the timing operation is not performed.

According to the microcomputer of claim 5, when the simultaneous occurrence of task switching and break instruction issuance is detected by the coincidence detecting means, the task timer correcting means before the CPU returns from the break instruction processing routine. The predetermined value stored in the task switching start register is corrected and written back to the task timer.
In other words, if the acceptance of a break instruction and the switching of a task from an aperiodic task to a periodic task occur simultaneously, the CPU accepts a break after task switching, so the task timer value becomes “0” in the break processing routine. . Therefore, if the predetermined value stored in the task switching start register is corrected and written back to the task timer before the CPU returns from the break processing routine to the non-periodic task, the periodicity of the periodic task can be maintained.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. The microcomputer of this embodiment performs a desired process by executing a periodic task and a non-circular task. Specifically, the execution of the periodic task is periodically performed, and the aperiodic task is executed between a certain periodic task and the next periodic task. Periodic tasks are processes that require accurate time management, such as timer counting and communication processing. Non-periodic tasks are applications that execute applications that do not require periodic execution (interrupt processing, for example). is there.

  FIG. 1 is a functional block diagram showing an internal configuration of a microcomputer 1 with respect to a part according to the gist of the present invention. The control that the microcomputer 1 of the present invention executes in a time-division parallel manner while switching between the periodic task and the non-periodic task is basically the same as the microcomputer disclosed in Patent Document 2. The microcomputer 1 includes a CPU 2 and an ICE interface unit 3, and the CPU 2 includes a calculation unit 4 and a task switching / break control unit 5. The calculation unit 4 corresponds to the execution unit 322 of Patent Document 2, and the task switching / break control unit 5 corresponds to the functions of the control unit 310 and the data path 320.

  The task switching / break control unit 5 includes a task timer 6, a task switching register 7, a task switching start register 8, a task switching control unit 9 (task switching control in the figure) for controlling task switching based on these, and an ICE interface. A break control unit 10 (same break control) that performs break control in response to a break request from the unit 3, a break register 11, an overall control unit 12 (same control unit), and a coincidence detection unit (simultaneous occurrence detection unit) 13 are provided. ing. The task timer 6 is a timer that performs a timing operation during the period when the CPU 2 is executing the non-periodic task, and the timer value is output to the task switching control unit 9. In the task switching register 7, as described above, when task switching is executed, an address for returning to the processing of the task being executed is stored by the control unit 12.

  The task switching start register 8 stores data indicating the start timing for the CPU 2 to switch the execution target from the non-periodic task to the periodic task, and the data is output to the task switching control unit 9. The break control unit (simultaneous occurrence detection means) 10 performs processing related to break control with the overall control unit 12 when a break request occurs, and the break register 11 has a return address when returning from break processing. Stored by the overall control unit 12.

  The task switching control unit (simultaneous occurrence detecting means) 9 outputs a task switching signal to the simultaneous occurrence detecting unit 13 when the execution target task is switched from the non-periodic task to the periodic task. When an instruction is issued, a break instruction generation flag is set for the simultaneous occurrence detection unit 13. The coincidence detection unit 13 outputs a coincidence detection signal to the ICE interface unit 3 when task switching occurs and the break instruction generation flag is set at the same time.

  The ICE interface unit 3 performs communication processing with the ICE 14 used when performing development work using the microcomputer 1, and is connected to the CPU 2 via an address bus 15 and a data bus 16 inside the microcomputer 1. The ICE interface unit 3 stores a monitor program 17 executed by the CPU 2. In the monitor program 17, an address switching process (address exchange means) 18 and a break register correction process (task timer correction means) are stored. 19 is executed. When the coincidence detection unit 13 outputs a coincidence detection signal, a task switching break simultaneous occurrence flag 20 is set in the ICE interface unit 3.

  Further, when the user sets a breakpoint in the ICE 14, the ICE interface unit 3 converts the data at the address corresponding to the breakpoint on the emulation memory (not shown) connected to the buses 15 and 16 into the specific data that is a break instruction. Rewrite to “FA00”. When the user operates the break issue switch of the ICE 14, a break request signal is directly output to the break control unit 10.

  Next, the operation of this embodiment will be described with reference to FIGS. FIG. 2 is a diagram corresponding to FIG. 8, and is a timing chart showing processing when task switching and issue of a break instruction occur simultaneously in the microcomputer 1 of the present invention. When the user sets a breakpoint at the address A4 in the ICE 21, the ICE interface unit 3 rewrites the data of the target address on the emulation memory to the specific data “FA00”.

  Thereafter, when the execution of the user program is started, if the CPU 2 is executing an aperiodic task (A task), the CPU 2 fetches the specific data (break instruction) at the address A4 immediately before the task switching timing. (FIG. 2 (c)), in the next cycle, the task switching start register setting value matches the task timer value, so that task switching processing is started, and the task switching control unit 5 sets the signal indicating the task switching interval to the high level. (FIG. 2D).

  At the same time, the break control unit 10 activates a break mask signal to prohibit acceptance of breaks during task switching (FIG. 2 (e)). Therefore, the break control unit 10 sets a break instruction generation flag (FIG. 2 (i)), but the break instruction processing is in a pending state. Accordingly, the coincidence detection unit 13 outputs a coincidence detection signal to the ICE interface unit 3, and the task occurrence break occurrence flag 20 is set (FIG. 2 (j)).

  In this case, as described above with reference to FIG. 7, the aperiodic task address A6 is stored in the task switching register 7 as the return destination at the next task switching (FIG. 2 (g)). The execution target of the CPU 2 is switched from the non-periodic task to the periodic task (L task), and the execution address is switched to the start address L0 of the periodic task stored in the task switching register 7 at the previous task switching. (FIG. 2 (b)).

  After the address is switched, a break instruction is accepted at the address L0, the address L0 is stored in the break register 11 (FIG. 2 (h)), and the break mask signal is output again (FIG. 2 (e)). . Then, after the address L2, a vector corresponding to the break instruction is issued, and processing by the monitor program 17 (break instruction processing routine) is started.

FIG. 3 is a flowchart showing the pre-return process when the CPU 2 returns from the process of the monitor program 17. First, it is confirmed whether or not the break factor is caused by a break instruction (step S1). If the break instruction is caused by a break instruction (YES), a break occurrence flag 20 during task switching is set to determine whether or not a break has occurred during task switching. Judgment is made based on whether or not (step S2).
Here, if the flag 20 is not set (NO), the timer value of the task timer 6 is not “0”, and if a break occurs during the timer operation (step S5: YES), it continues. In steps S6 and S7, processing similar to that in steps S11 and S12 is performed. If the timer value is “0” (step S5: NO), only step S7 is executed.

  On the other hand, if the flag 20 is set in step S2 (YES), processing for setting the return destination from the monitor program 17 to the address where the break instruction is generated is performed in step S3. First, (1) the contents of the task switching register 7 and the contents of the break register 11 are exchanged by the address switching process 18 (see FIGS. 2 (g) and (h)), and the address L0 is set in the task switching register 7. The address A6 is stored in the register 11.

Next, (2) “2” is subtracted from the address value stored in the break register 11 by the break register correction process 19 (see FIG. 2 (i)) as in step S7, and the address value is set to A4. Then, (3) a value obtained by adding “1” to the value of the task switching start register is set in the task timer 6. In this case, since the value of the task switching start register 8 is “4”, “5” including “1” is set in the task timer 6 (see FIG. 2A).
When the process of step S3 is completed, the task switching break occurrence flag 20 is cleared (see FIG. 2J), and the process returns to the normal process. In this case, as shown in FIG. 2B, the execution target address is A4 of the non-periodic task, and switching to the periodic task (address L0) is executed again.

  As described above, according to the present embodiment, when the CPU 2 issues a break instruction by the task switching register 7 in which the return destination address is stored when switching between the execution of the periodic task and the non-periodic task, and the ICE 14. And a break register 11 in which a return destination address is stored. When the coincidence detection unit 13 detects that the switching of the periodic task and the non-periodic task by the CPU 2 and the issue of the break instruction occur simultaneously, the address switching process 18 of the monitor program 17 is stored in the task switching register 7. And the address stored in the break register 11 are interchanged.

Therefore, it is possible to set the return address after performing the processing corresponding to the break instruction to be the address on the task side being executed when the break instruction is issued. Since the address switching process 18 is executed in the monitor program 17 when the CPU 2 executes the break instruction, the address change can be executed with only a slight modification of the monitor program 17.
The task timer 6 performs a time measuring operation while the CPU 2 is executing the non-periodic task, and the task switching start register 8 stores a predetermined value of the task timer value indicating the timing at which the CPU 2 performs task switching. Therefore, the periodicity of the periodic task can be maintained.

  The break register correction process 19 is stored in the task switching start register 8 before the CPU 2 returns from the monitor program 17 when the simultaneous detection of the task switching and the break instruction issuance is detected by the simultaneous detection unit 13. The predetermined value is corrected and written back to the task timer 6. That is, the timer value of the task timer 6 advances by an amount corresponding to the time required for the address switching process 18 by the address switching process 18 and is stored in the task switching start register 8 before returning from the monitor program 17. If the predetermined value is corrected and written back to the task timer 6, the periodicity of the periodic task can be maintained.

(Second embodiment)
FIG. 4 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described. The microcomputer 21 of the second embodiment includes an address switching section (address exchange means) 23 that implements a function corresponding to the address switching processing 18 of the first embodiment with a hardware logic circuit inside the CPU 22. The address switching unit 23 has a built-in data buffer, receives the coincidence detection signal from the coincidence detection unit 13 and directly accesses the task switching register 7 and the break register 11, and stores the address values stored in both of them. Execute the process of replacing.

The monitor program 25 of the ICE interface unit 24 executes only the break register correction process 19.
According to the second embodiment configured as described above, the address switching unit 23 is realized by the logic circuit built in the CPU 22, so that the address replacement can be executed without changing the software.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
In the second embodiment, the function corresponding to the break register correction process 19 may also be realized by a logic circuit built in the CPU 22.
In the first and second embodiments, when the user sets a breakpoint in the ICE 14, the address comparator does not rewrite the address data corresponding to the breakpoint on the emulation memory with the specific data “FA00”. It may be realized by comparing the fetch address of the CPU 22 with the address corresponding to the breakpoint and replacing the content of the data bus with the specific data “FA00” when a match between the two is detected.
The specific data may be other than “FA00”.

1 is a functional block diagram showing the configuration of a microcomputer according to a first embodiment of the present invention. Timing chart showing processing when task switching and break instruction issuance occur simultaneously Flow chart showing pre-return processing when returning from the monitor program FIG. 1 equivalent view showing a second embodiment of the present invention. Timing chart when a break instruction is issued showing conventional technology 3 equivalent figure Timing chart for task switching 2 equivalent diagram

Explanation of symbols

  In the drawings, 1 is a microcomputer, 2 is a CPU, 3 is an ICE interface unit, 6 is a task timer, 7 is a task switching register, 8 is a task switching start register, 9 is a task switching control unit (simultaneous occurrence detection means), 10 Is a break control section (simultaneous occurrence detection means), 13 is a coincidence detection section (simultaneous occurrence detection means), 14 is ICE, 18 is an address switching process (address replacement means), 19 is a break register correction process (task timer correction) Means), 21 is a microcomputer, 22 is a CPU, 23 is an address switching section (address exchange means), and 24 is an ICE interface section.

Claims (5)

CPU is time division parallel feasible the periodic tasks and aperiodic tasks, Ri program period of the periodic tasks by switching the execution target periodically task from aperiodic tasks for every predetermined number of cycles Do constant, wherein during the switching prohibits acceptance of the break instruction, together configured so that accepts break instruction after completion of the switching, a microcomputer equipped with ICE interface unit which communicates with the ICE (in Circuit Emulator) There,
When the CPU switches between execution of the periodic task and the non-periodic task, when the CPU receives a break switching instruction from the ICE and a task switching register that stores a return destination address, the return destination address is A break register to be stored,
Simultaneous detection means for detecting that switching from the non-periodic task to the periodic task by the CPU and acceptance of a break instruction have occurred simultaneously;
When the simultaneous occurrence is detected by the simultaneous occurrence detection means, an address exchange means for exchanging the address stored in the task switching register and the address stored in the break register is provided. Microcomputer.   2. The microcomputer according to claim 1, wherein the address exchange means is realized in a break processing routine when the CPU executes the break instruction.   2. The microcomputer according to claim 1, wherein the address exchange unit is realized by a logic circuit built in the CPU. A task timer that performs a timekeeping operation during a period in which the CPU executes the non-periodic task;
4. A task switching start register in which a predetermined value measured by the task timer is stored as a timing at which the CPU switches between the periodic task and the non-periodic task. A microcomputer according to any one of the above.   When the coincidence detection unit detects the coincidence, the CPU corrects a predetermined value stored in the task switching start register before returning from the break instruction processing routine to the task timer. 5. The microcomputer according to claim 4, further comprising task timer correction means for writing back.

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