CN110297688B - Hardware counting device and method and processor - Google Patents
Hardware counting device and method and processor Download PDFInfo
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- CN110297688B CN110297688B CN201810241195.7A CN201810241195A CN110297688B CN 110297688 B CN110297688 B CN 110297688B CN 201810241195 A CN201810241195 A CN 201810241195A CN 110297688 B CN110297688 B CN 110297688B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/4555—Para-virtualisation, i.e. guest operating system has to be modified
Abstract
The embodiment of the invention provides a hardware computing device, a hardware computing method and a hardware computing processor, and relates to the technical field of computers. The hardware counting device comprises: adder, counting register, selector, comparator and comparison register. One end of the adder is connected with the output end of the counting register, and the other end of the adder is connected with the input end of the counting register through the selector and used for counting the value of the counting register. The selector is used for receiving a counting register signal output by the processor core and outputting a signal to the counting register according to the counting register signal so as to control the value of the counting register. The comparator is respectively connected with the counting register and the comparison register and is used for outputting clock interrupt when the value of the counting register is equal to the value of the comparison register. The embodiment of the invention can improve the precision of the clock system and reduce the expenditure.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a hardware computing apparatus, a hardware computing method, and a processor.
Background
With the rapid development of virtualization technology of modern microprocessors, the modern microprocessors usually add support of a hardware-assisted virtual clock system to generate a clock interrupt to notify an operating system through the hardware-assisted virtual clock system.
At present, three registers, namely, a virtual clock offset register (root.gtoffset), a virtual machine count register (guest.counter) and a virtual machine comparison register (guest.compare), are usually added to a Host counter register (root.counter) and a Host comparison register (root.compare) used by an original Host (Host) to implement a hardware-assisted virtual clock system in a modern microprocessor. Wherein the read-only value of guest.counter is the sum of the value of root.counter and the value of root.gtoffset, i.e. guest.counter is root.counter + root.gtoffset. Gtoffset is writable, and the value written to it may characterize the offset value of guest. When the value of guest.counter equals the value of guest.compare, a processor core in a modern microprocessor generates a clock interrupt that is handled directly by the virtual machine operating system. The virtual machine operating system may operate as a Guest (Guest) operating system in modern microprocessors. Thus, the clock interrupts directly handled by the virtual machine operating system are also known as Guest clock interrupts. When the virtual machine is switched in and out, the host needs to ensure that the virtual machine operating system sees a continuously monotonically increasing guest.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present invention provide a hardware counting apparatus and a corresponding hardware counting method, which solve the problem that overhead is increased due to the need to frequently calculate a root.
In order to solve the above problem, an embodiment of the present invention discloses a hardware counting apparatus, including: adder, counting register, selector, comparator and comparison register. One end of the adder is connected with the output end of the counting register, and the other end of the adder is connected with the input end of the counting register through the selector and used for counting the value of the counting register. The selector is used for receiving a counting register signal output by the processor core and outputting a signal to the counting register according to the counting register signal so as to control the value of the counting register. The comparator is respectively connected with the counting register and the comparison register and is used for outputting clock interrupt when the value of the counting register is equal to the value of the comparison register.
Optionally, the selector is configured to output a signal to the count register according to a count register signal output by the processor core, so as to control the value of the register, and includes: the selector transmits the output signal of the adder to the counting register to increase the value of the counting register when receiving the enabling signal output by the processor core; and the selector transmits a non-enable signal to the counting register when receiving the non-enable signal output by the processor core so as to suspend counting of the counting register.
Optionally, the selector is further configured to receive a write signal output by the processor core, and transmit the write signal to the count register, so as to store a corresponding write value into the count register.
Optionally, the selector comprises a first selector and a second selector. The first selector is connected with the adder and used for receiving an enable signal or a non-enable signal output by the processor core and forwarding an output signal of the adder to the second selector according to the enable signal. The second selector is connected with the counting register and is used for transmitting the writing signal to the counting register when receiving the writing signal so as to store the writing value into the counting register; or the output signal of the adder is transmitted to the counting register so as to trigger the counting register to increase the value of the counting register according to the output signal.
Optionally, the priority of the write signal is higher than the priority of the output signal of the adder.
The embodiment of the invention also discloses a hardware counting method, which is applied to the hardware computing device and comprises the following steps:
the selector receives a counting register signal output by the processor core;
controlling the value of the counting register according to the counting register signal;
and the comparator outputs clock interrupt when the value of the counting register is equal to the value of the preset comparison register.
Optionally, the controlling the value of the count register according to the count register signal includes:
when the selector receives an enabling signal, triggering an adder to count the value of the counting register, and transmitting an output signal of the adder to the counting register through the selector so as to trigger the counting register to increase the value of the counting register according to the output signal of the adder;
transmitting a disable signal to the count register to suspend counting by the count register when the selector receives the disable signal.
Optionally, the method further comprises: the selector receives a write-in signal output by the processor core; and transmitting the writing signal to the counting register so as to write the corresponding writing numerical value into the counting register.
Optionally, before the transmitting the output signal of the adder to the count register through the selector, the method further includes: detecting whether the selector receives a write signal output by the processor core; if the selector does not receive the write-in signal, the step of transmitting the output signal of the adder to a counting register through the selector is executed; and if the selector receives a write signal, executing the step of transmitting the write signal to the counting register.
Optionally, the method further comprises: the comparator reads the value of the counting register; judging whether the read value is equal to the value of a preset comparison register or not; and if the read value is equal to the value of the preset comparison register, determining that the value of the counting register is equal to the value of the preset comparison register.
The embodiment of the invention also discloses a processor, which comprises: the hardware computing device comprises a processor core, a virtual machine clock subsystem and a clock subsystem of a host machine, wherein the hardware computing device is used as the virtual machine clock subsystem.
The embodiment of the invention has the following advantages:
the hardware counting device provided by the embodiment of the invention is irrelevant to a host machine clock subsystem, solves the problem that the virtual clock system is realized by depending on the host machine clock subsystem in the prior art, overcomes the defects that the GToffset value needs to be frequently calculated in the conventional hardware auxiliary clock virtualization subsystem and the host machine frequently switches the virtual machine clock subsystem, reduces the expenditure and improves the precision of the clock system.
Drawings
FIG. 1 is a schematic structural diagram of a hardware counter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a hardware counter according to an exemplary embodiment of the present invention;
FIG. 3 is a block diagram of a processor according to an example of the invention;
FIG. 4 is a flowchart illustrating steps of a hardware counting method according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Modern microprocessors typically provide a physical Counter and comparator for the operating system's timing and scheduling subsystem, whose hardware architecture may include two registers of the same number of bits, a count register (Counter) and a Compare register (Compare), respectively. Wherein the Counter is typically a monotonically increasing Counter. The Counter value may change constantly as the processor clock rolls over. The operating system may write a number into the compare register that is greater than the value currently in the count register so that the processor core may generate a clock interrupt when the value of the count register is equal to the value written into the compare register, thereby implementing various timers for the operating system.
With the rapid development of the virtualization technology of modern microprocessors, a counter which is similar to the characteristic of a hardware counter of a physical processor and is incremented along a clock cycle can be seen by a virtual machine operating system through a software method. For example, in the case of a clock system using a software-emulated virtual machine, i.e., in the case of a pure software-emulated virtual machine Counter and a software-injected clock interrupt, each reading from the Counter or reading from or writing to the Compare by the virtual machine operating system may cause an exception, which may cause hardware (i.e., a processor core) to be transferred to the host operating system for execution. The host machine can return the values of Counter and Compare to the virtual machine operating system in a software simulation mode, and judge whether to inject the virtual machine clock interrupt into the virtual machine every time in the clock interrupt of the host machine. The frequency of clock interruption and timing time in the operation of the operating system is high, so that the virtual machine and the host machine are frequently switched, namely the states of the virtual machine and the host machine need to be frequently switched. In addition, the software Counter, the compass and the interrupt simulation bring a lot of overhead, which reduces the efficiency of the virtual machine, and the clock system using the software simulation is prone to processor clock skew, which affects the accuracy of the clock system.
It should be noted that the value of the count register in the clock system may increase with the input of the processor clock, i.e., the value of the Counter changes with the change of the clock Cycle (CPU Cycle) of the processor.
In the prior art, a hardware-assisted virtualized clock subsystem is realized on the basis of a clock subsystem of a host machine. The virtualized sub-clock system is also called virtual machine clock subsystem, including guest. The value of root.gtoffset needs to be calculated frequently when the virtual machine switches, and the host needs to switch the virtual machine clock subsystem on and off frequently.
One of the core concepts of the embodiments of the present invention is to provide a new hardware counting apparatus to overcome the disadvantages that the hardware-assisted virtual clock system implemented in the prior art needs to frequently calculate the value of root.
Referring to fig. 1, a schematic structural diagram of a hardware counting apparatus according to an embodiment of the present invention is shown.
In the embodiment of the present invention, the hardware counting device may include an adder 110, a counting register 120, a selector 130, a comparator 140, and a comparison register 150. One end of the adder 110 may be connected to the output end of the count register 120, and the other end may be connected to the input end of the count register 120 through the selector 130, for counting the value of the count register. The selector 130 may be configured to receive a count register signal output by a processor core and output a signal to the count register 120 according to the count register signal, so as to control the value of the count register 120.
Specifically, the selector 130 may output a signal to the count register signal 120 according to the received count register signal, so as to control the operation mode of the count register 120 through the output signal, and further, may implement control of the value of the count register based on the control of the operation mode. The operation mode of the count register 120 may include a count mode and a non-count mode. For example, the selector 130, upon receiving a non-count enable signal output by the processor core, may output a signal to the count register 120 based on the non-count enable signal to cause the count register 120 to enter a non-count mode, thereby causing the count register 120 to suspend counting; for another example, the selector 130 may transmit the count enable signal to the count register 120 upon receiving the count enable signal, thereby triggering the count register 120 to enter the count mode. When the count register 120 is in the compute mode, the adder 110 may increase the value of the count register 120 with the input of the processor clock, so that the value of the count register 120 can be continuously accumulated with the input of the processor clock, i.e., the value of the count register 120 is increased with the input of the processor clock.
The comparator 140 is respectively connected to the count register 120 and the compare register 150, and is configured to output a clock interrupt when the value of the count register 120 is equal to the value of the compare register 150. Specifically, the comparator 140 may acquire the value of the count register 120 and the value of the compare register 150, and then may compare the value of the count register 120 with the value of the compare register 150 to determine whether the currently acquired value of the count register 120 is equal to the value of the compare register 150. When the value of the count register 120 is equal to the value of the compare register 150, the comparator 140 may generate a clock interrupt and output the clock interrupt.
The hardware counting device provided by the embodiment of the invention can be applied to a processor and can be used as a virtual clock subsystem of the processor, so that the problem of the precision of the clock system caused by adopting a software simulation virtual machine clock system in the prior art can be solved.
In addition, the hardware counting device provided by the embodiment of the invention is irrelevant to root.counter and root.Complex, namely irrelevant to a host clock subsystem, solves the problem that a virtual clock system is realized by depending on the host clock subsystem in the prior art, overcomes the defects that the conventional hardware auxiliary clock virtualization subsystem needs to frequently calculate the value of GToffset and the host frequently switches the virtual clock subsystem, reduces the overhead and improves the precision of the clock system.
In this embodiment of the present invention, optionally, the count register signal received by the selector 130 may be an enable signal of the count register, so that the count register may be triggered to enter the count mode according to the enable signal; or a non-enable signal of the counting register, so that the counting register can be triggered to exit the counting mode according to the non-enable signal to suspend counting of the counting register. The selector 130 may be configured to output a signal to the count register 120 according to a count register signal output by the processor core, so as to control a value of the count register 120, and specifically may include: the selector 130 transmits the output signal of the adder 110 to the count register 120 to increase the value of the count register 120 when receiving the enable signal output by the processor core; the selector 130 transmits a disable signal to the count register 120 to suspend counting by the count register 120 when receiving the disable signal output from the processor core.
In a specific implementation, the hardware computing apparatus according to the embodiment of the present invention may add a count register signal to an input terminal of the selector 130, and the input terminal of the selector 130 may be connected to an output terminal of a status signal of a microprocessor (i.e. a processor) through a related hardware configuration, so that a signal output from the output terminal may be determined as the count register signal, so that an operation mode of the computing register may be subsequently controlled based on the count register signal, that is, counting may be suspended or continued in combination with a specific change in a state of the processor. The count register signal may be an enable signal (i.e., a count enable signal) of the count register, or may be a non-enable signal (i.e., a non-count enable signal) of the count register. Specifically, when the processor core operates in the virtual machine mode, the count register signal received by the selector 130 may be a count enable signal, and the count mode of the count register 120 may be automatically turned on, so that the adder continuously accumulates the value of the count register along with the change of the processor clock cycle, and outputs the signal to the selector. The selector 130 may transmit the output signal of the adder to the count register 120 based on the count enable signal to increase the value of the count register, so that the value of the count register 120 is continuously accumulated with the input of the processor clock, thereby realizing the counting of the count register. When the processor core operates in the host mode, the count register signal received by the selector 130 may be a non-count enable signal, and the selector 130 may automatically turn off the count mode of the count register 120 based on the non-count enable signal, i.e., suspend the counting of the count register 120, so that the value of the count register 120 remains unchanged and does not increase with the input of the processor clock.
In an optional embodiment of the present invention, the selector 130 is further configured to receive a write signal output by the processor core, and transmit the write signal to the count register 120, so as to store a corresponding write value into the count register 120, so that the count register in the hardware counting apparatus is writable, thereby saving and restoring the value of the Counter of the virtual machine each time the virtual machine is switched out and switched in, and further ensuring that the Counter of each virtual machine operating system is monotonically and continuously incremented in view of the virtual machine operating system.
In the embodiment of the present invention, the selector 120 may optionally include a first selector and a second selector. The first selector is connected with the adder and used for receiving an enable signal or a non-enable signal output by the processor core and forwarding an output signal of the adder to the second selector according to the enable signal. The second selector is connected with the counting register and is used for transmitting the writing signal to the counting register when receiving the writing signal so as to store the writing value into the counting register; or the output signal of the adder is transmitted to the counting register so as to trigger the counting register to increase the value of the counting register according to the output signal.
In a particular implementation, the first selector and the second selector may both be one-of-two selectors. For example, as shown in fig. 2, the first selector 131 may be connected to the adder 110, receive an output signal of the adder, and may receive a count register signal counter enable. The second selector 132 may be connected to the output terminal of the first selector 131, and may receive the signal output by the first selector 131, such as the output signal of the adder forwarded by the first selector 131, and may receive the write signal direct write output by the processor core. Wherein the priority of the write signal may be higher than the priority of the output signal of the adder.
In order that those skilled in the art will better understand the embodiments of the present invention, the following description is given by way of example:
as an example of the present invention, as shown in fig. 3, the hardware computing apparatus provided by the embodiment of the present invention may be applied in a processor as a virtual clock subsystem 310 of the processor. In particular, virtual clock subsystem 310 may include Guest.Counter and Guest.Compare, and the value of Guest.Counter may be continually self-adding as the clock cycles of the processor progress. Among them, the count register 120 in the hardware computing device can be regarded as guest.counter in the virtual clock subsystem 310, and the compare register 120 in the hardware computing device can be regarded as guest.compare in the virtual clock subsystem 310. The virtual clock subsystem 310 may generate a Guest clock interrupt (interrupt) when the value of Guest.
This example may also add a count register signal counter enable to the virtual clock subsystem 310, and this count register signal counter enable may be directly connected to the status signal that the processor core is in mode by the relevant hardware configuration, so that the virtual clock subsystem 310 may pause or continue counting in conjunction with a change in the operating mode of a particular processor core. The counter enable signal may automatically turn off guest counter when a processor core in the processor is operating in a host mode and may automatically turn on guest counter when the processor core is operating in a virtual machine. In a specific implementation, the host may further generate an instruction to control the switch of guest.counter, that is, when the processor core runs in the host mode, the host may modify the value of the count register signal counter enable according to a specific processor instruction, so that the virtual clock subsystem 310 may suspend or continue counting of guest.counter based on the value of the count register signal counter enable. Of course, whether the counter is suspended or continued to count as certain processor states change may also be adjusted by the configuration of the software, which is not limited in this example.
Additionally, the value of guest. counter can be modified by a specific processor instruction. After modification, if the guest counter is in count mode, virtual clock subsystem 310 may then increment the modified guest counter value. It can be seen that guest.counter of virtual clock subsystem 310 is writable and that guest.counter write operations can be performed by the host in host mode, so that the value of virtual machine Counter can be saved and restored each time the virtual machine switches out a switch-in, ensuring that the Counter of each virtual machine operating system appears to the virtual machine operating system to be monotonically continuously incremented, i.e., no jump occurs during the incrementing process.
It should be noted that, when the virtual machine is running and exiting, the guest.counter needs to be turned off, and when the virtual machine is resumed, the guest.counter needs to be turned on again, so that the virtual machine operating system can acquire a logically continuous clock.
In an alternative embodiment, the count Register signal counter enable is added to the virtual clock subsystem 310 to be connectable to a Bit of a configuration Register (configuration Register) of the processor, so that the virtual machine count Register can be turned off and closed by the Bit of the configuration Register. For example, the virtual machine counting register may be turned on by writing 1 into a bit of the configuration register so that the value of the counting register signal counter enabled is 1; for another example, a value of 0 may be written into a bit of the configuration register, so that the count register signal counter enabled is set to 0, thereby implementing the virtual machine count register shutdown. As can be seen, the value of the count register signal count enabled may be 0 or 1.
The write signal direct write added at the virtual clock subsystem 310 may be coupled to a General Register (General Register) output port from the processor core, which may write a value to a virtual machine count Register in the virtual clock subsystem 310 via a standard Store write operation.
Specifically, when the value of the count register signal counter enable is 1, the count register 120 in the virtual clock subsystem 310 is in the count mode, and the output signal of the adder 110 may be transmitted to the second selector 131 through the first selector 131. When the second selector 132 does not receive the write signal direct write, the signal output by the first selector, such as the output signal of the adder forwarded by the first selector, may be transmitted to the count register 120 through the second selector 132 to increase the value of the count register according to the output signal of the adder, so that the value of the count register is continuously accumulated by the input of the processor clock. When the second selector 132 receives the write signal direct write, the signal output by the first selector cannot be transmitted to the count register 120 through the second selector 132, and the write signal direct write can be transmitted to the count register 120 through the second selector, so as to introduce the write value corresponding to the write signal direct write into the count register 120. It can be seen that, when the hardware computing device according to the embodiment of the present invention receives the write signal, the hardware computing device can preferentially store the write value corresponding to the write signal into the count register 120. When the value of the counter enable signal is 0, the output signal of the adder may not be transmitted to the second selector through the first selector 131, i.e., the counting mode of the counter register 120 may be automatically turned off, and the counting of the counter register 120 may be suspended, so that the value of the guest counter register 120 may be maintained.
An embodiment of the present invention further provides a processor, which may include: the hardware computing device comprises a processing core, a virtual machine clock subsystem and a host machine clock subsystem, and can be used as the virtual machine subsystem. Thus, when the processing core is operating in virtual machine mode, the virtual machine clock subsystem may count with Guest.counter and may generate a clock interrupt with Guest.Compare based on the count register signal output by the processor core. When the host mode needs to be switched, the processor core can close the virtual machine clock subsystem by changing the value of the counting register signal, so that the host mode is switched, and the clock subsystem of the host can be used for counting and generating clock interrupt.
For example, the processor in the above example may also be provided with a clock subsystem 320 of the host and an interrupt handling control module 330. The host clock subsystem 320 may include: a host adder 321, a host count register 322, a host compare register 323, and a host comparator 324. The adder 321 of the host may output signals along with the input and output signals of the processor clock, so that the value of the count register 322 of the host may be continuously accumulated according to the output signal of the adder 321. The host's comparator 324 may take the value of the count register 322 and the value of the compare register 323 and output a clock interrupt when the value of the count register 322 equals the value of the compare register 323.
It should be noted that the clock interrupt generated by the clock subsystem 320 of the host and the clock interrupt generated by the clock subsystem 310 of the virtual machine can both be transmitted to the interrupt processing control module of the processor. Each time a clock interrupt is generated, an interrupt status flag of the processor can be set based on the clock interrupt, and the processor jumps to a processing entry address of the clock interrupt for processing.
To sum up, the present example implements the coherency of the virtual machine clock hardware subsystem by a writable guest.counter; the opening and closing of the guest.counter are automated through linkage with the hardware state of the microprocessor, and frequent software intervention is not needed, so that the switching and recovery operations of the virtual machine clock subsystem are simplified. Specifically, guest.counter in the virtual machine clock subsystem can be written in, and the switch of guest.counter can be controlled through the counter enable signal, so that the defects that GTOffset needs to be frequently calculated and the virtual machine clock needs to be frequently switched in the existing hardware auxiliary clock virtualization subsystem are overcome, and the analog overhead of the host machine on the virtual machine clock counter and the clock interrupt is reduced.
In addition, the virtual clock subsystem can be automatically turned off by the non-enable signal of the counting register output by the processing core, so that meaningless Guest clock interrupt generated when Guest is switched out can be avoided, the overhead is further reduced, and the efficiency is improved.
Referring to FIG. 4, a flow chart of steps of a hardware computation method embodiment of the present invention is shown. The hardware computing method can be applied to the hardware computing device provided by the invention, and specifically comprises the following steps:
in step 401, the selector receives a count register signal output by the processor core.
In an optional embodiment of the present invention, the controlling the value of the count register according to the count register signal may include: when the selector receives an enabling signal, triggering an adder to count the value of the counting register, and transmitting an output signal of the adder to the counting register through the selector so as to trigger the counting register to increase the value of the counting register according to the output signal of the adder; transmitting a disable signal to the count register to suspend counting by the count register when the selector receives the disable signal.
In step 405, the comparator outputs a clock interrupt when the value of the count register is equal to the value of the preset compare register.
In the embodiment of the present invention, optionally, the hardware calculation method may further include the following steps: the selector receives a write-in signal output by the processor core; and transmitting the writing signal to the counting register so as to write the corresponding writing numerical value into the counting register. Thereby, the writing of the write value corresponding to the write signal into the count register is achieved.
In an optional embodiment of the present invention, before the transmitting the output signal of the adder to the count register through the selector, the method further includes: detecting whether the selector receives a write signal output by the processor core; if the selector does not receive the write signal, the step of transmitting the output signal of the adder to the counting register through the selector is executed, so that the counting register can increase the value of the counting register according to the output signal of the adder; and if the selector receives a write-in signal, the step of transmitting the write-in signal to the counting register is executed, so that the write-in value corresponding to the write-in signal is stored in the counting register. It can be seen that the selector can also be used to store the corresponding write value into the count register according to the write signal.
Optionally, the hardware calculation method provided in the embodiment of the present invention may further include: a comparator in the hardware counting device reads the value of the counting register; judging whether the read value is equal to the value of a preset comparison register or not; and if the read value is equal to the value of the preset comparison register, determining that the value of the counting register is equal to the value of the preset comparison register.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The hardware computing device, the hardware computing method, and the processor provided by the present invention are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, and the description of the embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (11)
1. A hardware computing device, wherein the hardware counting device is integrated in a processor, is a virtual clock subsystem of the processor, is a host clock subsystem independent of the processor, and comprises: the device comprises an adder, a counting register, a selector, a comparator and a comparison register;
one end of the adder is connected with the output end of the counting register, and the other end of the adder is connected with the input end of the counting register through the selector and used for counting the value of the counting register;
the selector is used for receiving a counting register signal output by a processor core, outputting a signal to the counting register according to the counting register signal so as to control the value of the counting register, and controlling the working mode of the counting register based on the counting register signal; the counting register signals comprise an enable signal and a non-enable signal;
the comparator is respectively connected with the counting register and the comparison register and is used for outputting clock interrupt when the value of the counting register is equal to the value of the comparison register.
2. The apparatus of claim 1, wherein the selector is configured to output a signal to the count register to control the value of the register in accordance with a count register signal output by a processor core, comprising:
the selector transmits the output signal of the adder to the counting register to increase the value of the counting register when receiving the enabling signal output by the processor core;
and the selector transmits a non-enable signal to the counting register when receiving the non-enable signal output by the processor core so as to suspend counting of the counting register.
3. The apparatus of claim 2, wherein the selector is further configured to receive a write signal output by a processor core and transmit the write signal to the count register to store a corresponding write value to the count register.
4. The apparatus of claim 3, wherein the selector comprises a first selector and a second selector;
the first selector is connected with the adder and used for receiving an enable signal or a non-enable signal output by the processor core and forwarding an output signal of the adder to the second selector according to the enable signal;
the second selector is connected with the counting register and is used for transmitting the writing signal to the counting register when receiving the writing signal so as to store the writing value into the counting register; or the output signal of the adder is transmitted to the counting register so as to trigger the counting register to increase the value of the counting register according to the output signal.
5. The apparatus of claim 4,
the priority of the write signal is higher than the priority of the output signal of the adder.
6. A hardware computing method applied to a hardware computing device, wherein the hardware computing device is integrated in a processor, is a virtual clock subsystem of the processor, and is independent of a host clock subsystem of the processor, and the hardware computing device is as claimed in any one of claims 1 to 5, and the method comprises:
the selector receives a counting register signal output by the processor core; the counting register signals comprise an enable signal and a non-enable signal;
controlling the value of a counting register according to the counting register signal, and controlling the working mode of the counting register based on the counting register signal;
and the comparator outputs clock interrupt when the value of the counting register is equal to the value of the preset comparison register.
7. The method of claim 6, wherein said controlling the value of said count register in accordance with said count register signal comprises:
when the selector receives an enabling signal, triggering an adder to count the value of the counting register, and transmitting an output signal of the adder to the counting register through the selector so as to trigger the counting register to increase the value of the counting register according to the output signal of the adder;
transmitting a disable signal to the count register to suspend counting by the count register when the selector receives the disable signal.
8. The method of claim 7, further comprising:
the selector receives a write-in signal output by the processor core;
and transmitting the writing signal to the counting register so as to write the corresponding writing numerical value into the counting register.
9. The method of claim 8, wherein prior to transmitting the output signal of the adder to a count register via the selector, further comprising:
detecting whether the selector receives a write signal output by the processor core;
if the selector does not receive the write-in signal, the step of transmitting the output signal of the adder to a counting register through the selector is executed;
and if the selector receives a write signal, executing the step of transmitting the write signal to the counting register.
10. The method of claim 9, further comprising:
the comparator reads the value of the counting register;
judging whether the read value is equal to the value of a preset comparison register or not;
and if the read value is equal to the value of the preset comparison register, determining that the value of the counting register is equal to the value of the preset comparison register.
11. A processor, comprising: processor core, virtual machine clock subsystem and host's clock subsystem, characterized in that, as the virtual machine clock subsystem, the hardware computing device of any of claims 1 to 5 is used.
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