JP4943763B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a DMOS (Diffused MOS) type transistor.

  A DMOS type MOS transistor has a high source / drain breakdown voltage and a high gate breakdown voltage, and is widely used in various drivers such as LCD drivers, power supply circuits, and the like. In particular, in recent years, a high breakdown voltage MOS transistor having a high drain breakdown voltage (BVds) and a low on-resistance has been demanded.

  FIG. 8 is a cross-sectional view showing a structure in which an N-channel type DMOS transistor 100 and a P-channel type MOS transistor 101 are mixedly mounted on the same semiconductor substrate.

  An N-type epitaxial layer 103 is formed on the surface of the P-type semiconductor substrate 102. An N + type buried layer 104 is formed at the interface between the epitaxial layer 103 and the bottom of the semiconductor substrate 102. The epitaxial layer 103 is separated into a plurality of regions by an insulating separation layer 105 in which a P-type impurity is diffused. In the figure, a first separation region 106 and a second separation region 107 are provided.

  The insulating separation layer 105 has a configuration in which the upper separation layer 105 a and the lower separation layer 105 b are overlapped and integrated in the epitaxial layer 103. Upper isolation layer 105 a is formed by downwardly diffusing P-type impurities such as boron from the upper surface of epitaxial layer 103. On the other hand, the lower isolation layer 105 b is formed by upwardly diffusing P-type impurities such as boron from the bottom side of the semiconductor substrate 102.

  In the epitaxial layer 103 of the first isolation region 106, the DMOS transistor 100 is formed. A gate electrode 109 is formed on the epitaxial layer 103 via a gate insulating film 108. A P type body layer 110 is formed on the surface of the epitaxial layer 103, and an N + type source layer 111 is formed on the surface of the body layer 110 adjacent to one end of the gate electrode 109. Further, an N + type drain layer 112 adjacent to the other end of the gate electrode 109 is formed on the surface of the epitaxial layer 103.

  A surface region of the body layer 110 between the epitaxial layer 103 and the source layer 111 is a channel region CH. Further, a P + type potential fixing layer 113 for fixing the potential of the body layer 110 is formed adjacent to the source layer 111.

  In the second isolation region 107, a P channel comprising a source layer 114 and a drain layer 115 formed on the surface of the epitaxial layer 103, and a gate electrode 117 formed on the epitaxial layer 103 via a gate insulating film 116. A type MOS transistor 101 is formed.

The technique related to the present invention is described in the following patent documents.
JP 2004-39774 A

  In the structure of the conventional DMOS transistor 100 described above, the epitaxial layer 103 functions as a drain region. That is, the drain layer 112 and the epitaxial layer 103 are set to the same potential. Therefore, the elements that can be mixed with the DMOS transistor 100 are limited in one isolation region surrounded by the insulating isolation layer 105 as described above. For example, it is impossible to form both the DMOS transistor 100 and the above-described P-channel MOS transistor 101 in one isolation region. In addition, the DMOS transistor 100 and the opposite conductivity type (P channel type) DMOS transistor cannot be formed in one isolation region.

  However, in recent years, miniaturization and high integration of semiconductor devices are desired. For example, 200 volts is used as the high power supply voltage (Vdd1) in one isolation region, 190 volts is used as the low power supply voltage (Vss1), and 10 volts is used as the high power supply voltage (Vdd2) in the other separation region. The voltage used in each isolation region may be different, such as using 0 volts as the voltage (Vss2). In such a case, with the conventional structure, a large number of isolation regions are formed by the insulating isolation layer 105, resulting in an increase in chip area.

  Accordingly, one object of the present invention is to reduce the chip area in a semiconductor device including a DMOS transistor.

  In addition, a DMOS transistor having a small on-resistance (resistance between source and drain) and high current driving capability is desired. Accordingly, another object of the present invention is to provide a DMOS transistor having a high source / drain breakdown voltage, a low on-resistance, and a high current driving capability.

  The main features of the present invention are as follows. That is, the semiconductor device of the present invention includes a second conductivity type well layer having an element isolation function formed on the surface of the first conductivity type semiconductor layer, and a DMOS transistor formed in the well layer. The DMOS transistor includes a second conductivity type body layer including a channel region formed on the surface of the well layer, a first conductivity type source layer formed on the surface of the body layer, and the body layer. A gate electrode formed on a portion of the well layer via a gate insulating film; a drain layer of a first conductivity type formed on the surface of the well layer; and a first electrode formed under the gate electrode to reduce on-resistance. And a first diffusion layer of one conductivity type. In addition, the 2nd conductivity type here is a conductivity type opposite to the 1st conductivity type.

  Further, the semiconductor device of the present invention has a first conductivity type higher in concentration than the first diffusion layer formed on the surface of the well layer adjacent to the end of the gate electrode on the drain layer side. And a second diffusion layer.

  The semiconductor device of the present invention is characterized in that the second diffusion layer is formed deeper than the first diffusion layer.

  In addition, the semiconductor device of the present invention includes a third diffusion layer of a second conductivity type that overlaps with the drain layer and is formed deeper than the drain layer.

  In addition, the semiconductor device of the present invention includes an insulating isolation layer that isolates the semiconductor layer into a plurality of isolation regions and insulates adjacent isolation regions, and the DMOS transistor and the DMOS transistor are the same in one isolation region. The device element using the power supply voltage is mixedly mounted.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a second conductivity type well layer having an element isolation function on the surface of the first conductivity type semiconductor layer, and formation of a gate electrode on the surface of the well layer. Forming a first conductivity type first diffusion layer for reducing on-resistance in the region, forming a gate electrode on a part of the first diffusion layer via a gate insulating film, Forming a second conductivity type body layer in the well layer and reaching a part of a region below the gate electrode; and forming a source layer adjacent to the gate electrode in the body layer And a step of forming a drain layer in the well layer.

  In the method for manufacturing a semiconductor device according to the present invention, the first conductivity type having a higher concentration than the first diffusion layer is formed on the surface of the well layer, adjacent to the end of the gate electrode on the drain layer side. And a step of forming the second diffusion layer.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a third diffusion layer of a second conductivity type that overlaps with the drain layer and is deeper than the drain layer.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: separating the semiconductor layer into a plurality of isolation regions; and forming an insulating isolation layer that insulates adjacent isolation regions; And a step of forming a device element using the same power supply voltage as that of the DMOS transistor.

  In the present invention, the second conductivity type well layer is formed in the first conductivity type semiconductor layer, and the DMOS transistor is formed in the well layer. With this configuration, the drain region of the DMOS transistor and the semiconductor layer are insulated by the well layer. Therefore, it becomes possible to efficiently mount the DMOS transistor and other device elements in one isolation region surrounded by the insulating isolation layer, and the chip area can be reduced.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment of the present invention.

  An N type epitaxial layer 2 is formed on the surface of the P type semiconductor substrate 1. An N + type buried layer 3 is formed at the interface between the epitaxial layer 2 and the bottom of the semiconductor substrate 1. A P + W layer 4 in which a P-type impurity is implanted is formed on the surface of the epitaxial layer 2. A DMOS transistor 50 is formed in the region where the P + W layer 4 is formed.

  The DMOS transistor 50 will be described. A gate electrode 6 is formed on the P + W layer 4 via a gate insulating film 5. Further, a body layer 7 into which a P-type impurity is implanted is formed on the surface of the P + W layer 4, and an N-type source layer 8 (NSD) adjacent to one end of the gate electrode 6 is formed on the surface of the body layer 7. Has been. An N-type drain layer 9 (NSD) adjacent to the other end of the gate electrode 6 is formed on the surface of the P + W layer 4. The drain layer 9 may be separated from the gate electrode 6.

  A surface region of the body layer 7 between the P + W layer 4 and the source layer 8 is a channel region CH. A P + type potential fixing layer 10 (PSD) for fixing the potential of the body layer 7 is formed in the body layer 7 and adjacent to the source layer 8.

  A P channel type MOS transistor 60 is formed in the same epitaxial layer 2. The MOS transistor 60 includes a source layer 11 (P +) and a drain layer 12 (P +) formed on the surface of the epitaxial layer 2, and a gate electrode 14 formed on the epitaxial layer 2 via a gate insulating film 13. .

  An insulating isolation layer 15 in which a P-type impurity is diffused is formed so as to surround both elements of the DMOS transistor 50 and the MOS transistor 60. The insulating separation layer 15 has a configuration in which the upper separation layer 15a and the lower separation layer 15b are overlapped and integrated in the epitaxial layer 2. Upper isolation layer 15 a is formed by downwardly diffusing P-type impurities such as boron from the upper surface of epitaxial layer 2. On the other hand, the lower isolation layer 15 b is formed by upwardly diffusing P-type impurities such as boron from the bottom side of the semiconductor substrate 1. Adjacent isolation regions are insulated by the insulating isolation layer 15.

  In the configuration as described above, the P + W layer 4 is formed in the N type epitaxial layer 2, and the N channel type DMOS transistor 50 is formed in the P + W layer 4. With this configuration, the epitaxial layer 2 and the drain region of the DMOS transistor 50 are insulated by the P + W layer 4 and can be set to potentials independent of each other. Therefore, the DMOS transistor 50 and other device elements can be efficiently mounted in one region surrounded by the insulating isolation layer 15, and the chip area can be reduced as compared with the conventional structure. In addition, this configuration does not affect the characteristics of other device elements (MOS transistor 60 in the above example).

  Further, with the above configuration, a semiconductor chip as shown in FIG. 2 can be designed. In FIG. 2, in one isolation region X surrounded by the insulating isolation layer 15, for example, a DMOS transistor using 200 volts as a high power supply voltage (Vdd1) and 190 volts as a low power supply voltage (Vss1), and the DMOS transistor Device elements such as MOS transistors and bipolar transistors using the same power supply voltages (Vdd1 and Vss1) are formed together.

  In another isolation region Y, for example, a DMOS transistor that uses 10 volts as a high power supply voltage (Vdd2) and 0 volts as a low power supply voltage (Vss2), and the same power supply voltages (Vdd2 and Vss2) as the DMOS transistor are used. Device elements such as MOS transistors and bipolar transistors are collectively formed.

  Thus, according to the configuration of the present embodiment, the isolation region can be formed for each power supply voltage to be used, and a large number of isolation regions are not formed unlike the conventional case. Therefore, the chip area as a whole can be reduced.

  Next, in the DMOS transistor formed in the P + W layer 4 as described above, a configuration with low on-resistance and improved current driving capability will be described with reference to the drawings. 3 to 6 are cross-sectional views showing the DMOS transistor formation region of the configuration in the order of the manufacturing process. The same components as those of the above-described DMOS transistor 50 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

  First, as shown in FIG. 3, an N-type impurity is ion-implanted at a high concentration on the surface of a P-type semiconductor substrate 1, and epitaxial growth is performed to form an epitaxial layer 2 and an N + buried layer 3.

Next, a P-type impurity is implanted into the insulating isolation layer forming region on the surface of the epitaxial layer 2 using a photoresist layer (not shown) as a mask, and diffused to form a lower isolation layer 15b (part of the insulating isolation layer 15). P + B). The ion implantation is performed, for example, using boron ions under the conditions of an acceleration voltage of 80 KeV and an implantation amount of 1.6 × 10 ¹⁴ / cm ² .

Next, P-type impurities are implanted into the surface of the epitaxial layer 2 using a photoresist layer (not shown) as a mask, and a P + W layer 4 is formed in a region where a DMOS transistor is to be formed. The ion implantation is performed, for example, using boron ions under the conditions of an acceleration voltage of 80 KeV and an implantation amount of 3 × 10 ¹³ / cm ² .

  Next, using a photoresist layer (not shown) as a mask, a P-type impurity is implanted into a position corresponding to the lower separation layer 15b and thermally diffused to form the upper separation layer 15a (ISO). As a result, the upper isolation layer 15a and the lower isolation layer 15b overlap in the epitaxial layer 2, and an integrated insulating isolation layer 15 is formed.

Next, using a photoresist layer (not shown) as a mask, an N-type impurity is implanted into a region of the surface of the P + W layer 4 partially including the gate electrode formation region, thereby forming an FN layer 20 for reducing on-resistance. The ion implantation is performed, for example, using arsenic (As) ions under the conditions of an acceleration voltage of 160 KeV and an implantation amount of 5 × 10 ¹² / cm ² . The reason for using arsenic (As) ions is to form the FN layer 20 in a shallow region of the P + W layer 4. Thereby, a depletion layer becomes easy to spread and a proof pressure improves. From the viewpoint of preventing punch-through, it is preferable to form the FN layer 20 in a shallow region.

  Next, as shown in FIG. 4, a gate insulating film 5 having a thickness of about 90 nm is formed on the surface of the semiconductor substrate 1 by, for example, a thermal oxidation method. Next, a gate electrode 6 having a thickness of about 400 nm is formed on the gate insulating film 5. The gate electrode 6 is patterned so as to be disposed on a part of the FN layer 20. The gate electrode 6 is made of polysilicon, refractory metal silicide or the like.

Next, using the gate electrode 6 as a part of the mask, a P-type impurity is implanted into the surface of the P + W layer 4 on the left side of the gate electrode 6 and thermally diffused to form a P + D layer 21 that becomes a part of the body layer. The At the same time, a P + D layer 22 separated from the gate electrode 6 is formed on the surface of the P + W layer 4 on the right side of the gate electrode 6. The ion implantation is performed, for example, using boron ions under the conditions of an acceleration voltage of 50 KeV and an implantation amount of 2 × 10 ¹³ / cm ² . The P + D layer 22 is formed below a contact formation region to be formed later. In addition, the P + D layer 22 is a layer that contributes to improving the electrostatic breakdown resistance by making the breakdown point deeper than when there is no P + D layer 22.

Next, N-type impurity concentration is higher than that of the FN layer 20 by injecting N-type impurities into the surface of the P + W layer 4 on the right side of the gate electrode 6 using the gate electrode 6 as a part of the mask. An N + D layer 23 in which N-type impurities are implanted deeper than 20 is formed. The ion implantation is performed, for example, using phosphorus ions under the conditions of an acceleration voltage of 100 KeV and an implantation amount of 1.5 × 10 ¹³ / cm ² . By forming the N + D layer 23, the N-type impurity concentration is gradually increased from the end of the FN layer 20 on the gate electrode 6 side to the drain region side, and the on-resistance is reduced. Further, by forming the N + D layer 23 deeper than the FN layer 20 and providing a step in the N-type impurity concentration distribution, the depletion layer below the gate electrode 6 can be easily expanded, and the effective channel length can be shortened. it can.

Next, as shown in FIG. 5, a P-type impurity is implanted into a region where the P + D layer 22 is formed using a photoresist layer (not shown) as a mask to form an FP layer 24 overlapping the P + D layer 22. The ion implantation is performed, for example, using boron ions under the conditions of an acceleration voltage of 50 KeV and an implantation amount of 1.5 × 10 ¹³ / cm ² . Note that, like the P + D layer 22, the FP layer 24 is formed below a contact formation region to be formed later, so that the breakdown point is at a deeper position and contributes to improving the resistance to electrostatic breakdown. Is a layer.

Next, using the gate electrode 6 as a part of the mask, a P-type impurity is implanted into the surface of the P + D layer 21 to form an SP + D layer 25 having a P-type impurity concentration higher than that of the P + D layer 21. The ion implantation is performed, for example, using boron ions under the conditions of an acceleration voltage of 50 KeV and an implantation amount of 2 × 10 ¹⁴ / cm ² . Thus, the body layer 7 of the present embodiment has a double structure of the P-type P + D layer 22 and the SP + D layer 25 having a higher concentration and shallower diffusion than the P + D layer 22. With this double structure, the P + D layer 21 with a low concentration can have a withstand voltage, the threshold value can be adjusted with the SP + D layer 25 with a high concentration, and punch-through can be prevented.

Next, a P-type impurity is implanted using a photoresist layer (not shown) as a mask, and the potential fixing layer 10 adjacent to the source layer 8 is formed on the surface of the SP + D layer 25. The ion implantation is performed, for example, with phosphorus ions under the conditions of an acceleration voltage of 50 KeV and an implantation amount of 1.3 × 10 ¹⁵ / cm ² .

  Next, N-type impurities are implanted using the gate electrode 6 as a part of the mask, and heat treatment is performed, thereby forming the source layer 8 (NSD) and the drain layer 9 (NSD) adjacent to each end of the gate electrode 6. To do.

  Next, as shown in FIG. 6, an interlayer insulating film 26 (for example, a silicon oxide film or a BPSG film formed by a thermal oxidation method or a CVD method) is formed on the entire surface of the semiconductor substrate 1. Next, the interlayer insulating film 26 and the gate insulating film 5 are etched using a photoresist layer (not shown) as a mask, thereby forming contact holes reaching the source layer 8, the drain layer 9, and the potential fixing layer 10. Next, a wiring layer 27 made of a conductive material such as aluminum is formed in the contact hole. The previously formed P + D layer 22 and FP layer 24 are located below the contact region.

  From the above manufacturing process, a DMOS transistor 70 having a sufficient source / drain breakdown voltage and a low on-resistance and high current driving capability can be obtained.

An example of the operating characteristics of the DMOS transistor 70 shown in FIG. 6 will be described. In the configuration of the DMOS transistor 70, a DMOS transistor (DMOS1) when the ion implantation amount of the FN layer 20 is 5.5 × 10 ¹² / cm ² , and a condition where the implantation amount is 6.0 × 10 ¹² / cm ² . The operation characteristics of the DMOS transistor (DMOS2) and the conventional DMOS transistor (Normal DMOS) shown in FIG. 8 are compared.

  FIG. 7 shows the threshold (Vt), on-resistance (Ron), transconductance (Gm), saturation current (Idsat), and off (when the gate potential, source potential, and substrate potential are 0 V) for each of the above DMOS transistors. ) Shows the measurement results of the source / drain breakdown voltage (BVdson) when on (when the source potential and the substrate potential are 0 V and the gate voltage Vg is 10 V).

  As is clear from this figure, the on-resistance (Ron) of DMOS1 and DMOS2 is about half that of the conventional structure (Normal DMOS), and the transconductance (Gm) is about 7 times larger. Therefore, it can be seen that the current driving capability is improved. It can also be seen that the withstand voltage (BVds) at the time of OFF maintains the same withstand voltage as in the conventional structure. Also, the withstand voltage (BVdson) at the time of on is sufficiently high. That is, in the configuration of the present embodiment, both the maintenance of the withstand voltage and the reduction of the on-resistance are achieved.

  Furthermore, the measurement results of another DMOS transistor in which the N + D layer 23 is not formed and the case where it is formed were compared. Then, when the N + D layer 23 was not formed, the on-resistance was about 103.1 (kΩ), whereas when it was formed, it decreased by about 6.6% to about 96.3 (kΩ). From this, it can be seen that it is preferable to provide the N + D layer 23 from the viewpoint of improving the on-resistance.

  Thus, in this embodiment described above, a well layer having a conductivity type opposite to that of the epitaxial layer is formed in the epitaxial layer, and the DMOS transistor is disposed in the well layer. Therefore, the DMOS transistor and other device elements can be efficiently mounted in one isolation region surrounded by the insulating isolation layer, and the chip area can be reduced as compared with the conventional structure.

  In the DMOS transistor of this embodiment, N-type impurity diffusion layers (FN layer 20 and N + D layer 23) are formed so that the N-type impurity concentration gradually increases from the region below the gate electrode 6 toward the drain. Therefore, the on-resistance and the mutual conductance are improved. Further, by forming the FN layer 20 shallower than the N + D layer 23, punch-through can be prevented and a high breakdown voltage can be achieved.

  Furthermore, by forming a P-type impurity diffusion layer (P + D layer 22 or FP layer 24) below the contact region of the drain layer 9, the breakdown point BD is disposed at a position deeper than the substrate surface. Therefore, the breakdown at the gate end is unlikely to occur, and the resistance to electrostatic breakdown is considered to be improved. The breakdown point here is a position where a breakdown phenomenon occurs.

  Needless to say, the present invention is not limited to the above-described embodiment, and the design can be changed without departing from the gist thereof. For example, in order to improve the electrostatic breakdown resistance, the P + D layer 22 and the FP layer 24 have a two-layer structure in the above embodiment. However, the electrostatic breakdown resistance can be similarly improved by changing the implantation conditions. It can also be made. In addition, although description on the P-channel type DMOS transistor is omitted, it is well known that the structure is the same except that the conductivity type is different. The present invention can also be applied to a structure in which the DMOS transistor of the present invention and other device elements other than the P-channel MOS transistor are mounted together.

It is sectional drawing explaining the outline of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the outline of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing explaining the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is a table | surface explaining the characteristic of the semiconductor device of this invention. It is sectional drawing explaining the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial layer 3 Buried layer 4 P + W layer 5 Gate insulating film 6 Gate electrode 7 Body layer 8 Source layer
9 Drain Layer 10 Potential Fixed Layer 11 Source Layer 12 Drain Layer 13 Gate Insulating Film 14 Gate Electrode 15 Insulating Separation Layer
15a Upper separation layer 15b Lower separation layer 20 FN layer 21 P + D layer
22 P + D layer 23 N + D layer 24 FP layer 25 SP + D layer 26 Interlayer insulating film 27 Wiring layer 50 DMOS transistor 60 MOS transistor 70 DMOS transistor
DESCRIPTION OF SYMBOLS 100 DMOS transistor 101 MOS transistor 102 Semiconductor substrate 103 Epitaxial layer 104 Buried layer 105 Insulating separation layer 105a Upper separation layer 105b Lower separation layer
106 first isolation region 107 second isolation region 108 gate insulating film 109 gate electrode 110 body layer 111 source layer 112 drain layer 113 potential fixing layer 114 source layer 115 drain layer 116 gate insulating film 117 gate electrode CH channel region BD break Down point

Claims (10)

A second conductivity type well layer having an element isolation function formed on the surface of the first conductivity type semiconductor layer;
A DMOS transistor formed in the well layer,
The DMOS transistor includes a body layer of a second conductivity type including a channel region formed on the surface of the well layer;
A first conductivity type source layer formed on the surface of the body layer;
A gate electrode formed extending from an end of the source layer through a gate insulating film;
A first conductivity type first diffusion layer formed on the surface of the well layer so as to extend from below the gate electrode in a direction opposite to the source layer;
A drain layer of a first conductivity type formed on the surface of the first diffusion layer, extending from the end of the gate electrode opposite to the source layer toward the outside of the end ;
A second diffusion layer of the first conductivity type formed extending from the surface of the first diffusion layer adjacent to the end of the gate electrode opposite to the source layer to the drain layer side; A semiconductor device comprising: The semiconductor device according to claim 1, wherein the second diffusion layer has an impurity concentration higher than that of the first diffusion layer. 3. The semiconductor device according to claim 2, wherein the second diffusion layer extends to a deeper region inside the well layer than the first diffusion layer.   The semiconductor device according to claim 1, further comprising a third diffusion layer of a second conductivity type that overlaps with the drain layer and is formed deeper than the drain layer.   The semiconductor layer is separated into a plurality of isolation regions, and an insulating isolation layer that insulates adjacent isolation regions is provided. In one isolation region, the DMOS transistor and a device element that uses the same power supply voltage as the DMOS transistor The semiconductor device according to claim 1, wherein the semiconductor device is mounted together. Forming a second conductivity type well layer on the surface of the first conductivity type semiconductor layer;
Forming a first conductivity type first diffusion layer on the surface of the well layer;
Forming a gate insulating film on the semiconductor layer including the well layer and the first diffusion layer;
Forming a gate electrode extending from the well layer to the first diffusion layer via the gate insulating film;
Forming a second conductivity type body layer extending to the well layer below the gate electrode on the surface of the well layer;
The surface of the first diffusion layer extends from the surface of the first diffusion layer adjacent to the end of the gate electrode on the side overlapping with the first diffusion layer toward the side opposite to the body layer. Forming a second diffusion layer of the first conductivity type;
Forming a source layer of a first conductivity type on the surface of the body layer from the end of the gate electrode on the side overlapping the body layer;
The first conductivity type extending from the end of the gate electrode on the side overlapping the first diffusion layer to the outside of the end, extending the surfaces of the second diffusion layer and the first diffusion layer Forming a drain layer . A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 6, wherein the second diffusion layer has an impurity concentration higher than that of the first diffusion layer. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the second diffusion layer extends to a deeper region inside the well layer than the first diffusion layer . The method further comprises the step of forming a third diffusion layer of a second conductivity type that overlaps with the drain layer after forming the gate electrode and after forming the second diffusion layer and deeper than the drain layer. A method for manufacturing a semiconductor device according to claim 6.   Separating the semiconductor layer into a plurality of isolation regions, forming an insulating isolation layer that insulates adjacent isolation regions, and utilizing the same DMOS transistor and the same power supply voltage as the DMOS transistor in one isolation region A method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a device element.

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