JP4942950B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a semiconductor nonvolatile memory element, and more particularly, to a semiconductor device having a semiconductor nonvolatile memory element formed of a thin film and a transistor. The present invention also relates to a semiconductor device such as an ID chip having a semiconductor nonvolatile memory element, a CPU, and a system LSI.

  An EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory are known as a memory that represents a semiconductor nonvolatile memory. Since these are nonvolatile, unlike the volatile DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), data is not lost even when the power is turned off. Further, when compared with a magnetic disk representing another nonvolatile memory, it has excellent characteristics in terms of integration density, impact resistance, power consumption, writing / reading speed, and the like (see, for example, Patent Document 1).

Nonvolatile memories formed using a single crystal semiconductor substrate have already been put into practical use and are on the market. In particular, nonvolatile memories having a large memory capacity, that is, a high integration density, are widely used.

On the other hand, semiconductor devices represented by ID chips capable of transmitting and receiving data such as identification information wirelessly have been put into practical use in various fields, and further expansion of the market is expected as a new type of information communication terminal. ing. An ID chip is also called a wireless tag, an RFID (Radio Frequency Identification) tag, or an IC tag, and a type having an antenna and an integrated circuit formed using a semiconductor substrate is now in practical use. is there.

In addition, by forming a nonvolatile memory in which data cannot be rewritten in an integrated circuit included in the ID chip, unauthorized rewriting of identification information of the ID chip can be prevented.
JP 2003-204000 A

However, as non-contact and contact type ID chips become widespread, it is necessary to manufacture a large number of ID chips that can be used for humans, animals and plants, commodities, banknotes, etc. at a very low cost. Therefore, the realization of the structure and process of an ID chip capable of mass production is demanded.

Currently, in manufacturing an ID chip, a method is used in which a plurality of integrated circuits are formed on a silicon wafer, and the silicon wafer is removed by polishing (called back grinding) to separate the plurality of integrated circuits. Yes. However, although the silicon wafer is expensive, it is polished and removed, so an increase in manufacturing cost cannot be avoided. Further, since an integrated circuit made of a silicon wafer is thick, when it is mounted on a product container itself, the surface has irregularities, and there is a limit to the range of design choices.

In addition, there is an urgent need to mount more semiconductor devices typified by CPUs and system LSIs in a limited volume of electronic equipment. For this reason, in order to reduce the size and weight of the semiconductor device, it is required to reduce the thickness of the integrated circuit of the semiconductor device.

Therefore, the present invention provides a semiconductor device that can be mass-produced at low cost and a method for manufacturing the semiconductor device. In addition, a semiconductor device using an extremely thin integrated circuit and a manufacturing method thereof are provided. Furthermore, a semiconductor device with low power consumption and a manufacturing method thereof are provided.

  The present invention includes a semiconductor nonvolatile memory element (hereinafter referred to as a memory transistor) on an insulating surface, and the floating gate electrode of the memory transistor is formed of a plurality of conductive particles or semiconductor particles. The gist of the semiconductor device is as follows.

Another feature of the present invention is that in addition to the memory transistor, a transistor whose threshold voltage is controlled is included in part. A typical example of such a transistor includes a semiconductor region having a first conductivity type region covered with a gate electrode, a source region and a drain region of a second conductivity type, and a channel region. This region is provided between the channel region and one of the source region and the drain region. Here, the first conductivity type region is a semiconductor region exhibiting one of n-type or p-type, and the second conductivity type source region and drain region are semiconductor regions exhibiting the other of n-type or p-type. .

According to another aspect of the present invention, the first semiconductor region, the first insulating film formed on the first semiconductor region, the floating gate electrode formed on the first insulating film, and the floating gate electrode are formed. A first transistor having a second insulating film; a first gate electrode formed on the second insulating film; a second semiconductor region; a third insulating film formed on the second semiconductor region; 3 and a second transistor having a second gate electrode formed on the insulating film, the first transistor and the second transistor are formed on the same insulating surface, and the floating gate electrode includes a plurality of interspersed It is a semiconductor device characterized by being a particle.

According to another aspect of the present invention, the first semiconductor region, the first insulating film formed on the first semiconductor region, the floating gate electrode formed on the first insulating film, and the floating gate electrode are formed. A first transistor having a second insulating film, a first gate electrode formed on the second insulating film, a second semiconductor region, a third insulating film formed on the second semiconductor region, and 3 A second transistor having a second gate electrode formed on the first insulating film, a third semiconductor region, a fourth insulating film formed on the third semiconductor region, and a fourth insulating film. A third transistor having a third gate electrode, wherein the second semiconductor region has a source region and a drain region to which an impurity element imparting one of n-type and p-type is added, and the third semiconductor A region is a non-contributing one of n-type or p-type. A first transistor and a second transistor, each having a source region and a drain region to which a physical element is added, and a region to which an impurity element imparting the other of n-type and p-type is added and is covered with the third gate electrode The third transistor is formed on the same insulating surface, and the floating gate electrode is a plurality of scattered particles. Note that the region covered with the third gate electrode and formed of the impurity element imparting the other of the n-type and the p-type is formed between the channel region of the third semiconductor region and one of the source region and the drain region. The

According to another aspect of the present invention, the first semiconductor region, the first insulating film formed on the first semiconductor region, the floating gate electrode formed on the first insulating film, and the floating gate electrode are formed. A first transistor having a second insulating film; a first gate electrode formed on the second insulating film; a second semiconductor region; a third insulating film formed on the second semiconductor region; A thin film integrated circuit having a second transistor having a second gate electrode formed on the three insulating film and an antenna, the first transistor and the second transistor being formed on the same insulating surface and floating; The gate electrode is a semiconductor device including a plurality of scattered particles.

According to another aspect of the present invention, the first semiconductor region, the first insulating film formed on the first semiconductor region, the floating gate electrode formed on the first insulating film, and the floating gate electrode are formed. A first transistor having a second insulating film; a first gate electrode formed on the second insulating film; a second semiconductor region; a third insulating film formed on the second semiconductor region; A second transistor having a second gate electrode formed on the third insulating film; a third semiconductor region; a fourth insulating film formed on the third semiconductor region; and a fourth insulating film. A thin film integrated circuit having a third transistor having a third gate electrode and an antenna, wherein the first to third transistors are formed on the same insulating surface, and the floating gate electrodes are scattered. Multiple particles The second semiconductor region has a source region and a drain region to which an impurity element imparting one of n-type or p-type is added, and the third semiconductor region is an impurity element imparting one of n-type or p-type And a source region and a drain region to which is added, and a region which is covered with the third gate electrode and to which an impurity element imparting the other of n-type and p-type is added. Note that the region covered with the third gate electrode and added with the impurity element imparting the other of n-type or p-type is formed between the channel region of the third semiconductor region and one of the source region and the drain region. The

The thin film integrated circuit has one or more selected from a power supply circuit, a clock generation circuit, a data demodulation / modulation circuit, an interface circuit, a control circuit, and a memory. Further, the thin film integrated circuit may be provided over glass or a flexible substrate.

  In the present invention, the floating gate electrode is a plurality of particles formed of a semiconductor material or a conductive material. At this time, the diameter of the particles of the floating gate electrode is preferably 1 to 5 nm. One or more of the first to third semiconductor regions are formed of a crystalline semiconductor film or a single crystal semiconductor.

The first insulating film is formed by laminating a silicon oxide film having a thickness of 1 to 2 nm and a silicon nitride film having a thickness of 1 to 5 nm in this order from the first semiconductor region side. A silicon nitride film having a thickness of 10 to 20 nm and a silicon oxide film having a thickness of 20 to 50 nm are sequentially stacked from the first semiconductor region side, and a silicon oxide film having a thickness of 1 to 2 nm and a silicon nitride having a thickness of 1 to 5 nm. A film and a silicon oxide film having a thickness of 20 to 50 nm are sequentially stacked from the second semiconductor region side, and the fourth insulating film is a silicon oxide film having a thickness of 1 to 2 nm and a nitridation having a thickness of 1 to 5 nm. It is preferable that a silicon film and a silicon oxide film having a thickness of 20 to 50 nm are sequentially stacked from the third semiconductor region side.

  The transistor of the present invention may have a sidewall structure or a silicide structure.

According to one embodiment of the present invention, a semiconductor film is formed over an insulating surface, a crystalline semiconductor film is formed by laser irradiation, and part of the crystalline semiconductor film is etched to form the first semiconductor region and the first semiconductor region. After the two semiconductor regions are formed, a first insulating film is formed on the first semiconductor region and the second semiconductor region, a plurality of particles are formed on the first insulating film, and formed on the second semiconductor region. After forming a floating gate electrode by selectively etching a plurality of particles, a second insulating film is formed on the floating gate electrode and the first insulating film, and a first conductive film is formed on the second insulating film. Then, after part of the first conductive film is etched to form the first gate electrode and the second gate electrode, an impurity element is added to the first semiconductor region and the second semiconductor region to activate the impurity element. After forming the source and drain regions, the source wiring The other is a method for manufacturing a semiconductor device and forming a drain wiring.

According to another embodiment of the present invention, a semiconductor film is formed over an insulating surface, a laser beam is irradiated on the semiconductor film to form a crystalline semiconductor film, and a part of the crystalline semiconductor film is etched. Forming a first semiconductor region and a second semiconductor region; forming a first insulating film on the first semiconductor region and the second semiconductor region; forming a plurality of particles on the first insulating film; After selectively removing some of the plurality of particles formed on one insulating film, a second insulating film is formed on the remaining plurality of particles and the first insulating film, and the second insulating film A first conductive film is formed thereon, and the first conductive film and a part of the remaining plurality of particles are selectively removed to form a first gate electrode, a second gate electrode, and a floating gate electrode. , Adding an impurity element to the first semiconductor region and the second semiconductor region, After forming the source and drain regions are activated, a method for manufacturing a semiconductor device and forming a source wiring and a drain wiring in contact with each of the source and drain regions.

According to one embodiment of the present invention, a semiconductor film is formed over a substrate, laser light is irradiated to form a crystalline semiconductor film, and part of the crystalline semiconductor film is etched to form a first semiconductor region and a second semiconductor region. After forming the semiconductor region and the third semiconductor region, a first insulating film is formed on the first semiconductor region, the second semiconductor region, and the third semiconductor region, and a plurality of particles are formed on the first insulating film. A plurality of particles formed on the second semiconductor region and the third semiconductor region are selectively etched to form a floating gate electrode, and then a second insulating film is formed on the floating gate electrode and the first insulating film. Forming a first conductive film on the second insulating film, etching a part of the first conductive film to form a first gate electrode, a second gate electrode, and a third gate electrode; After covering the first semiconductor region and the second semiconductor region with a mask, the third gate An impurity element imparting one of n-type and p-type is added to the third semiconductor region at an angle of 0 to 60 degrees with respect to the surface of the third semiconductor region and from one direction to the surface of the third semiconductor region, and a mask is formed. After removing, an impurity element imparting the other of n-type or p-type is added at an angle perpendicular to the surfaces of the first semiconductor region to the third semiconductor region, and heated to form a source region and a drain region, A method for manufacturing a semiconductor device is characterized in that a source wiring or a drain wiring is formed.

In the present invention, laser light for crystallizing an amorphous semiconductor film is continuous wave laser light or pulsed laser light. The pulse oscillation frequency is preferably 0.5 MHz or more. In addition, when the crystalline semiconductor film is etched, it is preferable to perform etching so that the channel regions of the first to third semiconductor regions are aligned.

  Further, when an impurity element imparting one of n-type and p-type is added to the third semiconductor region at an angle of 0 to 60 degrees with respect to the surface of the third semiconductor region, the substrate may be fixedly added. preferable.

  Since the present invention forms a semiconductor device using a thin film integrated circuit formed on an inexpensive substrate such as glass, it can be manufactured at low cost. In addition, after a thin film integrated circuit is formed using a large substrate, a plurality of thin film integrated circuits can be cut out to manufacture a semiconductor device, so that the cost can be reduced. Furthermore, a semiconductor device in which power consumption can be reduced can be manufactured by providing a semiconductor element whose threshold voltage is controlled more than that of another semiconductor element in part of the integrated circuit.

Embodiments of the present invention will be described below with reference to the drawings. However, it should be understood by those skilled in the art that the present invention can be implemented in many different modes, and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a manufacturing process of a semiconductor device having an integrated circuit over an insulating substrate will be described with reference to FIGS. As the transistor, a thin film transistor (hereinafter referred to as TFT) will be described.

  As shown in FIG. 1A, a semiconductor film 101 is formed over a substrate. Next, mask patterns 102 and 103 formed of resist, organic resin, or the like are provided over the semiconductor film 101.

  Examples of the substrate 100 include a glass substrate, a quartz substrate, a ceramic substrate, a plastic substrate, a stainless steel substrate, and a flexible substrate. In addition, a semiconductor film may be formed using an SOI (Silicon on Insulator) substrate. When using these substrates, if a base film (not shown) in contact with the substrate is required, it may be appropriately used. In this embodiment mode, the substrate 100 including the base film is shown.

As the semiconductor film 101, a crystalline semiconductor obtained by crystallizing an amorphous semiconductor film formed by a low pressure thermal CVD method, a plasma CVD method, a sputtering method, or the like by a laser crystallization method is preferably used. Further, a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film formed by the above film formation method by a solid phase growth method, a crystalline semiconductor film formed by using the technique disclosed in Japanese Patent No. 3300153 is used. Also good. Alternatively, the crystalline semiconductor film formed by the method may be irradiated with a laser to increase crystallinity. Alternatively, a crystalline semiconductor film obtained by laser crystallization of a microcrystalline semiconductor film formed using silane (SiH ₄ ) as a raw material may be used. Further, a microcrystalline semiconductor film may be used as the semiconductor film.

  As a semiconductor material of the semiconductor film, a compound semiconductor material such as silicon (Si), germanium (Ge), a silicon germanium alloy, silicon carbide (silicon carbide), gallium arsenide, or the like can be used.

In the case of laser crystallization, it is desirable to perform thermal annealing on the semiconductor film at 500 ° C. for 1 hour before laser crystallization in order to increase the resistance of the semiconductor film to the laser. By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second harmonic to the fourth harmonic of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. Power density at this time is approximately 0.01 to 100 MW / cm ² (preferably 0.1~10MW / cm ^2). Then, irradiation is performed at a scanning speed of about 10 to 200 cm / sec.

As the laser, a known continuous wave gas laser or solid-state laser can be used. Examples of gas lasers include Ar laser and Kr laser, and solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, Y ₂ O ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser. Etc.

  Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from melting a semiconductor film by irradiating laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction of the included crystal grains and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in at least the channel direction of the TFT.

  Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. As a result, it is possible to suppress the roughness of the semiconductor surface by laser light irradiation, and to suppress the variation in threshold voltage caused by the variation in interface state density.

In this embodiment mode, a crystalline silicon film is formed by irradiating an amorphous semiconductor film with pulsed laser light. Thereafter, in order to control a threshold value of a transistor to be formed later, the semiconductor film may be doped with B ₂ H ₆ to perform channel doping.

  The mask patterns 102 and 103 form a resist mask using a known photolithography process. In addition, a mask can be formed by discharging an insulating material such as an organic resin or an inorganic material by an inkjet method or a droplet discharging method that can discharge a material to a predetermined place. It is also possible to use a printing method. Furthermore, by reducing the area of the mask patterns 102 and 103, a semiconductor device in which memory transistors and TFTs are highly integrated can be manufactured.

  Next, as shown in FIG. 1B, the semiconductor film 101 is etched using the mask patterns 102 and 103 to form a first semiconductor region 111 and a second semiconductor region 112. The first semiconductor region 111 becomes an active region of a semiconductor memory transistor formed later, and the second semiconductor region 112 becomes an active region of a TFT formed later.

  Next, after removing the mask patterns 102 and 103, a first insulating film 113 is formed on the semiconductor regions 111 and 112 and the substrate 100. The first insulating film 113 has a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm. The first insulating film later functions as a tunnel oxide film in the memory transistor and as a part of the gate insulating film in the TFT. For this reason, it is preferable that the thinner the first insulating film, the easier the tunnel current to flow and the high speed operation becomes possible. Further, as the first insulating film is thinner, charges can be accumulated in the floating gate electrode at a lower voltage. As a result, it is possible to reduce power consumption of a semiconductor device formed later.

As a method for forming the first insulating film 113, the surface of the semiconductor region is oxidized using a GRTA (Gas Rapid Thermal Anneal) method, an LRTA (Lamp Rapid Thermal Anneal) method, or the like, and a thermal oxide film is formed. A thin first insulating film can be formed. In addition to this method, a CVD method, a coating method, or the like may be used. The first insulating film 113 can be formed using a silicon oxide film or a silicon nitride film. Alternatively, a stacked structure of a silicon oxide film and a silicon nitride film, a silicon oxide film, a silicon nitride film, and a silicon oxide film may be employed from the substrate 100 side. In this embodiment mode, the first insulating film 113 is formed by stacking a silicon oxide film and a silicon nitride film.

Next, a plurality of conductive particles or semiconductor particles (hereinafter, referred to as dispersed particles) 114 dispersed (scattered) over the first insulating film 113 are formed. As a method for manufacturing the dispersed particles, a known method such as a sputtering method, a plasma CVD method, a low pressure CVD (LPCVD) method, a vapor deposition method, or a droplet discharge method can be used. When dispersed particles are formed by a plasma CVD method, a low pressure CVD (LPCVD) method, a vapor deposition method, a droplet discharge method, or the like, it is possible to reduce the impact on the first insulating film when the dispersed particles are formed. 1 It is possible to suppress the occurrence of defects in the insulating film. As a result, a highly reliable semiconductor device can be manufactured. Further, after forming a conductive film or a semiconductor film by the above method, the dispersed particles can be formed by etching into a desired shape. The size of the dispersed particles is 0.1 to 10 nm, preferably 2 to 5 nm. Moreover, as a material of the conductive particles, gold, silver, copper, palladium, platinum, cobalt, tungsten, nickel, or the like can be used. As a material of the semiconductor particles, silicon (Si), germanium (Ge), a silicon germanium alloy, or the like can be used. Here, silicon fine particles are formed as the dispersed particles 114.

Here, some of the dispersed particles may be aggregated.

  Next, a mask pattern 115 is formed on the dispersed particles 114. Here, the mask pattern 115 is formed on the first semiconductor region 111 to be a memory transistor later.

Next, as shown in FIG. 1C, part of the dispersed particles 114 is etched using the mask pattern 115 to form the floating gate electrode 121. As a method for removing the dispersed particles 114, a known etching method such as a dry etching method or a wet etching method can be used. Note that if dry etching is used when the thickness of the first insulating film 113 on which the dispersed particles 114 are formed is thin, defects may occur in the first insulating film due to plasma bombardment. For this reason, it is preferable to remove by wet etching. Here, the silicon microcrystals that are the dispersed particles 114 are selectively removed by a wet etching method using an NMD ₃ solution (an aqueous solution containing 0.2 to 0.5% tetramethylammonium hydroxide) or the like.

The floating gate electrode is formed of dispersed particles. For this reason, even when the first insulating film functioning as the tunnel oxide film has a defect, it is possible to prevent all charges accumulated in the floating gate electrode from flowing out of the defect into the semiconductor region. As a result, a highly reliable semiconductor memory transistor can be formed.

Next, after removing the mask pattern 115, a second insulating film 122 is formed on the floating gate electrode 121 and the first insulating film 113. The second insulating film 113 has a thickness of 1 to 100 nm, preferably 10 to 70 nm, and more preferably 10 to 30 nm. The second insulating film 122 needs to maintain insulation between the floating gate electrode 121 and a gate electrode formed later in the memory transistor. For this reason, it is preferable to set the film thickness so that the leakage current does not increase between them. Similar to the first insulating film 113, the second insulating film 122 can be formed using a silicon oxide film or a silicon nitride film. Alternatively, a stacked structure including two layers of a silicon oxide film and a silicon nitride film, or three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film may be employed from the substrate 100 side. Note that it is preferable to form a silicon oxide film in contact with the semiconductor region because an interface state between the gate insulating film and the semiconductor region is lowered. Here, the second insulating film 122 is formed with a stacked structure of a silicon oxide film with a thickness of 10 nm and a silicon nitride film with a thickness of 20 nm.

Thereafter, after forming the second insulating film, as shown in FIG. 1B, the dispersed particles and a mask pattern covering the dispersed particles may be formed to form the second floating gate electrode. Furthermore, the same process may be repeated to form a plurality of stacked floating gate electrodes.

  Next, a first conductive film 123 is formed over the second insulating film 122. The first conductive film can be formed by a known method such as sputtering, vapor deposition, or CVD. The first conductive film is selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and neodymium (Nd). Or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor film to which an impurity element is added can be used.

  Note that as the material of the first conductive film 123, it is desirable to use a material whose etching rate is sufficiently higher than that of the second insulating film 122. As a result, over-etching of the second insulating film 122 exposed when the first conductive film is etched can be prevented.

  Next, mask patterns 124 and 125 are formed on the first conductive film 123. As a method for forming the mask patterns 124 and 125, a method similar to that for the mask patterns 102 and 103 can be used as appropriate. Further, the pattern formed by the above method may be slimmed by ashing or the like to reduce the width of the mask pattern. As a result, it is possible to form a TFT having a short channel structure with a narrow width in the channel length direction of a gate electrode to be formed later, and a TFT capable of high-speed operation can be formed. The mask patterns 124 and 125 are mask patterns 124 and 125 for forming gate electrodes later. Therefore, when the gate electrode is formed using the droplet discharge method, the mask patterns 124 and 125 are not necessarily provided.

  Next, as shown in FIG. 1D, the first conductive film is etched using the mask patterns 124 and 125 to form gate electrodes 131 and 132. The width of the gate electrode is 0.2 to 1.5 μm, preferably 0.2 to 0.7 μm. By setting the width of the gate electrode within the range, a memory transistor and a TFT having a short channel length can be formed later, and a semiconductor device capable of high-speed operation can be manufactured.

  Next, an impurity element imparting n-type or p-type is added to each of the first semiconductor region 111 and the second semiconductor region 112 using the mask patterns 124 and 125 and the gate electrodes 131 and 132 as masks. Next, after removing the mask patterns 124 and 125, an insulating film is formed, and an impurity element is activated by heat treatment, a GRTA method, an LRTA method, or the like, so that source and drain regions 133 to 136 are formed. . Thereafter, an inorganic insulating film made of a silicon nitride film may be provided over the second insulating film and the gate electrode, and heat treatment may be performed. By forming this inorganic insulating film under the condition that hydrogen is contained in the film and performing heat treatment, it is possible to hydrogenate the dangling bonds at the end of each semiconductor region.

  Next, as illustrated in FIG. 1E, a third insulating film functioning as an interlayer insulating film is formed over the second insulating film 122. For the third insulating film, an organic resin having heat resistance such as polyimide, acrylic, or polyamide can be used. In addition to the organic resin, a low dielectric constant material (low-k material), a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material (hereinafter referred to as a siloxane-based resin), or the like is used. be able to. The siloxane-based resin may have at least one of an organic group such as an alkyl group or an aromatic hydrocarbon in addition to hydrogen as a substituent. Moreover, you may have a fluoro group. For the formation of the third insulating film, depending on the material, spin coating, dipping, spray coating, droplet discharge method, ink jet method, screen printing, offset printing, doctor knife, roll coater, curtain coater, knife coater, A CVD method, a vapor deposition method, or the like can be employed. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the third insulating film may be formed by stacking these insulating films. Here, acrylic is applied and baked to form a third insulating film.

Next, a part of the third insulating film, the second insulating film 122, and a part of the first insulating film 113 are etched by a photolithography process and an etching process to form contact holes, and the source region and the drain region are formed. Expose part. At this time, the etched third insulating film is referred to as a third insulating layer 141, the etched second insulating film is referred to as a second insulating layer 142, and the etched first insulating film is referred to as a first insulating layer 143. Note that here, the third insulating layer 141 is an insulating film having a flat surface, but the third insulating layer 141 may not be flat.

Next, source and drain electrodes 144 to 147 connected to the source and drain regions are formed. The source electrode and the drain electrode can be formed by forming a conductive film by a PVD method (Physical Vapor Deposition), a CVD method (Chemical Vapor Deposition), a vapor deposition method, or the like, and then etching into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. Source region and drain region materials are Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba, etc. It is formed using a metal, an alloy thereof, or a metal nitride thereof. Moreover, it is good also as these laminated structures.

Here, the positional relationship between the end portions of the gate electrode 131 and the floating gate electrode 121 will be described with reference to FIG. In FIG. 27, the width of the gate electrode 131 is indicated as L1 to L3, and the width of the floating gate electrode is indicated as D1 to D3. In FIG. 27A, the width L1 of the gate electrode 131 and the width D1 of the floating gate electrode 121 are equal to each other, that is, the memory transistor in which the end of the gate electrode and the end of the floating gate electrode substantially match each other. Indicates.

  In FIG. 27B, the width D2 of the floating gate electrode 121 is larger than the width L2 of the gate electrode 131, that is, both ends of the floating gate electrode are provided outside the both ends of the gate electrode. A memory transistor is shown. At this time, the floating gate electrode 152 provided outside the gate electrode 131 does not function as a charge storage layer. Therefore, the structure in which both end portions of the floating gate electrode 121 are provided outside the both end portions of the gate electrode 131 and the structure that overlaps with each other may be appropriately selected so as to be advantageous for the manufacturing process and miniaturization.

FIG. 27C shows a memory transistor having a structure in which the width D3 of the floating gate electrode 121 is smaller than the width L3 of the gate electrode 131. In this case, the memory transistor has a so-called split gate electrode structure. The split gate electrode structure refers to an element that constitutes a memory transistor and a selection transistor for selecting a memory transistor by one semiconductor region 111 and a gate electrode 131. This is a structure in which the memory transistor 162 and the selection transistor 163 are controlled by a pair of signal lines 160 and 161 as shown in FIG. Such a configuration has an excellent operation margin because the selectability of the memory cell can be maintained by the selection transistor 163 even when the memory transistor is in an over-erased state (a state that is more negative than the threshold voltage). Note that FIG. 27C illustrates a structure in which one end of the floating gate electrode matches the end of the gate electrode; however, the structure is not limited thereto. Both ends of the floating gate electrode 121 may be provided inside the both ends of the gate electrode 131.

Further, the memory transistor 148 and the TFT 149 can be peeled from the substrate 100 shown in FIG. 1 by the following method. As a peeling method, (1) a substrate having a heat resistance of about 300 to 500 degrees is used as the substrate 100, a metal oxide film is provided between the substrate 100, the memory transistor 148, and the TFT 149, and the metal oxide film is (2) An amorphous silicon film containing hydrogen is provided between the substrate 100 and the memory transistors 148 and TFT 149, and irradiated with laser light or gas. A method of removing the memory transistor 148 and the TFT 149 by removing the amorphous silicon film by etching with a solution; (3) mechanically removing the substrate 100 on which the memory transistor 148 and the TFT 149 are formed; or by removing by etching with solution or CF ₃ and the like of the gas, the notes And a method of disconnecting the transistors 148 and TFT149 the like. The peeled memory transistor 148 and the TFT 149 may be attached to the flexible substrate using a commercially available adhesive, for example, an adhesive such as an epoxy resin adhesive or a resin additive.

As described above, when the peeled memory transistor 148 and the TFT 149 are attached to a flexible substrate, a semiconductor device which is thin, light, and hardly broken even when dropped can be provided. In addition, since the flexible substrate has flexibility, it can be bonded on a curved surface or an irregular shape, and a wide variety of uses can be realized. Further, if the substrate 100 is reused, an inexpensive semiconductor device can be provided.

  Through the above process, the memory transistor 148 including the first semiconductor region 111, the first insulating layer 143 functioning as a tunnel oxide film, the floating gate electrode 121, the second insulating layer 142, and the gate electrode 131, and the second semiconductor A semiconductor device including the region 112, the first insulating layer 143 and the second insulating layer 142 functioning as a gate insulating film, and the TFT 149 including the gate electrode 132 can be formed over the same substrate. The TFT 149 includes a decoder circuit for selecting a memory transistor, a peripheral circuit such as a write / read circuit, a functional circuit such as a CPU, DRAM, an image processing circuit, and an audio processing circuit, a buffer circuit, a shift register circuit, a level shifter circuit, and a sampling circuit. It can be suitably used for a drive circuit or the like.

  Since the semiconductor device formed in this embodiment can be formed using a crystalline silicon film, it can be manufactured without using an expensive single crystal semiconductor substrate. For this reason, cost reduction is possible. In addition, a large-area substrate is used as the substrate 100, a circuit pattern of a plurality of semiconductor devices is formed by the above-described process, and finally, a rectangular shape or a strip shape is divided, and individual semiconductor devices are taken out, so that a large amount of semiconductors are obtained. It is possible to form a device. As a result, the cost can be reduced. Further, a thin semiconductor device can be manufactured by peeling the memory transistor 148 and the TFT 149 manufactured in this embodiment and bonding them to a flexible substrate.

In addition, since particles dispersed in the floating gate electrode of the memory transistor are used, outflow of accumulated charges due to defects in the tunnel oxide film can be avoided. For this reason, a highly reliable semiconductor device can be formed.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device including a memory transistor in which end portions of a floating gate electrode and a gate electrode are substantially the same as those in Embodiment 1 will be described with reference to FIGS.

  As shown in FIG. 29A, dispersed particles 114 are formed over the first insulating film 113 as in the first embodiment. Next, a mask pattern 155 is formed. Here, the mask pattern 155 may cover at least the first semiconductor region 111 serving as the active region of the memory transistor without covering the second semiconductor region 112 serving as the active region of the TFT.

  Next, as shown in FIG. 29B, a second insulating film 122 and a first conductive film 123 are formed. Next, mask patterns 124 and 125 are formed.

  Next, as shown in FIG. 29C, the first conductive film 123, the second insulating film 122, and a part of the remaining dispersed particles 151 are removed by etching using the mask patterns 124 and 125, and the gate electrode 131 and 132, second insulating layers 165 and 166, and a floating gate electrode 167 formed of dispersed particles are formed. Here, the first conductive film 123 and the second insulating film 122 are etched by dry etching. Thereafter, the mask patterns 124 and 125 are not removed, and a part of the remaining dispersed particles 151 is etched by wet etching. By this step, the gate electrode 131 and the floating gate electrode 167 are formed in a self-aligning manner.

Thereafter, the memory transistor 178 and the TFT 179 can be formed by the same process as that in Embodiment Mode 1.

Through the above process, the memory transistor 178 including the first semiconductor region 111, the first insulating layer 143 functioning as a tunnel oxide film, the floating gate electrode 167, the second insulating layer 165, and the gate electrode 131, and the second semiconductor A semiconductor device including the region 112, the first insulating layer 143 and the second insulating layer 166 functioning as a gate insulating film, and the TFT 179 including the gate electrode 132 can be formed over the same substrate.

(Embodiment 3)
In this embodiment, a process of forming a memory transistor and a MOS transistor over the same substrate using a single crystal semiconductor substrate will be described with reference to FIGS.

    As illustrated in FIG. 2A, element isolation regions 202 to 204 are formed in the substrate 201. The substrate 201 is a single crystal semiconductor substrate or a compound semiconductor substrate, and is typically an n-type or p-type single crystal silicon substrate, GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, or the like. Is mentioned. An SOI substrate (Silicon On Insulator) can also be used. In this embodiment, a single crystal silicon substrate is used as the substrate 201. For the element isolation regions 202 to 204, a known selective oxidation method (LOCOS (Local Oxidation of Silicon) method) or a trench isolation method can be used as appropriate. Here, as the element isolation regions 202 to 204, a part of the silicon substrate is oxidized by a LOCOS method to form a silicon oxide film. Thereafter, well ion implantation, channel stop ion implantation, and threshold voltage adjustment ion implantation are appropriately performed.

  Next, the surface of the substrate 201 is washed to expose the surface of the substrate 201. Thereafter, the first insulating film 211 is formed by a known method. Since the first insulating film functions as a tunnel oxide film of the memory transistor, the film thickness is preferably thin. When the film thickness is thin, charges can be accumulated in the floating gate electrode with a low voltage, and a semiconductor device with low power consumption can be formed. Here, as the first insulating film 211, a silicon oxide film is formed by a thermal oxidation method.

  Next, the dispersed particles 114 are formed over the first insulating film 211 as in the first embodiment. Next, a mask pattern 213 is formed in a region where a memory transistor will be formed later.

  Next, part of the dispersed particles 114 is etched to form the floating gate electrode 121 as shown in FIG. Next, a second insulating film 222 is formed over the element isolation regions 202 to 204, the first insulating film 211, and the floating gate electrode 121. Note that the floating gate electrode may be formed using a process similar to that in Embodiment 2. Next, a first conductive film 223 is formed over the second insulating film 222. The second insulating film 222 and the first conductive film 223 can be formed using a material and a deposition method similar to those of the second insulating film 122 and the first conductive film 123 in Embodiment 1, respectively. Next, mask patterns 124 and 125 are formed on the first conductive film 223.

  Next, the first conductive film is etched using the mask patterns 124 and 125 to form gate electrodes 131 and 132 as shown in FIG. Next, an impurity element is added to the substrate 201 in a self-aligning manner using the mask patterns 124 and 125 and the gate electrodes 131 and 132 as masks. Next, after removing the mask patterns 124 and 125, activation of the impurity element is performed by heat treatment, a GRTA method, an LRTA method, or the like, so that source and drain regions 233 to 236 are formed.

  Next, as illustrated in FIG. 2D, a third insulating film is formed over the second insulating film 222. Thereafter, part of the third insulating film, part of the second insulating film 222, and part of the first insulating film 211 are etched to form contact holes, and part of the source and drain regions are exposed. Here, the etched third insulating film is referred to as a third insulating layer 141, the etched second insulating film is referred to as a second insulating layer 242, and the etched first insulating film is referred to as a first insulating layer 243. Thereafter, source and drain electrodes 144 to 147 connected to the source region and the drain region are formed.

Through the above steps, the memory transistor 251 including the substrate 201 using a semiconductor single crystal, the first insulating layer 243 functioning as a tunnel oxide film, the floating gate electrode 121, the second insulating layer 242, and the gate electrode 131, A semiconductor device having a substrate 201 using a semiconductor single crystal, a first insulating layer 243 and a second insulating layer 242 functioning as a gate insulating film, and a MOS transistor 252 including a gate electrode 132 is formed over the same substrate. can do. The MOS transistor 252 includes a decoder circuit for selecting a memory transistor, a peripheral circuit such as a write / read circuit, a functional circuit such as a CPU, DRAM, an image processing circuit, and an audio processing circuit, a buffer circuit, a shift register circuit, a level shifter circuit, and the like. It can be suitably used for a drive circuit such as a sampling circuit.

Further, an SOI substrate (Silicon On Insulator) is used as the substrate 201, and the memory transistor and the MOS transistor can be separated by a separation method using an oxide insulating film from the silicon substrate as described in Embodiment Mode 1. Further, by attaching the peeled memory transistor and MOS transistor to a flexible substrate in the same manner as in Embodiment Mode 1, the semiconductor device can be thinned.

Further, since dispersed particles are used as the floating gate electrode of the memory transistor, it is possible to avoid the outflow of accumulated charges due to a defect in the tunnel oxide film. For this reason, a highly reliable semiconductor device can be formed.

  In this embodiment, a manufacturing process of a semiconductor device including a memory transistor and a CMOS circuit over the same substrate will be described with reference to FIGS. In this embodiment, the memory transistor and the TFT have a single drain structure.

  As shown in FIG. 3A, a first insulating film 301 is formed over a glass substrate 300. The first insulating film 301 functions as a blocking film for preventing an impurity element from the substrate from diffusing into a semiconductor region to be formed later. Therefore, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed as the first insulating film 301. Further, a silicon oxide film and a silicon nitride film may be continuously stacked.

  Next, an amorphous silicon film is formed over the first insulating film 301, and a crystalline silicon film is formed by irradiating the amorphous silicon film with pulsed laser light having a frequency of 80 MHz. Next, the crystalline silicon film is etched into a desired shape by a photolithography process and an etching process, so that the first semiconductor region 303, the second semiconductor region 304, and the third semiconductor region 305 are formed. Note that the first semiconductor region 303 functions as an active region of a later memory transistor, the second semiconductor region 304 functions as an active region of a later n-channel TFT, and the third semiconductor region 305 functions as an active region of a later p-channel TFT. .

  Next, after removing the natural oxide film formed on the surfaces of the first to third semiconductor regions 303 to 305, the surface is exposed to ozone water containing hydroxy radicals for several tens of seconds to several minutes. A silicon oxide film is formed. Thereafter, the silicon oxide film is further densified by a GRTA (Gas Rapid Thermal Anneal) method or an LRTA (Lamp Rapid Thermal Anneal) method to form second insulating films 306 to 308 having a thickness of 1 to 2 nm. By this method, since the treatment can be performed in a short time and at a high temperature, it is possible to form a dense and thin second insulating film without stretching the substrate. Next, a third insulating film 309 is formed over the second insulating films 306 to 308 and the glass substrate 300. Here, a silicon nitride film or a silicon nitride oxide film (SiNO (N> O)) with a thickness of 1 to 5 nm is formed as the third insulating film 309.

  Next, silicon fine particles 310 are formed as dispersed particles on the third insulating film 309 by a plasma CVD method. Next, a fourth insulating film 311 is formed on the silicon fine particles 310 and the third insulating film 309. As the fourth insulating film 311, a silicon nitride film or a silicon nitride oxide film (SiNO (N> O)) with a film thickness of 10 to 20 nm is formed by plasma CVD, and then a mask pattern 312 is formed by a photolithography process. It is formed on the first semiconductor region 303.

  Next, as shown in FIG. 3B, the fourth insulating film and part of the silicon fine particles 310 are etched using the mask pattern 312 to form an insulating layer 313 having a floating gate electrode. Here, the fourth insulating film is etched by dry etching to expose the silicon fine particles 310, and then the silicon fine particles using an NMD3 solution (an aqueous solution containing 0.2 to 0.5% tetramethylammonium hydroxide) or the like. Etch. Here, the floating gate electrode is formed of the remaining silicon fine particles.

  Next, as illustrated in FIG. 3C, a fifth insulating film 321 is formed over the insulating layer 313 having the fourth insulating film and the floating gate electrode. As the fifth insulating film 321, a silicon oxide film or silicon oxynitride (SiON (O> N)) having a thickness of 20 to 50 nm is formed by a plasma CVD method.

  Next, a first conductive film 322 is formed. Here, a 400-nm-thick tungsten film is formed as the first conductive film 322 by a sputtering method. Next, mask patterns 323 to 325 are formed over the first to third semiconductor regions 303 to 305 by a photolithography process.

  Next, as illustrated in FIG. 3D, the first conductive film 322 is etched using the mask patterns 323 to 325 to form gate electrodes 331 to 333. The width of the gate electrode at this time is 0.2 to 1.5 nm, preferably 0.2 to 0.7 nm. Next, after removing the mask patterns 323 to 325, a mask pattern 334 is newly formed on the third semiconductor region 305.

  Next, an impurity element is added to the first semiconductor region 303 and the second semiconductor region 304 using the gate electrodes 331 and 332 as masks. Here, phosphorus (P) which is an impurity element exhibiting n-type is added to each semiconductor region, so that source and drain regions 335 to 338 exhibiting n-type are formed.

  Next, as shown in FIG. 3E, after the mask pattern 334 is removed, mask patterns 341 and 342 are formed over the first semiconductor region 303 and the second semiconductor region 304 by a photolithography process. Next, an impurity element is added to the third semiconductor region 305 using the gate electrode 325 as a mask. Here, boron (B) which is an impurity element exhibiting p-type is added to the semiconductor region, so that source and drain regions 343 and 344 exhibiting p-type are formed. Next, after removing the mask patterns 341 and 342, the impurity elements in the source region and the drain region are activated by heating. After that, an insulating film containing hydrogen may be formed over the fifth insulating film 321 and heated to hydrogenate the surface of the semiconductor region.

  Next, as illustrated in FIG. 3F, a sixth insulating film functioning as an interlayer insulating film is formed over the fifth insulating film 321. Here, a siloxane-based resin is applied and baked to form a sixth insulating film. Next, the sixth insulating film, the fifth insulating film, the third insulating film, and the second insulating film are etched to form contact holes, and part of the source and drain regions 335 to 338, 343, and 344 are formed. Exposed. The etched sixth insulating film is referred to as a sixth insulating layer 351, the etched fifth insulating film is referred to as a fifth insulating layer 352, and the etched third insulating film third insulating layer 353. In addition, the etched second insulating film is referred to as second insulating layers 354 to 356. Next, after a titanium film, an aluminum silicon alloy film, and a titanium film are stacked by a sputtering method, source and drain electrodes 357 to 362 are formed using a photolithography process and an etching process.

  Through the above steps, the first semiconductor region 303, the second insulating layer 354 and the third insulating layer 353 functioning as a tunnel oxide film, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 352, and the gate electrode 331 are also provided. Can be formed. In addition, an n-channel TFT 372 including the second semiconductor region 304, the second insulating layer 355 functioning as a gate insulating film, the third insulating layer 353, the fifth insulating layer 352, and the gate electrode 332 may be formed. it can. In addition, a p-channel TFT 373 including the third semiconductor region 305, the second insulating layer 356 functioning as a gate insulating film, the third insulating layer 353, the fifth insulating layer 352, and the gate electrode 333 may be formed. it can. Further, a semiconductor device including the memory transistor 371 having a single drain structure, the n-channel TFT 372, and the p-channel TFT 373 can be formed over the same substrate.

  Further, this example can be used in combination with each of the first to third embodiments.

  In this embodiment, a manufacturing process of a semiconductor device having a memory transistor and a CMOS circuit on the same substrate will be described with reference to FIGS. In this embodiment, the memory transistor and the TFT have a sidewall (side wall spacer) and a low-concentration impurity region (LDD (referred to as a Light Doped Drain) region) covered with the region.

In this example, the process up to the step of forming the gate electrode is the same as that of Example 1, and the subsequent processes will be described. As shown in FIG. 3D, gate electrodes 331 to 333 of the memory transistor, the n-channel TFT, and the p-channel TFT are formed according to the steps of the first embodiment. Next, as shown in FIG. 4A, phosphorus (P), which is an n-type impurity element, is formed in the semiconductor regions of the memory transistor and the n-channel TFT (the first semiconductor region 303 and the second semiconductor region 304). First low-concentration impurity regions (hereinafter referred to as first n-type impurity regions) 401 to 404 exhibiting n-type are formed. Next, boron (B), which is an impurity element exhibiting p-type, is added to the semiconductor region of the p-channel TFT (third semiconductor region 305), and a first low-concentration impurity region (hereinafter referred to as p-type) is formed. 405 and 406 are formed.

  Next, a sixth insulating film 410 is formed over the gate electrodes 331 to 333 and the fifth insulating film 321. As the sixth insulating film, a silicon oxide film is formed by a CVD method.

  Next, the sixth insulating film 410 is anisotropically etched by RIE (Reactive Ion Etching) to form sidewalls (side wall spacers) 411 to 413 as shown in FIG. To do. At this time, part or all of the second to fifth insulating films are also etched by the material of the insulating film. Here, the first to fourth semiconductor regions function as etching stoppers, and the second to fifth insulating films are etched. Here, the etched second insulating films 407 to 409 are used as second insulating layers 416a to 416c, the etched third insulating film 321 is used as third insulating layers 415a to 415c, and the etched fifth insulating film 410 is used. Respectively shown as second insulating layers 414a to 414c.

  Next, as shown in FIG. 4C, a mask pattern 421 that covers a third semiconductor region 305 that is a semiconductor region of a p-channel TFT to be formed later is formed by a photolithography process. Next, phosphorus (P) which is an impurity element exhibiting n-type is added to the first semiconductor region 303 and the second semiconductor region 304, and high-concentration impurity regions (source and drain regions) 422 to 425 exhibiting n-type are added. Form. At this time, n-type first low-concentration impurity regions (hereinafter referred to as second n-type impurity regions (LDD regions)) 426 to 429 covered with the sidewalls are also formed. At this time, the width of the second n-type impurity regions 426 to 429 is preferably 0.01 to 0.3 μm. Thereafter, the mask pattern 421 is removed. Note that the second n-type impurity region is a low-concentration impurity region.

  Next, as shown in FIG. 4D, mask patterns 431 and 432 covering the first semiconductor region 303 and the second semiconductor region 304 are formed by a photolithography process. Next, boron (B) which is an impurity element exhibiting p-type is added to the semiconductor region in the third semiconductor region 305 to form high-concentration impurity regions (source region and drain region) 422 to 425 exhibiting p-type. . At this time, first p-type impurity regions (hereinafter referred to as second p-type impurity regions (LDD regions)) 428 and 429 covered with the sidewalls are also formed. At this time, the width of the second p-type impurity regions 428 and 429 is preferably 0.01 to 0.3 μm. Next, after removing the mask patterns 431 and 432, the impurity elements are activated by heating.

  Next, after forming a seventh insulating film functioning as an interlayer insulating film, the seventh insulating film is etched to form contact holes and source and drain regions 422 to 425 as in Example 1. 433 and 434 are partially exposed. The seventh insulating film is formed by the same material and method as the sixth insulating film of Example 1. The etched seventh insulating film is referred to as a seventh insulating layer 451. Thereafter, the source and drain electrodes 357 to 362 are formed as in the first embodiment.

  Through the above steps, the first semiconductor region 303, the second insulating layer 416a and the third insulating layer 415a functioning as a tunnel oxide film, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 414a, the gate electrode 331, and the side A memory transistor 441 having a wall 411 can be formed.

In addition, an n-channel TFT 429 including the second semiconductor region 304, the second insulating layer 416 b functioning as a gate insulating film, the third insulating layer 415 b, the fifth insulating layer 414 b, the gate electrode 332, and the sidewall 412 is provided. Can be formed.

Further, a p-channel TFT 443 including the third semiconductor region 305, the second insulating layer 416 c functioning as a gate insulating film, the third insulating layer 415 c, the fifth insulating layer 414 c, the gate electrode 333, and the sidewall 413 is provided. Can be formed. Further, a semiconductor device including the memory transistor 441, the n-channel TFT 442, and the p-channel TFT 443 over the same substrate can be formed.

In addition, since the memory transistor and the TFT formed in this embodiment have a sidewall structure, an LDD region can be formed even in a memory transistor and a TFT having a submicron structure. In addition, since the LDD region is provided, there is an effect of relaxing an electric field in the vicinity of the drain to prevent deterioration due to hot carrier injection and an effect of reducing off-current. As a result, a highly reliable semiconductor device can be manufactured.

    Further, this example can be used in combination with each of Embodiment Modes 1 to 3 and Example 1.

In this embodiment, a manufacturing process of a semiconductor device including a memory transistor and a CMOS circuit over the same substrate will be described with reference to FIGS. In this embodiment, the memory transistor and the TFT have a silicide structure.

  In this embodiment, the steps up to the step of forming the source region and the drain region are the same as those in Embodiment 2, and therefore the subsequent steps will be described. As shown in FIG. 5A according to the second embodiment, after forming sidewalls 411 to 413, first insulating layers 416a to 416c, second insulating layers 415a to 415c, and fifth insulating layers 414a to 414c, the source Region and drain regions 422-425, 433, 434 are formed. Thereafter, the mask patterns 431 and 432 are removed.

  Next, as illustrated in FIG. 5B, a conductive film 510 is formed. As a material of the conductive film 510, titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), tantalum (Ta), vanadium ( A film containing V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), or the like is formed. Here, a titanium film is formed by a sputtering method.

  Next, as illustrated in FIG. 5C, silicides 521 to 526 are formed by reacting the silicon in the exposed source and drain regions with the conductive film by heat treatment, a GRTA method, an LRTA method, or the like. . Thereafter, the conductive film 510 that has not reacted with silicon is removed.

  Next, after forming a seventh insulating film functioning as an interlayer insulating film as in the second embodiment, a part of the seventh insulating film is etched to form a contact hole, and part of the silicides 521 to 526 is formed. To expose. Next, source and drain electrodes 357 to 362 are formed as in the third embodiment.

Through the above steps, the first semiconductor region 303, the second insulating layer 416a and the third insulating layer 415a functioning as a tunnel oxide film, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 414a, the gate electrode 331, and the silicide A memory transistor 531 having 521 and 522 can be formed.

The n-channel TFT 532 includes the second semiconductor region 304, the second insulating layer 416 b functioning as a gate insulating film, the third insulating layer 415 b, the fifth insulating layer 414 b, the gate electrode 332, and the silicides 523 and 524. Can be formed.

The p-channel TFT 533 includes the third semiconductor region 305, the second insulating layer 416 c functioning as a gate insulating film, the third insulating layer 415 c, the fifth insulating layer 414 c, the gate electrode 333, and silicides 525 and 526. Can be formed. Furthermore, a semiconductor device including the memory transistor 531 having a silicide structure, the n-channel TFT 532, and the p-channel TFT 533 over the same substrate can be efficiently formed.

Since the memory transistor and the TFT formed in this embodiment have a silicide structure, the resistance of the source region and the drain region can be reduced, and the speed of the semiconductor device can be increased. Further, since operation at a low voltage is possible, power consumption can be reduced.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 and 2.

  In this embodiment, a manufacturing process of a semiconductor device having a memory transistor and a CMOS circuit on the same substrate will be described with reference to FIGS. In this embodiment, the memory transistor and the TFT have a low concentration impurity region (hereinafter referred to as a GOLD region or a Lov region) covered with a gate electrode.

  In this example, the process up to the step of forming the insulating layer 313 having the floating gate electrode is the same as that of Example 1, and therefore the subsequent processes will be described. As shown in FIG. 3C, an insulating layer 313 including a floating gate electrode and a fifth insulating film 321 are formed. Next, as illustrated in FIG. 6A, a first conductive film 601 and a second conductive film 602 are formed over the insulating layer 313 including the floating gate electrode and the fifth insulating film 321. Here, a tantalum nitride film with a thickness of 30 nm is formed as the first conductive film 601, and a tungsten film with a thickness of 370 nm is formed as the second conductive film.

  Next, mask patterns 603 to 605 are formed on the second conductive film 602 by a photolithography process. Here, the mask patterns 603 to 605 form a mask pattern having a tapered portion (inclined portion) of 40 to 80 degrees, preferably 60 to 70 degrees in a region in contact with the second conductive film 602. The angle of the tapered portion (taper angle) is defined as the angle formed by the substrate surface (horizontal plane) and the inclined portion of the tapered portion. Here, when a mask pattern having a tapered portion is formed, a reduction projection exposure apparatus (commonly referred to as a stepper) or a mirror projection exposure apparatus (commonly referred to as MPA) is used as an exposure apparatus for exposing a resist. Is preferably used. When a reduction projection exposure apparatus is used, there is a case where a mask pattern having no tapered portion and a side surface is vertically formed is formed. In this case, the tapered portion is formed on the side surface by heating the resist at 160 to 200 degrees. can do. Note that as long as it is possible to form a mask pattern having a tapered portion on a side surface, the exposure apparatus is not limited to these exposure apparatuses, and a known exposure apparatus can be used freely.

  Next, as shown in FIG. 6B, the first conductive film 601 and the second conductive film 602 are etched under the first condition, and the first conductive layers 611, 613, and 615 having tapered portions and the second conductive film are etched. Layers 612, 614, 616 are formed. During this etching process, the mask patterns 603 to 605 are also etched to form narrow mask patterns 617 to 619. The first conductive layers 611, 613, and 615 are conductive layers in which the first conductive film 601 is etched, and the second conductive layers 612, 614, and 616 are conductive layers in which the second conductive film 602 is etched. Here, the first condition is an etching condition in which the selection ratio between the first conductive film and the second conductive film is substantially equal. In this embodiment, the first conductive film and the second conductive film are etched by an ICP (Inductively Coupled Plasma) etching method. As a result, the first conductive layers 611, 613, and 615, the second conductive layers 612, 614, and 616, and the mask patterns 617 to 619 having substantially the same taper angle are formed.

  Next, as shown in FIG. 6C, the second conductive layers 612, 614, and 616 are etched under the second condition to form third conductive layers 621 to 623. Here, the second condition is a condition for selectively etching the second conductive layer. As such a condition, the second conductive layer is selectively etched while the mask patterns 617 to 619 are retracted. In this embodiment, the second conductive layers 612, 614, and 616 are etched by an ICP (Inductively Coupled Plasma) etching method. As a result, it is possible to form the third conductive layers 621 to 623 having an angle of the tapered portion larger than that of the second conductive layer and narrower than that of the first conductive layer. At this time, in FIG. 6, the mask patterns retreated by the second condition are 624 to 626.

  Through the above steps, the first conductive layer 611 and the third conductive layer 621 function as gate electrodes of memory transistors to be formed later. The first conductive layer 613 and the third conductive layer 622 function as gate electrodes of n-channel TFTs to be formed later. The first conductive layer 615 and the third conductive layer 623 function as gate electrodes of p-channel TFTs to be formed later.

  Next, phosphorus (P) which is an impurity element exhibiting n-type is added to the first semiconductor region 303 and the second semiconductor region 304, and high-concentration impurity regions (source and drain regions) 631 to 634 exhibiting n-type are formed. At the same time, low-concentration impurity regions (GOLD regions) 637 to 640 that are covered with the gate electrode and exhibit n-type are formed. Here, the region of the first conductive layers 611 and 613 is thinner than the third conductive layer 621. Therefore, a low-concentration impurity element is added to the semiconductor regions 303 and 304 that are not covered by the third conductive layers 621 and 622 but are covered by the first conductive layers 611 and 613.

  Next, boron (B) which is an impurity element exhibiting p-type is added to the third semiconductor region 305 to form high-concentration impurity regions (source region and drain region) 635 and 636 exhibiting p-type, and the gate electrode Low concentration impurity regions (GOLD regions) 641 and 642 covered with are formed. Here, similarly, the region of the first conductive layer 615 is thinner than the third conductive layer 623. Therefore, a low-concentration impurity element is added to the semiconductor region 305 that is not covered with the third conductive layer 623 but is covered with the first conductive layer 615.

  Next, after removing the mask patterns 624 to 626, the impurity elements are activated by heating. Next, a sixth insulating film functioning as an interlayer insulating film is formed by a process similar to that in Example 1, and then contact holes are formed and part of the source and drain regions 631 to 636 are exposed. Next, source and drain electrodes 357 to 362 are formed.

Through the above steps, the first semiconductor region 303 having the GOLD regions 637 and 638, the source region and the drain regions 631 and 632, the second insulating layer 354 and the third insulating layer 353 functioning as a tunnel oxide film, and the floating gate electrode are provided. A memory transistor 651 including the insulating layer 313, the fifth insulating layer 352, and the first conductive layer 611 and the third conductive layer 621 which function as gate electrodes can be formed.

In addition, the second semiconductor region 304 having GOLD regions 639 and 640, source and drain regions 633 and 634, a second insulating layer 355 functioning as a gate insulating film, a third insulating layer 353, a fifth insulating layer 352, and An n-channel TFT 652 including the first conductive layer 613 and the third conductive layer 622 that function as gate electrodes can be formed.

Further, the third semiconductor region 305 having GOLD regions 641 and 642, source and drain regions 635 and 636, a second insulating layer 356 functioning as a gate insulating film, a third insulating layer 353, a fifth insulating layer 352, and A p-channel TFT 653 including the first conductive layer 613 and the third conductive layer 623 functioning as a gate electrode can be formed. Further, a semiconductor device including the memory transistor 651 having the GOLD region, the n-channel TFT 652, and the p-channel TFT 653 over the same substrate can be formed.

In addition, since the memory transistor and the TFT of this embodiment have the GOLD region, it is possible to relax the electric field in the vicinity of the drain and suppress deterioration of on-current due to hot carriers. As a result, a semiconductor device capable of high speed operation can be formed.

Note that a semiconductor device having the same effect can be manufactured by performing side etching on the second conductive layer and forming a memory transistor and a TFT having a GOLD region in place of the gate electrode manufacturing process of this embodiment. can do.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 3.

In this embodiment, a method for manufacturing a semiconductor device including a TFT capable of high-speed operation and a TFT having high withstand voltage characteristics in addition to a memory transistor will be described with reference to FIGS.

  In this embodiment, the process up to the step of forming the insulating layer 313 having the floating gate electrode is the same as that of the first embodiment. As shown in FIG. 7A, the first semiconductor region 701, the second semiconductor region 702, the third semiconductor region 703, the fourth semiconductor region 704, and the fifth semiconductor are formed on the first insulating film 301 as in the embodiment. Region 705 is formed. The first semiconductor region 701 is an active region of a later memory transistor, the second semiconductor region 702 is an active region of an n-channel TFT capable of later high-speed operation, and the third semiconductor region 703 is capable of later high-speed operation. The active region of the p-channel TFT, the fourth semiconductor region 704 is an active region of an n-channel TFT having a high breakdown voltage characteristic later, and the fifth semiconductor region 705 is an active region of a p-channel TFT having a subsequent high breakdown voltage characteristic. Function.

  Next, as in the first embodiment, second insulating films 706 to 710 are formed on the surfaces of the first semiconductor region to the fifth semiconductor region, respectively. The second insulating films 706 to 710 are formed by the same material and method as the second insulating films 306 to 309 of the first embodiment. Next, a third insulating film 306 is formed. Next, silicon fine particles 310 and a fourth insulating film 311 are formed as dispersed particles on the third insulating film 306. Next, a mask pattern 312 is formed on the first semiconductor region 701 by a photolithography process.

  Next, as shown in FIG. 7B, the fourth insulating film 311 and part of the silicon fine particles 310 are etched using the mask pattern 312 to form an insulating layer 313 having a floating gate electrode. Next, after removing the mask pattern 312, a fifth insulating film 711 is formed. Here, the fifth insulating film 711 is formed using the same material and method as the fifth insulating film 321 of the first embodiment. Next, mask patterns 712 and 713 are formed on the first semiconductor region 701, the fourth semiconductor region 704, and the fifth semiconductor region 705 by a photolithography process.

  Next, as shown in FIG. 7C, the fifth insulating film 711 in the region not covered with the mask patterns 712 and 713 is etched. At this time, the fifth insulating film is etched under an etching condition in which the selection ratio of the fifth insulating film 711 is higher than that of the fourth insulating film 311. As a result, the fifth insulating film on the second semiconductor region 702 and the third semiconductor region 703 is etched. Further, the etched fifth insulating film 721 remains over the first semiconductor region 701, the fourth semiconductor region 704, and the fifth semiconductor region 705. As a result, the film thickness of the gate insulating film of the TFT capable of high speed operation later is 1 to 10 nm, preferably 2 to 7 nm. Thereafter, the mask patterns 712 and 713 are removed.

  Next, a first conductive film 722 is formed over the etched fifth insulating film 721 and the exposed fourth insulating film 311. The first conductive film 722 is formed using a material and a method similar to those of the first conductive film 322 of Embodiment 1 as appropriate.

  Next, mask patterns 723 to 727 are formed over the first conductive film 722 by a photolithography process.

  Next, as shown in FIG. 7D, the first conductive layer is etched using mask patterns 723 to 727 to form gate electrodes 731 to 735. Next, as in Example 1, phosphorus (P), which is an n-type impurity element, is added to the first semiconductor region 701, the second semiconductor region 702, and the fourth semiconductor region 704, and an n-type source is obtained. Regions and drain regions 736 to 741 are formed. Further, boron (B) which is an impurity element exhibiting p-type is added to the third semiconductor region 703 and the fifth semiconductor region 705, so that source and drain regions 742 to 745 exhibiting p-type are formed. Next, after removing the mask patterns 723 to 727, the impurity elements are activated by heating. Next, after forming a sixth insulating film functioning as an interlayer insulating film, a contact hole is formed in the same manner as in Example 1, and a part of the source region and the drain region is exposed.

  Next, a part of each of the sixth insulating film to the second insulating film is etched to form a contact hole and expose a part of the source region and the drain region. Note that the etched sixth insulating film is the sixth insulating layer 746, the fifth insulating film is the fifth insulating layer 747, the third insulating film is the third insulating layer 748, and the second insulating film is the second insulating layer 749˜. 753. Next, source and drain electrodes 754 to 763 are formed.

Through the above steps, the first semiconductor region 701, the second insulating layer 749 and the third insulating layer 748 functioning as a tunnel oxide film, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 747, and the gate electrode 731 are provided. A memory transistor 771 can be formed.

In addition, an n-channel TFT 772 including the second semiconductor region 702, the second insulating layer 750 and the third insulating layer 748 functioning as a gate insulating film, and the gate electrode 732 that can operate at high speed can be formed.

In addition, a p-channel TFT 773 that can operate at high speed, which includes the third semiconductor region 703, the second insulating layer 751 and the third insulating layer 748 functioning as a gate insulating film, and the gate electrode 733 can be formed.

In addition, an n-channel TFT 774 having high breakdown voltage characteristics including the fourth semiconductor region 704, the second insulating layer 752 functioning as a gate insulating film, the third insulating layer 748, the fifth insulating layer 747, and the gate electrode 734 is provided. Can be formed.

In addition, a p-channel TFT 775 having high breakdown voltage characteristics including a fifth semiconductor region 705, a second insulating film 753 functioning as a gate insulating film, a third insulating layer 748, a fifth insulating layer 747, and a gate electrode 735 is provided. Can be formed.

Further, a semiconductor device including a memory transistor 771, an n-channel TFT 772 and a p-channel TFT 773 capable of high-speed operation, and an n-channel TFT 774 and a p-channel TFT 775 having high breakdown voltage characteristics over the same substrate is formed. Can do.

In other words, emphasis is placed on high breakdown voltage characteristics of memory transistors, TFTs such as CPU, DRAM, image processing circuit, audio processing circuit, etc., which are important for high-speed operation, and buffer circuits, shift register circuits, level shifter circuits, sampling circuits, etc. It is possible to form a driving circuit and the like on the same substrate. For this reason, semiconductor devices having elements having various functions and structures, such as a system LSI, can be manufactured on the same substrate.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 4.

In this embodiment, a method for manufacturing a semiconductor device with low power consumption will be described with reference to FIGS. FIG. 14 is a perspective view of the substrate of this embodiment. The memory transistor (AB), CMOS circuit portion (CD), and n-channel TFT (E) having a low-concentration p-type impurity region are shown in FIG. A cross-sectional structure corresponding to -F) is schematically shown in FIGS. In this embodiment, a region where the LDD region overlaps with the gate electrode through the gate insulating film is referred to as a Lov region, and a region where the LDD region does not overlap with the gate electrode through the gate insulating film is referred to as a Loff region.

As shown in FIG. 8A, a first insulating film 301 is formed over a glass substrate 300. Next, an amorphous silicon film 801 is formed over the first insulating film 301. Next, the amorphous silicon film 801 is irradiated with laser light 802 to form a crystalline silicon film 803. Here, as shown in FIG. 14A, the amorphous silicon film 801 is irradiated with laser light having a pulsed laser light with an oscillation frequency of 80 MHz as the laser light 802 and directed in a scanning direction 804 as indicated by an arrow. A crystalline silicon film 803 having crystal grains grown continuously is formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film in which there are almost no crystal grain boundaries that hinder the movement of TFT carriers.

Next, as shown in FIG. 8B, a mask pattern is formed on the crystalline silicon film by a photolithography process, and a part of the crystalline silicon film is etched using the mask pattern to form a first semiconductor region. 811, a second semiconductor region 812, a third semiconductor region 813, and a fourth semiconductor region 814 are formed. Note that the first to fourth semiconductor regions are etched so that a memory transistor and a TFT channel region which will be formed later are parallel to the scanning direction 804 of the laser light 802.

FIG. 14B is an enlarged view of the first to fourth semiconductor regions formed using part of the crystalline silicon film 803. Channel regions 811a to 814a of the first to fourth semiconductor regions 811 to 814 are parallel to the laser beam scanning direction 804, respectively. The first semiconductor region 811 is an active region of a memory transistor 896a formed later, the second semiconductor region 812 is an active region of a p-channel TFT 896b formed later, and a third semiconductor region 813 is an n-channel TFT 896c formed later. The active region, the fourth semiconductor region 814 functions as an active region of an n-channel TFT 896d having a low concentration p-type impurity region.

Next, as shown in FIG. 8C, the surfaces of the first semiconductor region to the fourth semiconductor region are oxidized to form second insulating films 815 to 818, and the first insulating film 301 and the second insulating film A third insulating film 309 is formed over 815 to 818. The second insulating films 815 to 818 can be formed using the same material and method as the second insulating films 306 to 308 of Example 1.

Next, an insulating layer 313 having a floating gate electrode is formed on the third insulating film 309 by the same process as in the first embodiment. Next, a fourth insulating film 321, a first conductive film 819, and a second conductive film 820 are stacked over the third insulating film 309 and the insulating layer 313 having a floating gate electrode. Next, mask patterns 821 to 824 are formed by a photolithography process. Here, a tantalum nitride film with a thickness of 30 nm is formed as the first conductive film 819, and a tungsten film with a thickness of 370 nm is formed as the second conductive film 820.

  Next, as shown in FIG. 8D, the second conductive film 820 is etched using mask patterns 821 to 824 to form first conductive layers 831 to 834. At this time, it is preferable to etch the second conductive film under a condition where the selection ratio of the second conductive film 820 is higher than that of the first conductive film 819. By this step, it is possible to selectively etch only the second conductive film.

Next, a mask pattern 835 that covers the first semiconductor region 811 to the third semiconductor region 813 is formed by a photolithography process. Next, an impurity element 836 imparting p-type conductivity is added. Here, an impurity element imparting p-type conductivity is added at 0 to 60 degrees, preferably 5 to 45 degrees with respect to the surface of each semiconductor region, so that first p-type impurity regions 837 and 838 are formed. Note that the first p-type impurity region 838 does not enter under the gate electrode because the impurity element is shielded by the gate electrode and added to the semiconductor region. Here, boron (B) is added so that the impurity element is contained in the first p-type impurity region at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ . Further, boron (B) may be added so that the impurity element is contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Note that the channel regions of the semiconductor region are aligned in one direction as shown in FIG. Therefore, the impurity element can be added to the semiconductor region covered with the gate electrode by adding the impurity element obliquely with respect to the surface of the semiconductor region as indicated by an arrow without rotating the substrate. Further, when an impurity element is added from one of the source region or the drain region to the other, the impurity is added to the semiconductor region that is on one side of the source region or the drain region and is covered with the gate electrode. In other words, since the substrate does not need to be rotated, the impurity element can be added to one of the semiconductor regions covered with the gate electrode even if the substrate 800 is a large-area substrate.

Here, the channel length of the TFT L, the channel length direction of the Lov region 2602a for the length L _OV be described. Further, in this embodiment, the length L _OV of the channel length L, the channel length direction of the Lov region 2602a of the TFT, the length and defining shown in Figure 21 (A). Basically, the equation is established width = L + L _OV gate electrode 2600 as shown in FIG. 21 (A). In the case where the impurity element doped by relatively high-temperature heat treatment is diffused after the substrate is obliquely doped, the boundary of the channel region 2603 becomes difficult to be clarified, but FIG. Identified as a structural diagram

Further, depending on doping conditions, the peak of the concentration profile 2604 may be located above the channel region 2606 or in the gate insulating film 2601 as shown by a dotted line in FIG. In FIG. 21 (B), the channel length L of the Lov region 2605a of the length L _OV and the channel region 2606 overlapping with the gate electrode 2600 is the same as FIG. 21 (A).

Further, depending on doping conditions, as indicated by a dotted line in FIG. 21C, the peak of the concentration profile 2607 may be located in the base insulating film or the substrate in the semiconductor region. In this case, the formula of the width of the gate electrode 2600 = L + _LOV does not hold. Since the channel is formed at the interface between the channel region 2609 and the gate insulating film 2601, the channel length L becomes long as shown in FIG. 21 (C), Lov region 2608a which overlaps with the gate electrode 2600, a length L _OV Point to the longest point. The structure shown in FIG. 21C cannot be manufactured unless the TFT has a long channel length because when the semiconductor substrate is used, the concentration profiles overlap each other under the gate or are too close to each other. It is a configuration.

  Next, in FIG. 21A, the impurity element concentration distribution in the horizontal and vertical directions of the Lov region 2602a will be described with reference to FIG. FIG. 22A is an enlarged view of one Lov region 2602a in FIG. FIG. 22B shows the concentration distribution of the impurity element in the depth direction (YY ′) in the Lov region of FIG. 22A, and the same lateral direction (XX ′: depth direction). FIG. 22C shows the distribution of the impurity concentration in the direction perpendicular to FIG.

As shown in FIG. 22B, in the Lov region, an impurity element concentration gradient is generated between the substrate side and the gate electrode side.

  Further, as shown in FIG. 22C, an impurity element concentration gradient is generated in the Lov region.

  Note that the concentration gradients in the depth direction and the lateral direction have various gradients as shown in FIGS. 21B and 21C.

Next, as shown in FIG. 9A, a mask pattern 849 is formed over the second semiconductor region 812 by a photolithography process. Next, an n-type impurity element 841 is added to each of the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 to form first n-type impurity regions 842 to 847. Here, phosphorus (P) is added to the first n-type impurity regions 842 to 847 so that an n-type impurity element of typically 1 × 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ is included. Here, the impurity element is added perpendicular to the surface of each semiconductor region.

Here, since phosphorus is added in a self-aligned manner using the gate electrode, a region overlapping with the first conductive layer 834 in the first p-type impurity region 837 remains as a p-type impurity region. This region is a second p-type impurity region (Lov region) 848. In addition, since phosphorus is already added in the first n-type impurity regions 846 and 847, phosphorus having a concentration higher than the boron concentration of the first p-type impurity regions 837 and 838 is used to invert from the p-type to the n-type. Added. Thereafter, the mask pattern 849 is removed.

Next, as shown in FIG. 9B, side walls (side wall spacers) 851 to 854 are formed on the side walls of the first conductive layers 831 to 834 in the same manner as in the second embodiment. In the sidewall, since the insulating film on the upper surface of the gate electrode functions as an etching stopper when the first conductive film 819 is etched later, it is possible to suppress the film loss of the gate electrode. Next, the second conductive layers 855 to 858 are formed by etching the first conductive film 819 using the sidewalls and the gate electrode as a mask.

Next, a mask pattern 859 is formed over the second semiconductor region 812 by a photolithography process. Next, an impurity element exhibiting n-type is added to the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 using the sidewalls and the first conductive layers 831 to 834 as masks to form the second n-type. Impurity regions 861 to 866 are formed. Here, boron (B) is added so that the impurity element is contained in the second n-type impurity region at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ . Note that the second n-type impurity regions 861 to 866 are high-concentration impurity regions and function as a source region and a drain region. The first n-type impurity regions covered with the second conductive layers 855, 857, and 858 and the sidewalls 851, 853, and 854 are denoted as third n-type impurity regions (Lov regions) 867 to 872. The third n-type impurity regions (Lov regions) 867 to 872 are low-concentration impurity regions. Since the third n-type impurity regions 867 to 872 are covered with the second conductive layers 855, 857, and 858 that function as gate electrodes, the electric field in the vicinity of the drain is relaxed and deterioration of on-current due to hot carriers is suppressed. Is possible. As a result, a semiconductor device capable of high speed operation can be formed.

Next, as illustrated in FIG. 9C, after removing the mask pattern 859, mask patterns 875 to 877 that newly cover the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 are formed. To do. Next, an impurity element imparting p-type conductivity is added at a high concentration, so that third p-type impurity regions 878 and 879 are formed. Here, the impurity element is added so that the ^third p-type impurity regions 878 and 879 include a p-type impurity element having a concentration of 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ³ . The third p-type impurity regions 878 and 879 are high concentration impurity regions.

Next, as illustrated in FIG. 10A, after the sidewall 852 is removed to expose a part of the second conductive layer 856, the exposed portion of the second conductive layer 856 is etched. As a result, a third conductive layer 881 having substantially the same width as the first conductive layer 832 is formed. In this etching step, when the second, third, and fifth insulating films are formed of the same material as the sidewall 852, some or all of these are also etched. Here, the second, third, and fifth insulating films are etched with the semiconductor region functioning as an etching stopper. Here, the etched second insulating film 816 is referred to as a second insulating layer 816a, the etched third insulating film 309 is referred to as a third insulating layer 309a, and the etched fifth insulating film 321 is referred to as a fifth insulating layer 321a.

Next, the p-type impurity element is added to the second semiconductor region 812 at a low concentration to form fourth p-type impurity regions (Loff regions) 882 and 883. Here, boron (B) is added so that the fourth p-type impurity region contains the impurity element at a concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ³ . The fourth p-type impurity regions (Loff regions) 882 and 883 are low concentration impurity regions. Since the fourth p-type impurity regions 882 and 883 are not covered with the gate electrode, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and to reduce the off current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

Next, as shown in FIG. 10B, after removing the mask patterns 875 to 877, the impurity elements are activated by heating. Next, a sixth insulating film functioning as an interlayer insulating film is formed by a process similar to that of the first embodiment. Next, a part of each of the sixth insulating film, the etched fifth insulating film, the third insulating film, and the second insulating film is etched to form contact holes and to function as a source region and a drain region. The 2n-type impurity regions 861 to 866 and a part of the third p-type impurity regions 878 and 879 functioning as a source region and a drain region are exposed. In FIG. 10, the etched sixth insulating film is the sixth insulating layer 885, the fifth insulating film is the fifth insulating layer 886, the third insulating film is the third insulating layer 887, and the second insulating film is the second insulating film. Insulating layers 805, 807, and 808 are shown. Next, source and drain electrodes 888 to 895 are formed.

Here, FIG. 28 shows the width of the gate electrode of the n-channel TFT having the second p-type impurity region, the width of the second p-type impurity region, and the Lov region.

  FIG. 28 shows an n-channel TFT 896d having a second p-type impurity region. The width D1 of the gate electrode is 200 to 1500 nm, preferably 200 to 700 nm. The width D2 of the second p-type impurity region is 5 to 200 nm. The width D3 of the third n-type impurity region is 10 to 200 nm. Since the short channel structure is obtained by setting the width of the gate electrode in the above range, high-speed operation is possible. In addition, by making the widths of the second p-type impurity region and the third n-type impurity region within the above range, an n-channel TFT capable of shifting the threshold voltage and reducing the cut-off current is manufactured. Is possible.

  Further, each of the memory transistor 896a, the p-channel TFT 896b, and the n-channel TFT 896c preferably has the same gate electrode width and the third n-type impurity region as the n-channel TFT 896d.

In addition, simulation results of current-voltage (IV) characteristics of an n-channel TFT having a second p-type impurity region will be described with reference to FIGS. 23A assumes a model diagram of the TFT shown in FIG. 23B, and is a standard n-channel TFT and an n provided with a second p-type impurity region (hereinafter referred to as p ⁻ ) on the drain side. The IV characteristics of the channel TFT are shown.

FIG. 23B shows the structure of each TFT. Structure A is a standard n-channel TFT having Loff (denoted as n ⁻ ), structure B is an n-channel TFT having a p ⁻ width of 100 nm, and structure C is an n-channel TFT having a p ⁻ width of 300 nm. TFT. Further, the L / W of each TFT is 1000/20000 nm, the width of the Loff region is 300 nm, the thickness of the gate insulating film is 20 nm, and the impurity concentration of the source region and the drain region (shown as n ⁺ ) is 1 × 10 ^20. The IV characteristics were simulated by setting the impurity concentration of cm ⁻³ , the Loff region to 1 × 10 ¹⁸ cm ⁻³ , ^and the impurity concentration of p ⁻ to 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 23A, the solid line indicates the IV characteristics of structure A, and the broken lines indicate the IV characteristics of structures B and C having p ^−, respectively. It can be seen that having p ⁻ shifts the threshold voltage of the TFT to the positive side. It can also be seen that the shift amount of the threshold voltage increases as the width of p ⁻ increases (that is, in the structure C than in the structure B).

FIG. 24 shows a simulation result of IV characteristics of a TFT in which p ⁻ is provided on the source side. 24A assumes a model diagram of the TFT shown in FIG. 24B, and a standard n-channel TFT and a second p-type impurity region (hereinafter referred to as p ⁻ ) are provided on the source side. The IV characteristic of an n-channel TFT is shown.

FIG. 24B shows the structure of each TFT. Structure A is the same as the standard n-channel TFT shown in FIG. 23B, structure D is an n-channel TFT with a p ⁻ width of 100 nm, and structure E has a p ⁻ width of 300 nm. This is an n-channel TFT. The L / W, Loff region width, gate insulating film thickness, and n ⁺ concentration of each TFT were the same as those used in FIG.

In FIG. 24A, the solid line indicates the IV characteristics of the structure A, and the broken lines indicate the IV characteristics of the structures D and E having p ^−, respectively. It can be seen that having p ⁻ shifts the threshold voltage of the TFT to the positive side. It can also be seen that the shift amount of the threshold voltage increases as the width of p ⁻ increases (that is, in the structure E than in the structure D). Further, it can be seen that the cut-off current (Icut) is lower than that of the standard n-channel TFT. The cut-off current (Icut) is a value of the drain current Id when the gate voltage Vg is 0 V in the Id-Vg characteristic.

  As described above, by using an n-channel TFT covered with a gate electrode and having a low-concentration p-type impurity region in one of a channel region and a source region or a drain region, the threshold voltage is shifted and the cut-off current is reduced. Reduce. Conventionally, TFTs such as CPUs, DRAMs, image processing circuits, and audio processing circuits that require high-speed operation have a short channel structure. However, if the channel length is short, the threshold voltage decreases and the cut-off current increases. There was a problem to do. However, the TFT of this embodiment can reduce the cut-off current with a short channel structure. By using such TFTs in key areas, the power consumption of the entire semiconductor device can be reduced. For example, it is possible to reduce power consumption during standby by connecting such TFT between the logic TFT and the power supply and turning it on during operation and turning it off during non-operation. It becomes. Alternatively, the power consumption of the entire semiconductor device can be reduced by forming a circuit with the TFT in a region where high-speed operation is not particularly required.

Further, in FIG. 8D, the mask pattern 835 is not formed, and the first semiconductor region 811 to the fourth semiconductor region 814 are similarly 0 to 60 degrees with respect to the surface of each semiconductor region, preferably 5 to 5 degrees. By adding an impurity element imparting p-type at 45 degrees and forming the first low-concentration p-type impurity region, the threshold voltage of each semiconductor element can be controlled without channel doping. . In this case, since channel doping is not necessary, the number of steps can be reduced.

Note that in a p-channel TFT, when a low-concentration n-type impurity region covered with a gate electrode is formed as in the n-channel TFT, the threshold voltage shifts to the negative side. Furthermore, it is possible to reduce the cut-off current by providing it on the source side. That is, similar to an n-channel TFT, high-speed operation is possible and power consumption can be reduced.

Through the above steps, the second n-type impurity regions 861 and 862 functioning as the source region and the drain region, the third n-type impurity regions 867 and 868, the first semiconductor region 811 having the channel region, and the second function as the tunnel oxide film. A memory transistor 896a including the insulating layer 805, the third insulating layer 887, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 886, and the second conductive layer 831 and the third conductive layer 855 functioning as the gate electrode is formed. be able to.

In addition, third p-type impurity regions 878 and 879 functioning as a source region and a drain region, fourth p-type impurity regions 882 and 883 serving as Loff regions, a second semiconductor region 812 having a channel region, and a first functioning as a gate insulating film. A p-channel TFT 896b including the second insulating layer 816a, the third insulating layer 309a, the fifth insulating layer 321a, and the second conductive layer 832 and the third conductive layer 881 functioning as a gate electrode can be formed.

The high-concentration impurity regions 863 and 864, the Lov regions 869 and 870, the third semiconductor region 813 having a channel region, the second insulating layer 807 functioning as a gate insulating film, the third insulating layer 887, and the fifth insulating layer An n-channel TFT 896c including the second conductive layer 833 and the third conductive layer 857 functioning as a gate electrode can be formed.

The high concentration impurity regions 865 and 866, the Lov regions 871 and 872, the second p-type impurity region 848 having a low concentration impurity, the fourth semiconductor region 814 having a channel region, and the second insulating layer 808 functioning as a gate insulating film. In addition, an n-channel TFT 896d including the third insulating layer 887, the fifth insulating layer 886, and the second conductive layer 834 and the third conductive layer 858 functioning as a gate electrode can be formed.

Further, a semiconductor device including the memory transistor 896a, the p-channel TFT 896b, the n-channel TFT 896c, and the n-channel TFT 896d having a low-concentration p-type impurity region over the same substrate can be formed. Since the memory transistor and the TFT of the semiconductor device of this embodiment are formed in a semiconductor region having almost no crystal grain boundary in the channel direction, high speed operation is possible. In addition, since an n-channel TFT having a low-concentration p-type impurity region is provided, a semiconductor device capable of high-speed operation and reduced power consumption can be formed.

  In this embodiment, a semiconductor device having a silicide structure in the TFT shown in Embodiment 6 will be described with reference to FIGS. In the present embodiment, the steps up to forming the first conductive film and the second conductive film are the same as those in the sixth embodiment.

As shown in FIG. 11A, according to the sixth embodiment, a first conductive film 901 and a second conductive film 902 are formed on the fifth insulating film. Here, a tungsten nitride (WN) film is formed as the first conductive film 901 by a sputtering method, and a tungsten (W) film is formed as the second conductive film 902 by a similar method. Next, mask patterns 903 to 906 are formed by a photolithography process.

Next, as shown in FIG. 11B, the second conductive film 902 and the first conductive film 901 are etched using mask patterns 903 to 906 to form gate electrodes 911 to 914. The gate electrodes 911 to 914 have a stacked structure of a tungsten nitride film and a tungsten film. Next, after removing the mask patterns 903 to 906, a mask pattern 915 that covers the first semiconductor region 811 to the third semiconductor region 813 is newly formed by a photolithography process.

Next, an impurity element 916 imparting p-type conductivity is added to the fourth semiconductor region 814. Here, as in Example 6, the impurity element imparting p-type is added at 0 to 60 degrees, preferably 5 to 45 degrees with respect to the surface of the semiconductor region, and the first p-type impurity regions 917 and 918 are formed. Form. Here, boron (B) is added so that the first p-type impurity region contains the impurity element at a concentration of about 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ . Further, boron (B) may be added so that the impurity element is contained at a concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ . Note that since the impurity element is added obliquely to the semiconductor region as indicated by an arrow, the impurity element is also added to the first p-type impurity region 917 in a region covered with the gate electrode 914. On the other hand, the first p-type impurity region 918 has an impurity element added to a part of the fourth semiconductor region 814.

Next, as shown in FIG. 11C, after the mask pattern 915 is removed, a mask pattern 921 is newly formed over the second semiconductor region 812. Next, an impurity element 922 imparting n-type conductivity is added to each of the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 to form first n-type impurity regions 923 to 928. Here, phosphorus (P) is added to the first n-type impurity regions 923 to 928 so that an n-type impurity element of typically 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ is included. Here, the impurity element is added perpendicular to the surface of each semiconductor region.

  Since phosphorus is added in a self-aligned manner using the gate electrode, the region overlapping with the gate electrode 914 in the first p-type impurity region 917 remains as a p-type impurity region. This region is referred to as a second p-type impurity region 929. Further, since boron is added in the first n-type impurity region 928, phosphorus having a concentration higher than that of the first p-type impurity region 917 is added to invert from p-type to n-type. Thereafter, the mask pattern 921 is removed.

Next, as shown in FIG. 12A, low-concentration boron is added to the second semiconductor region 812 to form third p-type impurity regions 930a and 930b. Here, boron (B) is typically added so as to contain a p-type impurity element of 5 × 10 ^{18 to} 5 × 10 ¹⁹ / cm ³ .

Next, side walls (side wall spacers) 931 to 934 are formed on the side walls of the gate electrodes 911 to 914 in the same manner as in the second embodiment. At this time, the exposed portion of the fifth insulating film is also etched. Here, the etched fifth insulating film is referred to as fifth insulating layers 935 to 938. Next, the exposed portions of the third insulating film 306 and the second insulating films 815 to 818 are etched using the sidewalls 931 to 935 as masks. Here, the etched third insulating film is referred to as third insulating layers 941 to 944, and the etched second insulating film is referred to as second insulating layers 945 to 958. As a result, a part of the first semiconductor region 811 to the fourth semiconductor region 814 is exposed.

Next, as shown in FIG. 12B, a mask pattern 961 is formed over the second semiconductor region 812 by a photolithography process. Next, an n-type impurity element 960 is added to the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 using the sidewalls and the gate electrode as a mask to add second n-type impurity regions 962 to 962. 967 is formed. Here, an impurity element is added from the vertical direction as indicated by an arrow with respect to the surface of each semiconductor region. Here, typically, phosphorus (P) is added so that an n-type impurity element of 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ is included. Note that the second n-type impurity regions 962 to 967 are high-concentration impurity regions and function as a source region and a drain region. The first n-type impurity regions covered with the sidewalls 931, 933, and 934 are denoted as third n-type impurity regions (Loff regions) 968 to 973. The third n-type impurity regions 968 to 973 are low-concentration impurity regions. Since the third n-type impurity regions 968 to 973 are not covered with the gate electrodes 911, 913, and 914, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and to reduce the off current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

Next, as shown in FIG. 12C, the mask pattern 961 is removed. Next, a third conductive film 975 is formed in order to form silicide as in the third embodiment. Here, a titanium film is formed as the third conductive film 975 by a sputtering method.

  Next, as illustrated in FIG. 13A, silicide 971 to 978 are formed by reacting the exposed silicon in the source and drain regions with the conductive film by heat treatment, a GRTA method, an LRTA method, or the like. . Thereafter, the third conductive film that has not reacted with silicon is removed.

Next, as shown in FIG. 13B, mask patterns 981 and 982 that cover the first semiconductor region 811, the third semiconductor region 813, and the fourth semiconductor region 814 are formed. Next, an impurity element 983 imparting p-type conductivity is added at a high concentration to form fourth p-type impurity regions 984 and 985. Along with this step, fifth p-type impurity regions 986 and 987 are formed in the second semiconductor region covered with the sidewalls 932. Here, the impurity element is added so that the fourth p-type impurity regions 884 and 885 include a high-concentration p-type impurity element of 1 × 10 ^{20 to} 5 × 10 ²¹ atoms / cm ³ . Further, since the impurity element (boron (B)) at a low concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ atoms / cm ³ is added to the fifth p-type impurity regions 986 and 987, the low-concentration impurity region It is. Since the fifth p-type impurity regions 986 and 987 are not covered with the gate electrode, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and to reduce the cut-off current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

Next, as shown in FIG. 13C, after removing the mask patterns 981 and 982, the impurity elements are activated by heating. Next, contact holes are formed by the same process as in the sixth embodiment, and part of the second n-type impurity regions 962 to 967 and the fourth p-type impurity regions 984 and 985 functioning as a source region and a drain region are exposed. Next, source and drain electrodes 888 to 895 are formed.

Through the above steps, second n-type impurity regions 962 and 963 functioning as a source region and a drain region, third n-type impurity regions 968 and 969 which are Loff regions, a first semiconductor region 811 having a channel region, and a tunnel oxide film A memory transistor 991 including the functioning second insulating layer 945 and the third insulating layer 941, the insulating layer 313 having a floating gate electrode, the fifth insulating layer 935, and the gate electrode 911 can be formed.

In addition, fourth p-type impurity regions 984 and 985 functioning as a source region and a drain region, fifth p-type impurity regions 986 and 987 which are Loff regions, a second semiconductor region 812 having a channel region, and a first semiconductor layer functioning as a gate insulating film. A p-channel TFT 992 including the second insulating layer 946, the third insulating layer 942, the fifth insulating layer 936, and the gate electrode 912 can be formed.

The high-concentration impurity regions 964 and 965, the Loff regions 970 and 971, the third semiconductor region 813 having a channel region, the second insulating layer 947 and the third insulating layer 943 functioning as a gate insulating film, and the fifth insulating layer An n-channel TFT 993 including the gate electrode 937 and the gate electrode 913 can be formed.

The high-concentration impurity regions 966 and 967, the Loff regions 972 and 973, the low-concentration p-type impurity region 974, the fourth semiconductor region 814 having a channel region, the second insulating layer 948 and the third insulating layer functioning as a gate insulating film An n-channel TFT 994 including the 944, the fifth insulating layer 938, and the gate electrode 914 can be formed.

Further, a semiconductor device including a memory transistor 991 having a silicide structure, a p-channel TFT 992, an n-channel TFT 993, and an n-channel TFT 994 having a low-concentration p-type impurity region can be formed over the same substrate.

Furthermore, the memory transistor and TFT formed by this embodiment have a silicide structure. In addition, since the n-channel TFT having the low-concentration p-type impurity region is provided, the resistance of the source region and the drain region can be reduced, the speed can be increased, the operation at a low voltage is possible, and the consumption A semiconductor device with reduced power can be formed.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 6.

FIG. 15 shows a typical block diagram of an ID chip typified by a contactless RFID (Radio Frequency Identification) tag, a wireless tag, etc., which is a typical example of the semiconductor device of the present invention. FIG. 15 shows a configuration having a simple function of reading fixed data such as authentication data. In the figure, an ID chip 1301 includes an antenna 1302, a high-frequency circuit 1303, a power supply circuit 1304, a reset circuit 1305, a clock generation circuit 1306, a data demodulation circuit 1307, a data modulation circuit 1308, a control circuit 1309, a non-volatile memory (Nonvolatile Memory: NVM) 1310 and ROM 1311.

In this embodiment, a memory transistor constituting the present invention is used as the NVM 1310. In addition, when a transistor that operates at high speed is required as a transistor constituting the high-frequency circuit 1303, the reset circuit 1305, the clock generation circuit 1306, the data demodulation circuit 1307, the data modulation circuit 1308, the control circuit 1309, and the ROM 1311, the present invention is used. The high-speed transistor can be manufactured at the same time as the memory transistor. In the case where a transistor having high withstand voltage characteristics is required as the transistor included in the power supply circuit 1304, the transistor can be manufactured at the same time as the memory transistor by the manufacturing process of the transistor having high withstand voltage characteristics forming the present invention. As described above, an RFID tag can be efficiently manufactured on the same substrate. Further, the cost and size of the ID chip 1301 can be reduced.

Further, all the circuits shown in FIG. 15 are formed on a glass substrate, a flexible substrate, or a semiconductor substrate. The antenna 1302 may be formed on the glass substrate, a flexible substrate, or a semiconductor substrate, or may be outside the substrate and connected to a high-frequency circuit inside the substrate.

The high frequency circuit 1303 is a circuit that receives an analog signal from the antenna 1302 and outputs the analog signal received from the data modulation circuit 1308 from the antenna 1302. The power supply circuit 1304 generates a constant power supply from the received signal, the reset circuit 1305 generates a reset signal, the clock generation circuit 1306 generates a clock signal, and the data demodulation circuit 1307 extracts data from the received signal. A circuit and data modulation circuit 1308 is a circuit that generates an analog signal to be output to an antenna based on a digital signal received from a control circuit or changes antenna characteristics, and an analog unit is configured by the above circuits.

On the other hand, the control circuit 1309 receives data extracted from the received signal and performs data reading. Specifically, an address signal of the NVM 1310 or the ROM 1311 is generated, data is read, and the read data is sent to the data modulation circuit. The digital circuit is composed of the above circuits.

  This example can be used in combination with Embodiment Modes 1 to 3 and Examples 1 to 7.

  FIG. 16A is a perspective view showing one mode of an ID chip which is one of the semiconductor devices of the present invention. Reference numeral 1101 denotes a high-frequency circuit 1303, a power supply circuit 1304, a reset circuit 1305, a clock generation circuit 1306, a data demodulation circuit 1307, a data modulation circuit 1308, a control circuit 1309, a nonvolatile memory (denoted as NVM) 1310 shown in the eighth embodiment, An integrated circuit typified by a ROM 1311, 1102 corresponds to an antenna, and the antenna 1102 is connected to the integrated circuit 1101. 1103 is a substrate, and 1104 is a cover material. The integrated circuit 1101 and the antenna 1102 are formed over the substrate 1103, and the cover material 1104 overlaps the substrate 1103 so as to cover the integrated circuit 1101 and the antenna 1102. Note that the cover material 1104 is not necessarily used, but the mechanical strength of the ID chip can be increased by covering the integrated circuit 1101 and the antenna 1102 with the cover material 1104.

  FIG. 16B is a perspective view showing one mode of an IC card which is one of the semiconductor devices of the present invention. Reference numeral 1105 denotes an integrated circuit typified by the high frequency circuit 1303, the power supply circuit 1304, the reset circuit 1305, the clock generation circuit 1306, the data demodulation circuit 1307, the data modulation circuit 1308, the control circuit 1309, the NVM 1310, and the ROM 1311 shown in the eighth embodiment. Reference numeral 1106 denotes an antenna, and the antenna 1106 is connected to the integrated circuit 1105. Reference numeral 1108 denotes a substrate that functions as an inlet sheet, and reference numerals 1107 and 1109 denote cover materials. The integrated circuit 1105 and the antenna 1106 are formed over a substrate 1108, and the substrate 1108 is sandwiched between two cover materials 1107 and 1109. Note that the IC card of the present invention may have a display device connected to the integrated circuit 1105.

  Next, FIGS. 17A and 17B are cross-sectional views taken along line A-A ′ of the ID chip shown in FIG. In the ID chip, a substrate 1103, a cover material 1104, an integrated circuit 1101 formed by a peeling process, and an antenna 1102 connected thereto are bonded through adhesives 1113 and 1114.

The integrated circuit 1101 can be formed using the integrated circuit described in any of Embodiments 1 to 3 or Examples 1 to 8. Further, the semiconductor element used for the integrated circuit 1101 is not limited to this. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used in addition to the TFT.

As shown in FIG. 17A, an interlayer insulating film 1110 is formed over the TFT of the integrated circuit 1101, and a barrier film 1111 made of a silicon nitride film or the like is formed over the interlayer insulating film 1110, on which An antenna 1102 is formed.

  On the other hand, as shown in FIG. 17B, an interlayer insulating film 1110 is formed over the TFT of the integrated circuit 1101, an antenna 1102 is formed over the interlayer insulating film 1110, and a barrier film is formed over the interlayer insulating film 1110 and the antenna 1102. 1121 may be provided. By providing the barrier film, an ID chip with improved reliability can be provided without the integrated circuit 1101 being contaminated.

The antenna 1102 is preferably gold, silver, copper, aluminum, or a metal plated with them.

In this embodiment, an example in which a laminated body having an integrated circuit and an antenna formed on an interlayer insulating film of the integrated circuit is bonded with different cover materials is shown, but the present invention is not limited to this, and the antenna is formed. The cover material and the integrated circuit may be fixed with an adhesive. At this time, the integrated circuit and the antenna are connected by performing UV treatment or ultrasonic treatment using an anisotropic conductive adhesive or an anisotropic conductive film, but the present invention is not limited to this method, and various Can be used.

As the substrate 1103 and the cover material 1104, a flexible material such as plastic, organic resin, paper, fiber, or carbon graphite can be used. Using a biodegradable resin for the cover material, it is decomposed into bacteria and reduced to the soil. Furthermore, since the integrated circuit of this embodiment is formed of silicon, aluminum, oxygen, nitrogen, or the like, it is possible to form a pollution-free ID chip. Further, by using an incineration-free pollution material such as paper, fiber, carbon graphite, etc., the used ID chip can be incinerated or cut. In addition, ID chips using these materials are non-polluting because they do not generate toxic gas even when incinerated.

The integrated circuit 1101 sandwiched between the substrate 1103 and the cover material 1104 may be formed to have a thickness of 5 μm or less, preferably 0.1 μm to 3 μm. The thickness of the substrate 1103 and the cover material 1104 is preferably 10 μm to 200 μm. Furthermore, the area of the integrated circuit 1101 is 5 mm square (25 mm ² ) or less, and desirably has an area of 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ).

Since the substrate 1103 and the cover material 1104 are formed of an organic resin material, the substrate 1103 and the cover material 1104 have a strong characteristic against bending. In addition, the integrated circuit 1101 itself formed by a separation process also has a strong characteristic against bending as compared with a single crystal semiconductor. Since the integrated circuit 1101, the substrate 1103, and the cover material 1104 can be in close contact with each other so that there is no gap, the completed ID chip itself has a strong characteristic against bending. The integrated circuit 1101 surrounded by the substrate 1103 and the cover material 1104 may be arranged on the surface or inside of another solid object, or may be embedded in paper.

  This example can be freely combined with any of Embodiments 1 and 2 and Examples 1 to 8.

In this embodiment, a block diagram of one chip of a CPU which is a typical example of a semiconductor device of the present invention will be described with reference to FIG.

  First, when an operation code is input to the interface 1001, the analysis circuit 1003 (also referred to as instruction decoder) decodes the code, and a signal is input to the control signal generation circuit 1004 (CPU Timing Control). When a signal is input, a control signal is output from the control signal generation circuit 1004 to the arithmetic circuit 1009 (hereinafter referred to as ALU) and the storage circuit 1010 (hereinafter referred to as register).

  The control signal generation circuit 1004 includes an ALU controller 1005 (hereinafter referred to as ACON) that controls the ALU 1009, a circuit 1006 (hereinafter referred to as RCON) that controls the register 1010, and a timing controller 1007 (hereinafter referred to as RCON) that controls timing. TCON), and an interrupt controller 1008 (hereinafter referred to as ICON) for controlling interrupts.

  On the other hand, when an operand is input to the interface 1001, it is output to the ALU 1009 and the register 1010. Then, processing based on the control signal input from the control signal generation circuit 1004 (for example, a memory read cycle, a memory write cycle, an I / O read cycle, an I / O write cycle, or the like) is performed.

  Note that the register 1010 includes a general-purpose register, a stack pointer (SP), a program counter (PC), and the like.

  An address controller 1011 (hereinafter referred to as ADRC) outputs a 16-bit address.

  Note that the configuration of the CPU shown in this embodiment is an example of a CPU formed by using the manufacturing method of the present invention, and does not limit the configuration of the present invention. Therefore, it is possible to use a known CPU configuration other than the configuration shown in this embodiment.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 9.

  A case where the present invention is applied to a system LSI which is an example of a semiconductor device of the present invention will be described with reference to FIG.

  The system LSI is an LSI that is incorporated in a device that assumes a specific application and constitutes a system that controls the device and performs data processing. Applications are diverse and include, for example, mobile phones, PDAs, televisions, printers, FAX machines, game machines, car navigation systems, DVD players, and the like.

  FIG. 19 shows an example of a system LSI. The system LSI typically includes a CPU core 1601, a non-volatile memory (NVM) 1604, a clock controller 1603, a main memory 1602, a memory controller 1605, an interrupt controller 1606, an I / O port 1607, and the like. Of course, the system LSI shown in FIG. 16 is a simplified example, and various circuit designs are performed on an actual system LSI depending on the application.

  The memory transistor of the present invention can be used for the NVM 1604.

In addition, as a transistor constituting the CPU core 1601, the clock controller 1603, the main memory 1602, the memory controller 1605, the interrupt controller 1606, and the I / O port 1607, a transistor capable of high-speed operation constituting the present invention is similarly manufactured. Can do. Thus, various circuits can be manufactured on the same substrate.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 10.

In this embodiment, a package which is an example of a semiconductor device formed using the present invention will be described with reference to FIGS. FIG. 20A is a perspective view showing a cross-sectional structure of a package in which a chip is connected to an interposer by a wire bonding method. Reference numeral 1901 denotes an interposer, 1902 denotes a chip, and 1903 denotes a mold resin layer. The chip 1902 is mounted on the interposer 1901 with a mounting adhesive 1904.

  An interposer 1901 shown in FIG. 20A is a ball grid array type in which solder balls 1905 are provided. The solder ball 1905 is provided on the side opposite to the side where the chip 1902 of the interposer 1901 is mounted. A wiring 1906 provided in the interposer 1901 is electrically connected to the solder ball 1905 through a contact hole provided in the interposer 1901.

  In this embodiment, the wiring 1906 for electrical connection between the chip 1902 and the solder ball 1905 is provided on the surface of the interposer 1901 on which the chip is mounted. It is not limited to. For example, the wiring may be provided in multiple layers inside the interposer.

  In FIG. 20A, the chip 1902 and the wiring 1906 are electrically connected by a wire 1907. FIG. 20B is a cross-sectional view of the package illustrated in FIG. The chip 1902 is provided with the semiconductor element 1909 shown in Embodiment Modes 1 to 3 and Examples 1 to 7, and the pad 1908 is provided on the opposite side of the chip 1902 from the side where the interposer 1901 is provided. Is provided. The pad 1908 is electrically connected to the semiconductor element 1909. The pad 1908 is connected to a wiring 1906 provided in the interposer 1901 by a wire 1907.

  Reference numeral 1910 corresponds to part of the printed wiring board, and 1911 corresponds to wiring or electrodes provided on the printed wiring board 1910. The wiring 1906 is connected to a wiring or electrode 1911 provided on the printed wiring board 1910 through a solder ball 1905. Note that various methods such as thermocompression bonding, thermocompression bonding with ultrasonic vibration, and the like can be used for the connection between the solder ball 1905 and the wiring or electrode 1911. It should be noted that the gap between the solder balls after pressure bonding may be filled with underfill to increase the mechanical strength of the connecting portion and the efficiency of diffusion of heat generated in the package. The underfill is not necessarily used, but connection failure can be prevented from occurring due to a stress caused by a mismatch between the thermal expansion coefficients of the interposer and the chip. When crimping by applying ultrasonic waves, poor connection can be suppressed as compared to the case of simply thermocompression bonding.

  In this embodiment, the package in which the chip is connected to the interposer by the wire bonding method is shown, but the present invention is not limited to this. These may be connected using a flip chip method. In this case, even if the number of pads to be connected is increased, a relatively wide pitch between the pads can be secured as compared with the wire bonding method, which is suitable for connection of a chip having a large number of terminals.

  Further, chips may be stacked in the package. In this case, since a plurality of chips can be provided in one package, there is an advantage that the size of the entire package can be suppressed.

  Furthermore, a plurality of packages may be stacked. This structure has an advantage that the yield can be increased because electrical inspection is performed for each package and only good products can be selected and stacked.

  Further, the package formed in this embodiment can be provided in a display device, an electronic device, or the like.

  According to the present invention, a small and highly integrated semiconductor device can be manufactured.

  This example can be used in combination with each of Embodiments 1 to 3 and Examples 1 to 11.

Although the semiconductor device of the present invention has a wide range of uses, for example, the ID chip 20 which is one form of the semiconductor device of the present invention is used for banknotes, coins, securities, certificates, bearer bonds, packaging containers, books And recording media, personal items, vehicles, foods, clothing, health supplies, daily necessities, medicines, electronic devices, and the like.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like (see FIG. 25A). The certificate refers to a driver's license, a resident's card, and the like (see FIG. 25B). Bearer bonds refer to stamps, gift cards, various gift certificates, and the like (see FIG. 25C). Packaging containers refer to wrapping paper for lunch boxes, plastic bottles, and the like (see FIG. 25D). Books refer to books, books, and the like (see FIG. 25E). The recording media refer to DVD software, video tapes, and the like (see FIG. 25F). Personal belongings refer to bags, glasses, and the like (see FIG. 25H). The vehicles refer to vehicles such as bicycles, ships, and the like (see FIG. 25G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

Forgery can be prevented by providing ID chips on bills, coins, securities, certificates, bearer bonds, and the like. In addition, by providing ID chips for personal items such as packaging containers, books, recording media, food items, daily necessities, electronic devices, etc., the efficiency of inspection systems and rental store systems can be improved. it can. By providing ID chips on vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. The ID chip is provided by being stuck on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

An example that can be applied to an object management and distribution system will be described with reference to FIG. Here, an example in which an ID chip is mounted on a product will be described. As shown in FIG. 26A, an ID chip 1402 is mounted on a beer bottle 1400 using a label 1401.

In the ID chip 1402, basic items such as a manufacturing date, a manufacturing place, and a material used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as a mask ROM or the memory transistor of the present invention. In addition, the ID chip 1402 records individual items such as the delivery destination and delivery date and time of each beer bottle. For example, as shown in FIG. 26B, when each beer bottle 1400 flows by the belt conveyor 1412 and passes through the writer device 1413, each delivery destination and delivery date and time can be recorded. Such individual items may be recorded using a rewritable and erasable memory (such as EEROM).

When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

Since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

By mounting an ID chip on such a product on which a plurality of delivery destinations can be recorded, it is possible to reduce the time required for manual input and to reduce input errors caused by the time. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to perform low-cost logistics management with few input errors.

Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced.

It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention. It is the perspective view which showed the manufacturing process of the semiconductor device which concerns on this invention. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention. 1 is a perspective view showing a semiconductor device according to the present invention. It is sectional drawing which showed the semiconductor device which concerns on this invention. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention. 1 is a block diagram showing a configuration of a semiconductor device according to the present invention. 1 is a perspective view showing a semiconductor device according to the present invention. It is a figure which shows _LOV definition. It is a figure which shows the concentration distribution of the impurity element in the horizontal direction and vertical direction of a GOLD area | region. It is a figure which shows the model figure and result of TFT which were used for simulation. It is a figure which shows the model figure and result of TFT which were used for simulation. It is a figure which shows the application example using the semiconductor device which concerns on this invention. It is a figure which shows the application example using the semiconductor device which concerns on this invention. It is sectional drawing which showed the semiconductor device which concerns on this invention. It is sectional drawing which showed the semiconductor device which concerns on this invention. It is sectional drawing which showed the manufacturing process of the semiconductor device which concerns on this invention.

Claims (3)

An amorphous semiconductor film is formed over a substrate having an insulating surface;
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Etching a portion of the crystalline semiconductor film to form a first semiconductor region and a second semiconductor region;
Forming a first insulating film on the first semiconductor region and the second semiconductor region;
Forming a plurality of particles on the first insulating film;
After selectively removing the plurality of particles formed on the second semiconductor region to form a floating gate electrode above the first semiconductor region, the floating gate electrode and the first insulating film A second insulating film is formed on top,
Forming a conductive film on the second insulating film,
And selectively removing portions of the conductive film, the first to form a first gate electrode larger width than the floating gate electrode over the semiconductor region, above the second semiconductor region Forming a second gate electrode on the substrate;
An impurity element is added to the first semiconductor region and the second semiconductor region;
A method for manufacturing a semiconductor device is characterized in that after the impurity element is activated to form a source region and a drain region, a source wiring or a drain wiring in contact with the source region and the drain region is formed. An amorphous semiconductor film is formed over a substrate having an insulating surface;
Irradiating the amorphous semiconductor film with laser light to form a crystalline semiconductor film,
Etching a portion of the crystalline semiconductor film to form a first semiconductor region, a second semiconductor region, and a third semiconductor region;
Forming a first insulating film on the first semiconductor region, the second semiconductor region, and the third semiconductor region;
Forming a plurality of particles on the first insulating film;
The floating gate electrode is formed by selectively removing the plurality of particles formed on the second semiconductor region and the third semiconductor region to form a floating gate electrode above the first semiconductor region. And forming a second insulating film on the first insulating film,
Forming a conductive film on the second insulating film,
And etching a portion of the conductive layer, wherein the floating than the gate electrode to form a first gate electrode having a large width above the first semiconductor region, the second above the second semiconductor region Forming a third gate electrode above the third semiconductor region,
After covering the first semiconductor region and the second semiconductor region with a mask, it is from one direction with respect to the third gate electrode and 0 degree to 60 with respect to the surface of the third semiconductor region Adding an impurity element imparting one of n-type and p-type to the third semiconductor region at an angle of degrees;
After the mask is removed, an impurity element imparting the other of n-type and p-type is added at an angle perpendicular to the surfaces of the first semiconductor region to the third semiconductor region, and the source region and the source region are heated. Forming a drain region,
A method for manufacturing a semiconductor device, comprising forming a source wiring or a drain wiring in contact with the source region and the drain region. In claim 2 ,
2. A method for manufacturing a semiconductor device, wherein directions of channel regions of the first to third semiconductor regions are the same.

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