JP4935782B2 - Self-diagnosis circuit - Google Patents

Description

  The present invention relates to a self-diagnosis circuit having a function of performing self-diagnosis as to whether or not the processing is correctly performed together with processing of an externally input signal.

  Conventionally, for example, Patent Document 1 proposes an apparatus having a function of performing signal processing on a sensor signal input from an external sensor and performing self-diagnosis on whether or not the signal processing is correctly performed. Specifically, in Patent Document 1, a signal processing circuit that inputs and processes a sensor signal, a diagnostic circuit that is the same circuit as the signal processing circuit, an output of the signal processing circuit, and an output of the diagnostic circuit An apparatus including a comparator for comparison has been proposed.

The diagnostic circuit receives the sensor signal, performs exactly the same signal processing as the signal processing circuit, and outputs the result. In addition, the comparator compares the output of the signal processing circuit and the output of the diagnostic circuit, and if the difference between the outputs exceeds the set value, an abnormality has occurred in either the signal processing circuit or the diagnostic circuit. Determine and output an abnormal signal.
Japanese Patent No. 4008044

  However, in the above conventional technique, in addition to the signal processing circuit that processes the sensor signal, a diagnostic circuit that is the same as the signal processing circuit is required, and it is necessary to prepare two circuit configurations in the apparatus. For this reason, if the circuit scale of the signal processing circuit is small, the parts and area are in an allowable range. However, as the circuit scale increases, both the parts and area become unacceptable levels.

  The comparator only compares the output of the signal processing circuit with the output of the diagnostic circuit and outputs the determination result. For this reason, it has not been possible to determine which of the signal processing circuit or the diagnostic circuit has failed. Therefore, if the diagnostic circuit has failed, it must be determined that one of the circuits is abnormal as long as an abnormal signal is output even though the original signal processing circuit is normal. There is also a problem that the entire apparatus having the self-diagnosis function has to be replaced.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a self-diagnosis circuit capable of performing self-diagnosis without providing a plurality of identical circuits.

  In order to achieve the above object, according to the first aspect of the present invention, the processing signal is allowed to pass when the clock signal of the first half period is input according to the clock signal in which one period is constituted by the first half period and the second half period. On the other hand, the first switching means (30) that permits passage of the reference signal when the clock signal of the second half cycle is input, and the processing signal and the reference signal are input from the first switching means (30), and the processing signal is input. Signal processing circuit means for generating a determination signal by performing signal processing on the reference signal when the reference signal is input while performing signal processing on the processing signal to generate an output signal (40) and the passage of the output signal output from the signal processing circuit means (40) when the clock signal of the first half period is input according to the clock signal, while the second half period is permitted. A second switching means (50) that permits passage of the determination signal output from the signal processing circuit means (40) when the clock signal is input, and an output signal from the second switching means (50) and sample hold The sample hold circuit means (60) for outputting the sampled and held output signal to the outside, and the signal processing circuit means when the determination signal is inputted from the second switching means (50) and the determination signal exceeds the allowable value. (40) is provided with determination circuit means (70) for outputting an abnormal signal indicating that a failure has occurred to the outside.

  Thus, by switching permission of signal passing by the first switching means (30) and the second switching means (50), processing of the processing signal and processing of the reference signal by one signal processing circuit means (40) It can be performed. Therefore, the self-diagnosis can be carried out without providing an extra signal processing circuit means (40) for self-diagnosis.

  According to the second aspect of the present invention, the determination circuit means (70) permits the output of the abnormal signal to the outside when both the clock signal of the second half period and the abnormal signal are input according to the clock signal. The circuit means (75) is provided.

  Thus, it is possible to prevent an abnormal signal from being output from the determination circuit means (70) when the signal processing circuit means (40) is processing the reference signal. Therefore, erroneous output of an abnormal signal can be prevented.

  As in the third aspect of the invention, the signal processing circuit means (40) can perform amplification processing of the signal as signal processing.

  The invention according to claim 4 is characterized in that the first switching means (30) and the second switching means (50) permit passage of a signal in accordance with a clock signal inputted from the outside. In this way, it is possible to capture from the outside without generating a clock signal in the self-diagnosis circuit.

  The invention according to claim 5 is characterized in that the first switching means (30) receives an externally generated reference signal and permits the passage of the reference signal in accordance with the clock signal. In this way, it is possible to capture from the outside without generating the reference signal by the self-diagnosis circuit.

  As in the sixth aspect of the invention, a voltage obtained by dividing the power supply voltage by a resistor can be used as the reference signal.

  As in the seventh aspect of the invention, the voltage generated by inputting the power supply voltage to the constant voltage circuit can be used as the reference signal.

  In the invention according to claim 8, the output permission circuit means (75) permits the output of the abnormal signal to the outside when both the clock signal and the abnormal signal in the latter half period are input according to the clock signal. It is a logic circuit that stops outputting an abnormal signal to the outside when a clock signal of the first half cycle is input.

  Thus, the output permission circuit means (75) can be constituted by a logic circuit. As the logic circuit, for example, a NOR circuit can be adopted, and a circuit constituted by an AND circuit or the like can also be adopted.

  In the invention according to claim 9, the first switching means (30) receives a plurality of reference signals, switches the passage of each of the plurality of reference signals according to the clock signal, and the signal processing circuit means (40) A plurality of reference signals input from the means (30) are sequentially processed.

  As a result, the result of signal processing for each of the plurality of reference signals can be determined, and more accurate determination can be performed.

  In the invention according to claim 10, the ratio between the first half cycle and the second half cycle of the clock signal is such that the first switching means (30) is allowed to pass the reference signal only once after the signal processing circuit means (40) is activated. It is characterized by being a ratio.

  Thereby, the self-diagnosis can be performed only once after the power supply to the self-diagnosis circuit is turned on, and the signal processing can be performed at all other times.

  In the invention according to claim 11, the ratio of the first half cycle to the second half cycle of the clock signal is such that the passage of the processing signal is permitted a plurality of times for one pass of the reference signal in the first switching means (30). It is characterized by a ratio. As a result, self-diagnosis can be performed at regular intervals.

  The invention as set forth in claim 12 is characterized in that a low-pass filter is provided after the sample-and-hold circuit means (60). Thereby, the switching noise generated when the second switching means (50) is switched can be attenuated.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
FIG. 1 is an overall configuration diagram of a self-diagnosis circuit according to a first embodiment of the present invention. As shown in this figure, the self-diagnosis circuit includes a clock 10, a reference voltage source 20, a first switch 30, a signal processing circuit 40, a second switch 50, a sample hold circuit 60, and a determination circuit 70. And.

  The clock 10 generates a clock signal having one cycle composed of a first half cycle and a second half cycle. For example, when the first half cycle of the clock signal is high and the second half cycle is low, the clock signal is a signal that repeats high / low. The clock signal generated by the clock 10 is input to the first switch 30, the second switch 50, the sample hold circuit 60, and the determination circuit 70, respectively. Hereinafter, the first half cycle of the clock signal is defined as high and the second half cycle is defined as low. This definition can be freely changed according to the design of the self-diagnosis circuit.

  The reference voltage source 20 is a power source that generates a constant reference voltage. This reference voltage is input to the first switch 30 as a reference signal.

  The first switch 30 is means for passing either the processing signal input from the outside or the reference signal input from the reference voltage source 20 in accordance with the clock signal input from the clock 10. The processing signal is, for example, a sensor signal output from the sensor.

  Specifically, the first switch 30 connects the input terminal 80 of the self-diagnosis circuit and the signal processing circuit 40 when a high clock signal is input from the clock 10, and passes the processing signal input to the input terminal 80. Allow. Further, the first switch 30 connects the reference voltage source 20 and the signal processing circuit 40 when a clock signal of the second half cycle is input, and permits passage of the reference signal output from the reference voltage source 20. The processed signal or the reference signal that has passed through the first switch 30 is input to the signal processing circuit 40. Such a first switch 30 is composed of, for example, a MOS transistor.

  The signal processing circuit 40 is a circuit that receives a processing signal and a reference signal from the first switch 30 and performs signal processing on each input signal. The signal processing circuit 40 performs the same signal processing on the processing signal and the reference signal.

  That is, when the processing signal is input, the signal processing circuit 40 performs signal processing on the processing signal to generate an output signal. In addition, when a reference signal is input, the signal processing circuit 40 performs the same signal processing as the signal processing of the processing signal on the reference signal to generate a determination signal. As the signal processing, for example, processing for amplifying a signal with a constant amplification factor is performed. The output signal or determination signal generated by the signal processing circuit 40 is a voltage value, and is input to the second switch 50.

  The second switch 50 is means for passing either the output signal input from the signal processing circuit 40 or the determination signal in accordance with the clock signal input from the clock 10. Specifically, the second switch 50 connects the signal processing circuit 40 and the sample hold circuit 60 when a high clock signal is input from the clock 10, and permits passage of the output signal output from the signal processing circuit 40. To do. The output signal that has passed through the second switch 50 is input to the sample and hold circuit 60. The second switch 50 connects the signal processing circuit 40 and the determination circuit 70 when a low clock signal is input from the clock 10 and permits the determination signal output from the signal processing circuit 40 to pass therethrough. The determination signal that has passed through the second switch 50 is input to the determination circuit 70.

  That is, while the high clock signal is input to the first switch 30 and the second switch 50, a path is formed in which the processing signal input to the input terminal 80 is processed by the signal processing circuit 40 and input to the sample hold circuit 60. Is done. On the other hand, while the low clock signal is input to the first switch 30 and the second switch 50, a path is formed in which the reference signal output from the reference voltage source 20 is processed by the signal processing circuit 40 and input to the determination circuit 70. Is done. Similar to the first switch 30, the second switch 50 is configured by, for example, a MOS transistor.

  The sample and hold circuit 60 inputs and outputs an output signal from the second switch 50, and outputs the sampled and held output signal to the outside via the output terminal 81. The sample and hold circuit 60 receives a clock signal from the clock 10 through a NOT circuit 90.

  Therefore, the sample hold circuit 60 samples the output signal while the high clock signal is output from the clock 10, and temporarily holds the hold signal while the low clock signal is output from the clock 10. Do. The sample and hold circuit 60 is composed of a switch, a capacitor, an operational amplifier, and the like.

  While the reference signal is signal-processed by the signal processing circuit 40 by switching the first switch 30 and the second switch 50, the signal processing circuit 40 generates a determination signal, so that the output from the signal processing circuit 40 is a normal output. Disappear. Therefore, the sample and hold circuit 60 always outputs a normal output signal obtained by processing the processed signal from the output terminal 81 even after the first switch 30 and the second switch 50 are switched so that the reference signal is processed. To play a role.

  The determination circuit 70 receives a determination signal from the second switch 50 and outputs an abnormal signal to the outside indicating that the signal processing circuit 40 has failed when the determination signal exceeds an allowable value. The determination circuit 70 includes a sample hold circuit 71, a first comparison voltage source 72, a second comparison voltage source 73, and a comparator 74.

  The sample hold circuit 71 samples and holds the determination signal input from the signal processing circuit 40 via the second switch 50 according to the clock signal input from the clock 10, and outputs the sampled determination signal to the comparator 74. To do. The sample hold circuit 71 samples the determination signal while the low clock signal is output from the clock 10, and temporarily holds (holds) the high clock signal from the clock 10. . Similar to the sample and hold circuit 60, the sample and hold circuit 71 includes a switch, a capacitor, an operational amplifier, and the like.

  The first comparison voltage source 72 is a power source that generates a constant first comparison voltage. This first comparison voltage is input to the comparator 74 as a first comparison signal. For example, the first comparison voltage is the upper limit value of the allowable value.

  The second comparison voltage source 73 is a power source that generates a constant second comparison voltage. This second comparison voltage is input to the comparator 74 as a second comparison signal. For example, the second comparison voltage is a lower limit value of the allowable value.

  The comparator 74 determines whether the determination signal input from the sample hold circuit 71 is within a range between the first comparison signal as the upper limit value and the second comparison signal as the lower limit value. When a preset reference voltage is amplified by the signal processing circuit 40, an expected processing result can be predicted. Therefore, the allowable value between the upper limit value and the lower limit value is determined by the signal processing circuit 40. If the signal is processed normally, it is set within a range that will naturally be included.

  When the voltage value indicated by the determination signal exceeds the first comparison voltage, which is the upper limit value, or falls below the second comparison voltage, which is the lower limit value, the comparator 74 generates the abnormal signal and sets the abnormal output terminal 82 to the abnormal output terminal 82. The abnormal signal is output to the outside. Such a comparator 74 includes a comparator or the like.

  The above is the overall configuration of the self-diagnosis circuit according to the present embodiment. This self-diagnosis circuit is used by being incorporated in an electronic circuit such as a sensor or an ECU.

  Next, the operation of the self-diagnosis circuit shown in FIG. 1 will be described. First, a clock signal is generated by the clock 10 and input to the sample and hold circuit 71 of the first switch 30, the second switch 50, the sample and hold circuit 60, and the determination circuit 70.

  When the first switch 30 and the second switch 50 are driven by a high clock signal, the self-diagnosis circuit enters the normal mode. That is, the input terminal 80 and the signal processing circuit 40 are connected by the first switch 30, and the signal processing circuit 40 and the sample hold circuit 60 are connected by the second switch 50.

  As a result, the processing signal input to the input terminal 80 is input to the signal processing circuit 40 via the first switch 30. The signal processing circuit 40 amplifies the signal to generate an output signal, and the output signal is input to the sample and hold circuit 60 via the second switch 50. The output signal is output to the outside from the output terminal 81 through the sample and hold circuit 60.

  Subsequently, when the first switch 30 and the second switch 50 are driven by a low clock signal, the self-diagnosis circuit is in a self-diagnosis mode. That is, the reference voltage source 20 and the signal processing circuit 40 are connected by the first switch 30, and the signal processing circuit 40 and the sample hold circuit 71 of the determination circuit 70 are connected by the second switch 50.

  As a result, the reference signal indicating the preset reference voltage output from the reference voltage source 20 is input to the signal processing circuit 40 via the first switch 30. Then, the signal processing circuit 40 amplifies similarly to the processing signal to generate a determination signal, and the determination signal is input to the sample hold circuit 71 via the second switch 50 and passes through the sample hold circuit 71. To the comparator 74.

  In the comparator 74, it is determined whether or not the voltage value indicating the determination signal is included in the allowable value between the first comparison voltage and the second comparison voltage. When it is determined that the voltage value is within the allowable value range, the signal processing circuit 40 outputs a normal signal indicating that it is functioning normally. On the other hand, when it is determined that the voltage value exceeds the allowable value, the comparator 74 generates an abnormal signal and outputs it to the outside via the abnormal output terminal 82.

  As described above, while the self-diagnosis mode is functioning, that is, while the low clock signal is input to the first switch 30 and the second switch 50, the output of the sample hold circuit 60 is sampled when the clock signal is high. Output signal is held. This is because when the self-diagnosis is performed, the output of the signal processing circuit 40 becomes a self-diagnosis output (determination signal) and is not a normal output, so that a normal processing output from the self-diagnosis circuit to the outside is maintained.

  In the sample hold circuit 71, the determination signal is sampled while the self-diagnosis mode is functioning, and the determination signal is held while the processing signal is processed. As a result, it is possible to prevent abnormality determination with respect to a regular input (process signal).

  As described above, the self-diagnosis circuit repeats the normal mode and the self-diagnosis mode, so that an output signal is continuously output, and when an abnormality occurs in the signal processing circuit 40, an abnormality signal is output. .

  As described above, in the present embodiment, the diagnostic reference signal and the original processing signal are time-divisionally input to the signal processing circuit 40 to be subjected to self-diagnosis, and the obtained determination signal is set. An abnormality of the signal processing circuit 40 is diagnosed by determining whether it is within the determination range.

  Thereby, it is not necessary to provide an extra signal processing circuit 40 for self-diagnosis, and the processing of the processing signal and the processing of the reference signal can be performed by one signal processing circuit 40. Therefore, the number of parts and the circuit area can be reduced.

  Further, when an abnormal signal is output, it can be reliably determined that the signal processing circuit 40 is in failure. For this reason, it is not necessary to replace the entire self-diagnosis circuit, and in some cases, it is possible to replace only the signal processing circuit 40.

  As for the correspondence between the description of the present embodiment and the description of the claims, the signal processing circuit 40 corresponds to the signal processing circuit means of the claims, and the sample hold circuit 60 is the sample of the claims. Corresponds to the hold circuit means. The first switch 30 corresponds to the first switching means in the claims, and the second switch 50 corresponds to the second switching means in the claims. Further, the determination circuit 70 corresponds to the determination circuit means in the claims.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. FIG. 2 shows a partial configuration diagram between the comparator 74 and the abnormal output terminal 82 in the determination circuit 70. As shown in this figure, the determination circuit 70 includes an output permission circuit 75 between the comparator 74 and the abnormal output terminal 82.

  The output permission circuit 75 is a NOR circuit that permits the output of the abnormal signal to the outside when both the low clock signal (CLK) and the abnormal signal are input. That is, the output permission circuit 75 stops passing the signal input from the comparator 74 while the high clock signal is input, that is, in the normal mode of the self-diagnosis circuit, and compares only in the self-diagnosis mode. The output of the device 74 is allowed to pass.

  As a result, an abnormal signal is output to the outside only in the self-diagnosis mode, and erroneous output of the determination circuit 70 in the normal mode can be prevented. Therefore, the reliability of the self-diagnosis circuit can be improved.

  For the correspondence between the description of this embodiment and the description of the claims, the output permission circuit 75 corresponds to the output permission circuit means of the claims.

(Other embodiments)
In each of the above embodiments, the signal processing circuit 40 performs signal amplification processing as signal processing. However, the content of the signal processing is not limited to signal amplification processing, and may be other processing.

  In each of the above-described embodiments, the configuration in which the clock 10 is provided in the self-diagnosis circuit is shown, but the clock signal may be input from the outside.

  In each of the above embodiments, a configuration in which the reference voltage source 20 is provided in the self-diagnosis circuit is shown, but a configuration in which a reference signal is input to the first switch 30 from the outside may be used. There is no limitation on the method of generating the reference signal, and the power supply voltage may be created by resistance division inside the self-diagnosis circuit, or may be created using an electronic circuit typified by a band gap constant voltage circuit. good. The same applies to the first comparison signal and the second comparison signal. That is, the reference signal may be a voltage obtained by dividing the power supply voltage with a resistor, or may be a voltage generated by inputting the power supply voltage to a constant voltage circuit.

  The configuration of the determination circuit 70 described in each of the above embodiments is an example, and the determination circuit 70 may be realized by another configuration. For example, the sample-and-hold circuit 71 used in the determination circuit 70 is not essential, and a logic circuit that does not perform abnormality determination in the normal mode may be constructed to prevent output of abnormality in the normal mode.

  The output permission circuit 75 shown in the second embodiment is composed of a NOR circuit, but is not limited to the NOR circuit, and may be composed of a logic circuit composed of an AND circuit or the like. That is, according to the clock signal, the logic circuit permits the output of the abnormal signal to the outside when both the low clock signal and the abnormal signal are input, while the abnormal signal is output when the high clock signal is input. Any configuration that stops output to the outside may be used.

  When the output permission circuit 75 shown in the second embodiment is used, an abnormal signal is output only in the self-diagnosis mode, so there is no need to consider abnormal signal output during normal operation, and the sample hold circuit 71 is omitted. You can also.

  The reference signal is not limited to one, and a plurality of reference signals may be used. In this case, the abnormality may be determined by sequentially switching using a switch capable of inputting a plurality of reference voltages to the signal processing circuit 40. Of course, the first switch 30 may be used for switching. In this case, the signal processing circuit 40 sequentially processes the plurality of reference signals input from the first switch 30.

  The time ratio between the normal mode and the self-diagnosis mode is determined by the high / low timing of the clock signal, but the time between the normal mode (eg, the first half cycle of the clock signal) and the self-diagnosis mode (eg, the second half cycle of the clock signal). The target ratio does not need to be 1: 1 and may be set freely. For example, the self-diagnosis mode may be performed only once when the power is turned on (that is, after the signal processing circuit 40 is started), or after performing the normal operation a plurality of times, the self-diagnosis is performed once. The operation may be repeated. In this case, the ratio between the high and low of the former clock signal is a ratio at which the first switch 30 is allowed to pass the reference signal only once after the signal processing circuit 40 is activated. On the other hand, the ratio between the high and low of the latter clock signal is a ratio in which the passage of the processing signal is permitted a plurality of times with respect to one pass of the reference signal in the first switch 30.

  There is a possibility that switching noise will be added to the output signal when the output signal is switched. For this reason, a low-pass filter may be provided after the sample and hold circuit 60 to attenuate the switching noise. Further, a moving average of the output signal may be taken to reduce the noise component.

1 is an overall configuration diagram of a self-diagnosis circuit according to a first embodiment of the present invention. It is a partial block diagram between a comparator and an abnormal output terminal in the determination circuit according to the second embodiment of the present invention.

Explanation of symbols

Reference Signs List 30 first switch 40 signal processing circuit 50 second switch 60 sample hold circuit 70 determination circuit 75 output permission circuit

Claims (12)

According to the clock signal in which one cycle is constituted by the first half cycle and the second half cycle, the processing signal is allowed to pass when the clock signal of the first half cycle is inputted, while the reference signal is inputted when the clock signal of the second half cycle is inputted. First switching means (30) for allowing passage of
The processing signal and the reference signal are input from the first switching means (30). When the processing signal is input, the processing signal is processed to generate an output signal, while the reference signal is input. Signal processing circuit means (40) for generating a determination signal by performing the same signal processing as the signal processing of the processing signal on the reference signal;
According to the clock signal, when the clock signal of the first half cycle is input, the output signal output from the signal processing circuit means (40) is allowed to pass, while when the clock signal of the second half cycle is input, Second switching means (50) for allowing passage of the determination signal output from the signal processing circuit means (40);
Sample and hold circuit means (60) for inputting and outputting the output signal from the second switching means (50), and outputting the sampled and held output signal to the outside;
The determination signal is input from the second switching means (50), and when the determination signal exceeds an allowable value, an abnormal signal indicating that the signal processing circuit means (40) is out of order is output to the outside. A self-diagnosis circuit comprising a determination circuit means (70).   The determination circuit means (70) is an output permission circuit means (75) for permitting the output of the abnormal signal to the outside when both the clock signal of the latter half period and the abnormal signal are input according to the clock signal. The self-diagnosis circuit according to claim 1, further comprising:   The self-diagnosis circuit according to claim 1 or 2, wherein the signal processing circuit means (40) performs amplification processing of the signal as the signal processing.   The said 1st switching means (30) and the said 2nd switching means (50) permit passage of the said signal according to the clock signal input from the outside. The self-diagnosis circuit described.   The said 1st switching means (30) inputs the said reference signal produced | generated outside, and permits passage of the said reference signal according to the said clock signal. Self-diagnosis circuit.   The self-diagnosis circuit according to any one of claims 1 to 4, wherein the reference signal is a voltage obtained by dividing a power supply voltage by a resistor.   5. The self-diagnosis circuit according to claim 1, wherein the reference signal is a voltage generated by inputting a power supply voltage to a constant voltage circuit.   The output permission circuit means (75) permits the output of the abnormal signal to the outside when both the clock signal of the second half cycle and the abnormal signal are input according to the clock signal, 3. The self-diagnosis circuit according to claim 2, wherein the self-diagnosis circuit is a logic circuit that stops outputting the abnormal signal to the outside when a clock signal is input. The first switching means (30) inputs a plurality of reference signals, switches the passage of each of the plurality of reference signals according to the clock signal,
The signal processing circuit means (40) sequentially processes a plurality of reference signals input from the first switching means (30), according to any one of claims 1 to 8. Self-diagnosis circuit.   The ratio between the first half cycle and the second half cycle of the clock signal is such that the first switching means (30) is allowed to pass the reference signal only once after the signal processing circuit means (40) is activated. 10. The self-diagnosis circuit according to any one of claims 1 to 9, wherein   The ratio between the first half period and the second half period of the clock signal is a ratio that allows the processing signal to pass a plurality of times with respect to one pass of the reference signal in the first switching means (30). The self-diagnosis circuit according to claim 1, wherein the self-diagnosis circuit is provided.   The self-diagnosis circuit according to any one of claims 1 to 11, wherein a low-pass filter is provided downstream of the sample-and-hold circuit means (60).

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