JP4935596B2 - Semiconductor test equipment - Google Patents

Description

  The present invention relates to a semiconductor test apparatus, and in particular, digitally measures a signal under measurement obtained by modulating and multiplexing a carrier signal output from a measurement target semiconductor (hereinafter referred to as DUT) used in the field of digital communication with a digital signal. The present invention relates to improvement of a digitizer that converts a signal into a memory.

  For example, in a DUT used in the field of digital communication such as a cellular phone, a carrier wave signal is modulated with a digital signal, and a multiplexed digital signal is output as a signal under measurement.

  FIG. 4 is a block diagram showing an example of a conventional semiconductor test apparatus configured to measure such a signal under measurement Ain. The signal under test Ain is input to the digitizer 10, converted into a digital signal by the A / D converter 11 at a predetermined timing, and stored in the capture memory 12. The control circuit 13 controls the capture timing of the digital signal to the capture memory 12 based on the trigger signal Strg input from the outside.

  The digital signal stored in the capture memory 12 is transferred to an external arithmetic device such as a tester controller 20 or a DSP, and predetermined arithmetic processing is executed to perform analysis processing of the DUT output.

  Here, the digital signal stored in the capture memory 12 is data obtained by digitally modulating the carrier wave signal, and when the analysis process is performed by the tester controller 20, detection processing and filter processing by the carrier wave signal are required. Therefore, in the conventional configuration shown in FIG. 4, the detection processing is performed by software of an arithmetic device (not shown) inside the tester controller 20, and the filter processing is performed by transferring the data after the detection processing from the tester controller 20 to the filter arithmetic device 30. It was.

  Patent Document 1 describes a configuration example of a digital modulation analysis apparatus in digital communication, and Patent Document 2 describes a configuration of a specific example of a digitizer in a semiconductor test apparatus.

Japanese Patent Application Laid-Open No. 07-297859 JP 2001-074810 A

  By the way, in recent years, an arithmetic device mounted on the tester controller 20 has been speeded up, and high-speed arithmetic processing can be performed without providing the filter arithmetic device 30 outside, but one arithmetic operation is always performed in the tester controller 20. Processing is rarely done. In particular, in the case of multi-CH processing that simultaneously measures a plurality of DUTs, it is necessary for the tester controller 20 to perform analysis processing for a plurality of CHs at the same time. In addition, it is desirable that the filter calculation process is performed by a dedicated device.

  However, even when analyzing data of a plurality of channels at the same time, it is necessary to share the filter arithmetic devices with each other, and there is a problem that analysis processing takes time.

  Further, since the measurement data of the DUT is temporarily stored in the capture memory 13 and then transferred to the tester controller 20, waveform acquisition to the capture memory 13, data transfer to the tester controller 20, and detection / filter processing are performed in order. It was necessary to be performed, which hindered the increase in measurement time.

  The present invention solves such a problem, and an object of the present invention is to provide a digital signal in a semiconductor test apparatus using a digital signal multiplexed by modulating a carrier signal with a digital signal as a signal to be measured. An object of the present invention is to realize a semiconductor test apparatus capable of executing detection / filter processing necessary for demodulation at high speed.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a semiconductor testing apparatus configured to convert a signal under measurement, which is a carrier wave signal output from a semiconductor to be measured, modulated by a digital signal and converted into a digital signal by a digitizer, and capture it in a memory,
The digitizer is provided with a filter circuit and a memory having a multiplier and one predetermined band characteristic of the one for detection respectively A / D converter for each measurement line, the other input of one of the measuring system A multiplexer is provided to switch the measurement system so that it can be input to the measurement system.
The A / D converter converts the signal to be measured into a digital signal, and at the same time, performs a detection process and a filter process using a multiplier and a filter circuit of both measurement systems, and fetches the processed data into the memory. It is characterized by that.

  According to the present invention, in a semiconductor test apparatus that uses a digital signal multiplexed by modulating a carrier wave signal with a digital signal as a signal to be measured, detection and filtering necessary for demodulating the digital signal can be performed at high speed. An executable semiconductor test apparatus can be realized.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, a signal under test Ain is a digital signal that is multiplexed by modulating a carrier signal with a digital signal. The signal under test Ain is input to a digitizer 40 from a DUT (not shown) and a predetermined signal is output by an A / D converter 41. It is converted into a digital signal at the timing.

The digital signal converted by the A / D converter 41 is input to one input terminal of the two multipliers 42 and 43. Signals I and Q having two carrier frequencies orthogonal to each other are input from the signal generation circuit 44 to the other input terminals of the multipliers 42 and 43, and detection processing is performed.
The multiplexed digital signal components are separated by the detection processing of the multipliers 42 and 43. Note that harmonic components generated in the detection process are attenuated by the filter circuits 45 and 46 having a predetermined band characteristic.

  The digital signal components Sdp and Sdq separated in this way are input to the capture memory 47 and stored. The digital data Sdp and Sdq stored in the capture memory 47 are transferred according to an instruction from the tester controller 50, and a DUT output analysis process is performed.

  The control circuit 48 controls operations of the signal generation circuit 44, the filter circuits 45 and 46, the capture memory 47, and the like based on a trigger signal Strg input from the outside.

  2A and 2B are diagrams for explaining the operation of FIG. 1. FIG. 2A shows the operation in the case of a single CH (channel), and FIG. 2B shows the operation in the case of multi-CH. In the case of a single channel, as shown in FIG. 2 (A), the detection process and the filter process are the data acquisition stage before being transferred to the capture memory 47 and stored, that is, the signal under measurement is converted into a digital signal by the A / D converter. It is done at the same time as the conversion.

  As a result, the computation processing time is hidden in the capture time, and execution can be completed at a higher speed than in the case where the analysis processing of the captured signals is processed sequentially as in the conventional example.

  In addition, in the case of a multi-CH that simultaneously measures a plurality of DUTs as shown in FIG. 2B, the detection / filter processing in the conventional example requires a processing time proportional to the number of CHs. For example, the detection and filter processing of each CH is performed simultaneously at the time of capturing regardless of the number of CHs, so that the execution of analysis processing can be completed faster than in the case of a single CH.

  FIG. 3 is a block diagram showing another embodiment of the present invention. In the embodiment of FIG. 1, two multipliers 42 and 43 and filter circuits 45 and 46 are provided for each CH. However, one multiplier and filter circuit are provided for each CH as shown in FIG. Also good.

  In FIG. 3, a signal under test Ain1 of CH1 is input from a DUT (not shown) to a digitizer 60 and converted into a digital signal by an A / D converter 61 at a predetermined timing.

  The digital signal converted by the A / D converter 61 is input to one input terminal of the multiplier 62 and also input to one input terminal of the multiplexer 72.

  To the other input terminal of the multiplier 62, one of the signals I and Q having two carrier frequencies orthogonal to each other (for example, I) is input from the signal generating circuit 63, and detection processing is performed. By the detection processing of the multiplier 62, the multiplexed digital signal component is separated. The harmonic component generated in the detection process is attenuated by the filter circuit 64 having a predetermined band characteristic.

  The digital signal component Sdp separated in this way is input to the capture memory 66 and stored. The digital data Sdp stored in the capture memory 66 is transferred in accordance with an instruction from the tester controller 80, and DUT output analysis processing is performed.

  The control circuit 65 controls operations of the signal generation circuit 63, the filter circuit 64, the capture memory 66, and the like based on a trigger signal Strg input from the outside.

  The digital signal converted by the A / D converter 61 is simultaneously input to the other input terminal of the multiplexer 72. The output signal of the multiplexer 72 is input to one input terminal of the multiplier 73.

  The other input terminal of the multiplier 73 is supplied with the other (for example, Q) of the signals I and Q having two carrier frequencies orthogonal to the carrier generated by the signal generator 63 from the signal generator 74. Processing is performed. By the detection processing of the multiplier 73, the multiplexed digital signal component is separated. The harmonic component generated in the detection process is attenuated by the filter circuit 75 having a predetermined band characteristic.

  The digital signal component Sdq thus separated is input to the capture memory 77 and stored. The digital data Sdq stored in the capture memory 77 is transferred according to an instruction from the tester controller 80, and analysis processing of the DUT output is performed.

  The control circuit 76 controls operations of the signal generation circuit 74, the filter circuit 75, the capture memory 77, and the like based on a trigger signal Strg input from the outside.

  By selecting a signal obtained by converting the signal under test Ain2 of CH2 into a digital signal by the A / D converter 71 at a predetermined timing in the multiplexer 72, CH2 constitutes a digitizer 70 that processes a signal different from CH1. You can also.

  The signal generation circuit, the control circuit, and the capture memory may be provided separately as shown in FIG. 3, but may be shared by both CHs.

  Further, the number of filter circuits is not limited to one for each CH, and may be constituted by a plurality of filter circuits, and the connection order of the multiplier and the filter circuit is not limited to the embodiment.

  As described above, according to the present invention, detection necessary for demodulating a digital signal in a semiconductor test apparatus using a digital signal multiplexed by modulating a carrier signal with a digital signal as a signal to be measured.・ Semiconductor test equipment capable of high-speed filter processing can be realized.

It is a block diagram which shows one Example of this invention. It is operation | movement explanatory drawing of FIG. It is a block diagram which shows the other Example of this invention. It is a block diagram of a conventional semiconductor test apparatus.

Explanation of symbols

40, 60, 70 Digitizers 41, 61, 71 A / D converters 42, 43, 62, 73 Multipliers 44, 63, 74 Signal generation circuits 45, 46, 64, 75 Filter circuits 47, 66, 77 Capture memory 48 , 65, 76 Control circuit 50, 80 Tester controller 72 Multiplexer

Claims (1)

In a semiconductor testing apparatus configured to convert a signal under measurement, which is a carrier wave signal output from a semiconductor to be measured, modulated by a digital signal and converted into a digital signal by a digitizer, and capture it in a memory,
The digitizer is provided with a filter circuit and a memory having a multiplier and one predetermined band characteristic of the one for detection respectively A / D converter for each measurement line, the other input of one of the measuring system A multiplexer is provided to switch the measurement system so that it can be input to the measurement system.
The A / D converter converts the signal to be measured into a digital signal, and at the same time, performs a detection process and a filter process using a multiplier and a filter circuit of both measurement systems, and fetches the processed data into the memory. A semiconductor test apparatus.

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