JP4933643B2 - Control device for gaming machine - Google Patents

Description

  The present invention relates to a control device for a gaming machine.

  Recent pachinko machines are provided with an operation device such as an image display device, a sound effect generator, and a lighting device for providing a player with various effects. In the conventional gaming machine control device shown in FIG. 16, the entire gaming machine is controlled by a control circuit including the microcomputer 7 and the ROM 8, and dedicated operation circuits 4 and 5 receiving signals from the microcomputer 7 are used. , 6 individually perform detailed control of the image display device 1, the sound effect generator 2, and the lighting device 3, thereby reducing the processing load on the microcomputer 7 (see, for example, Patent Document 1).

JP-A-4-17871 (second line on the right side of the lower part of the fifth page to eleventh line on the right side of the upper part of the sixth page, FIG. 2)

  However, in the above-described conventional gaming machine control device, the ROM 8 provided in the control circuit stores operation data related to the operations of the devices 1, 2, and 3 in addition to the control program. There is a problem that the storage area is limited.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a control device for a gaming machine capable of increasing the storage area of a control program than before.

  A gaming machine control device according to the invention of claim 1 made to achieve the above object, a CPU for controlling the gaming machine, control storage means for storing control program data executed by the CPU, An actuating device provided in the gaming machine, an actuating circuit for actuating the actuating device, and a control storage means, provided separately from the actuating data storage means for storing actuating data for the actuating device, and an actuating data storage And an address signal input unit for inputting an address designation signal corresponding to a control signal from the CPU, and an operation data storage means provided in the operation data storage means based on the address designation signal. Connected to the data signal output unit for outputting the operating data to the operating circuit, the pulse generating means for generating the pulse signal, and the address signal input unit, Addressing means for starting output of the addressing signal to the operating data storage means in response to the input of the control signal, and outputting a predetermined number of addressing signals one by one based on the pulse signal; The addressing signal changing means for changing the addressing signal output from the addressing means based on the pulse signal, the actuating circuit actuates the actuating device according to the operating data, and the pulse generating means comprises a CPU It is characterized in that a pulse signal is generated at an interval different from the clock pulse for operating.

[Invention of Claim 1]
According to the invention according to claim 1 configured as described above, the operation data storage means provided separately from the control storage means storing the control program data is the operation data for operating the operating device. Therefore, the storage area of the control program data in the control storage means can be made larger than before.

  When the CPU outputs a control signal, the addressing means sequentially outputs a predetermined number of addressing signals one by one in response to the control signal, and operates the address specified by these addressing signals. Data is sequentially output to the operating circuit. As a result, it is possible to reduce the processing load on the CPU as compared with the case where the CPU designates a predetermined number of addresses one by one.

  Further, the addressing signal can be output at a time interval different from the CPU clock pulse.

Front view of a pachinko gaming machine according to an embodiment of the present invention An exploded perspective view of a pachinko machine An exploded perspective view of a pachinko machine Front view of game board Rear view of pachinko machine Rear view of game board Block diagram showing electrical configuration of display control board Block diagram showing the electrical configuration of the voice control board Block diagram showing the electrical configuration of the illumination control board Block diagram of pulse generation circuit Block diagram of lamp control circuit Flow chart showing control program Conceptual diagram of storage area of data ROM Timing chart for address signal output The block diagram which shows the electrical constitution of the electrical decoration control board which concerns on other embodiment (3). Block diagram of a conventional gaming machine control device

  Hereinafter, a first embodiment of a pachinko gaming machine to which the present invention is applied will be described with reference to FIGS. In the pachinko gaming machine according to the present embodiment, as shown in FIG. 1, a front frame 90 is detachably attached to an outer frame 82 fixed to a game island of a game hall, as in a general game machine.

  A game board side assembly in which various parts are assembled to the game board 11 shown in FIG. 2 and a mechanism plate side assembly in which various parts are assembled to the mechanism plate 75 shown in FIG. Are assembled.

  First, the components constituting the game board side assembly will be described. The game board 11 is formed of a wooden, generally rectangular plate material. As shown in FIG. 4, a guide rail 12 is attached to the front surface of the game board 11, and the inside of the guide rail 12 is a game area R1. A display device 13 is provided substantially in the center of the game area R1, and a start winning port 14, a large winning port 15, and an out port 16 are provided below the display device 13 in a line from the top in order at intervals. ing. Wind turbines 19 and 19 are provided on the left and right sides of the display device 13 in the game area R1, and side lamps 22 and 22 incorporating LEDs 22A and 22B are provided on the outer sides of the wind turbines 19 and 19, respectively. In addition, start gates 18 and 18 and upper side winning ports 20 and 20 are provided on both the left and right sides of the start winning opening 14, respectively. The lower side winning prize ports 21 and 21 are provided. Further, in addition to these winning holes and the like, a plurality of nails (not shown) stand up in the game area R1.

  Further details of each required part will be described.

  The upper side winning port 20 and the lower side winning port 21 are both open upward with an opening width that allows one game ball to be won.

  The start gate 18 has a gate-like structure through which game balls can pass through, and the passed game balls are detected by a normal symbol start switch built in the start gate 18. Based on the detection signal, the symbols of the normal symbol display unit 24 to be described later are variably displayed.

  The start winning opening 14 has a so-called pocket structure and opens upward, and movable wing pieces 14C and 14C are provided on both sides of the opening. Both the movable wing pieces 14C, 14C are always in an upright state, and the opening width of the start winning opening 14 sandwiched between the two movable wing pieces 14C, 14C is large enough to accommodate about one game ball. ing. When the solenoid provided on the back of the game board 11 is driven, the movable wing pieces 14C and 14C are tilted sideways, and the game ball is guided to the movable wing piece 14C and easily enters the start winning opening 14.

  When a game ball wins the start winning opening 14, a special symbol start switch provided in the start winning opening 14 detects the game ball, and the display device 13 variably displays the symbols as described later. In addition, while the display device 13 displays the symbols in a variable manner, up to four winning balls won in the start winning opening 14 are stored on hold.

  The special winning opening 15 is formed in a horizontally long shape and is normally closed by the movable door 15T. When the pachinko gaming machine enters a “hit state” due to the establishment of a predetermined condition to be described later, the solenoid provided on the back of the game board 11 is driven, and the movable door 15T falls forward for a predetermined period. Thereby, the grand prize opening 15 is opened, and a large number of game balls can be awarded to the big prize opening 15 by using the movable door 15T as a guide. When a game ball wins the big prize opening 15, a detection switch provided in the big prize opening 15 detects the game ball, and, for example, 15 game balls are paid out as a prize ball based on the detection signal. When the predetermined condition is satisfied (for example, whether the opening time of the movable door 15T has reached 30 seconds or whether 10 game balls have been won in the big winning opening 15), the movable door 15T is moved to the game board 11 side. It rotates to close the special winning opening 15.

  The display device 13 includes a frame-shaped decorative frame 23 (see FIG. 4) attached from the front side of the game board 11 to an opening (not shown) formed through the game board 11, and the game board 11. The liquid crystal module is mounted from the rear surface side (not shown) (specifically, a TFT-LCD module). Then, the player can view the display screen 34 of the liquid crystal module through the decorative frame 23 from the front side of the game board 11.

  As shown in FIG. 1, usually three left, middle and right special symbols 13A, 13B and 13C are displayed side by side at the center of the display screen 34. Each of these special symbols 13A, 13B, and 13C is composed of, for example, a plurality of types that express numbers from “0” to “11”. Usually, each special symbol 13A, 13B, and 13C has a predetermined value. The types are confirmed and displayed on the display screen 34. Then, it is determined whether or not the game ball is won at the start winning opening 14, each special symbol 13A, 13B, 13C is scrolled up and down and displayed in a variably manner. After a predetermined time, for example, left, middle, right Each special symbol 13A, 13B, 13C is stopped and displayed in order. At this time, for example, when the result of the determination is successful and all the special symbols 13A, 13B, and 13C are the same symbol, that is, when they are all over, the game is in a “hit state” and the movable door 15T is opened. It is.

  A normal symbol display unit 24 is provided at the upper left corner of the display screen 34. This normal symbol display unit 24 determines whether or not the normal symbol start switch provided in the start gate 18 detects the passing of the game ball. For example, the normal symbol display unit 24 displays numbers (ordinary symbols) from “0” to “9”. After variably displaying over a predetermined period, a predetermined number is fixedly displayed. For example, when the final number displayed is an odd number, the movable wing pieces 14C and 14C provided in the start winning opening 14 are tilted sideways over a predetermined period (for example, 0.4 seconds). The normal symbols displayed on the normal symbol display unit 24 are not limited to numbers, and may be alphabets or symbols.

  Next, the mechanism plate-side assembly will be described. The mechanism plate 75 is made of a synthetic resin and has a rectangular shape that is longer in the vertical direction than the game board 11 as a whole, as shown in FIG. A rectangular window 74 is formed in the central portion of the mechanism plate 75, and when the mechanism plate 75 is stacked on the game board 11, control boards 49 to 52 (described later) fixed to the game board 11 are placed in the rectangular window 74. Be placed. A casing-like cover (not shown) that accommodates the control boards 49 to 52 is detachably attached to the edge of the rectangular window 74.

  As shown in FIG. 5, a game ball tank 71 is provided on the rear surface of the mechanism plate 75 above the rectangular window 74. In addition, a prize ball payout device 30 and a ball rental payout device 31 are provided on the side portion of the rectangular window 74. The game ball tank 71 and the prize ball payout device 30 and the rental ball payout device 31 are connected by a game ball guide rail 71R extending along the upper side and the right side of the rectangular window 74.

  Below the rectangular window 74 in the rear surface 75R of the mechanism plate 75, the payout control board 58 and the power supply device 54 are attached side by side. The payout control board 58 drives the prize ball payout device 30 and the ball lending payout device 31 based on a signal received from the main control board 49 described later, and a predetermined number of game balls are transferred to the upper plate 27A (FIG. 1 and FIG. 1). (See FIG. 3). The power supply device 54 receives power from the AC 24V facility power source provided in the pachinko hall, transforms this to a predetermined voltage, and distributes the power to each part. The payout control board 58 and the power supply device 54 are also individually housed in a transparent resin case. In addition, the mechanism board 75 is assembled | attached so that rotation with respect to the front frame 90 is possible with the hinge parts 73 and 73 with which the upper and lower ends of one side part were equipped (refer FIG. 2).

  Next, the outer frame 82 will be described. A front frame 90 is rotatably provided on the outer frame 82. The outer frame 82 is configured by joining four wooden long plates 83 into a vertically long rectangular shape, and a front plate 84 is interposed between lower ends of the long plates 83 constituting both sides of the outer frame 82. The lower edge portion of the front plate 84 is joined to a long plate 83 constituting the lower side.

  Metal hinge pieces 85, 85 are attached to one side of the outer frame 82 at two locations above and below it. Further, as shown in FIG. 2, the long plate 83 constituting the side opposite to the hinge piece 85 of the outer frame 82 has a pair of engagements at two locations on the inner surface near the upper end and the lower end. Parts 86, 86 are attached. Furthermore, the prepaid card unit 40 is attached to the outer surface of the outer frame 82 on the side provided with the hinge piece 85 as shown in FIG.

  The front frame 90 is made of, for example, a synthetic resin and has a rectangular structure corresponding to a portion above the front plate 84 in the front surface of the outer frame 82 as shown in FIG. On one side of the front frame 90, metal hinge pieces 91, 91 are provided at two locations above and below the front frame 90. The hinge pieces 91, 91 are engaged with hinge pieces 85, 85 provided on the outer frame 82, and the front frame 90 is attached to the outer frame 82 so as to be rotatable.

  Further, as shown in FIG. 2, a pair of locked portions 92 and 92 (see FIG. 2) are provided on the side of the front frame 90 opposite to the side on which the hinge piece 91 is provided. The front frame 90 is fixed to the outer frame 82 in a non-rotatable manner by locking the locking portions 86, 86 provided on the outer frame 82 and the locked portions 92, 92. The

  As shown in FIG. 3, a game window 90 </ b> W is formed in the front frame 90 so that the game area R <b> 1 of the game board 11 inserted from the rear side of the front frame 90 can be viewed from the front side of the front frame 90. It has become. A glass frame 95 is provided on the front surface of the front frame 90. The glass frame 95 is rotatably attached to a side edge portion of the front frame 90 on the hinge piece 91 side, and includes a window 95W that is slightly smaller than the game window 90W, and a glass plate is stretched thereon. . A decorative lamp 96 is disposed on the edge of the window 95 </ b> W in the front surface of the glass frame 95. The decorative lamp 96 includes a plurality of LEDs 96 </ b> A to 96 </ b> F (see FIG. 1) inside a lamp cover made of a colored (for example, red or yellow) translucent resin. The game board 11 is accommodated in a surrounding wall 78 standing upright on the rear side of the front frame 90, and is locked by locking levers 77 provided at a plurality of locations on the surrounding wall 78 (see FIG. 2). .

  As shown in FIG. 4, a horizontally long rotating plate 97 is attached to the front frame 90 below the glass frame 95 so as to be rotatable with respect to the front frame 90, similarly to the glass frame 95. An upper plate 27A is attached to the rotating plate 97.

  A lower plate unit 98 having a lower plate 27 </ b> B is attached to the front frame 90 below the rotating plate 97. Then, the game ball as a prize ball when the game is performed is paid out to the upper plate 27A, and when the button 29 provided on the upper plate 27A is pressed, the game ball moves from the upper plate 27A to the lower plate 27B.

  A pair of speakers 59S and 59S are provided near the left and right ends of the upper plate 27A in the rotating plate 97, and an operation knob 28 is provided at the right end of the lower plate 27B in the lower plate unit 98. It has been. The speaker 59S, the operation knob 28, the decorative lamp 96, and the like are connected to a predetermined electric circuit of the pachinko gaming machine by a connector. When the operation knob 28 is operated, the launching device 53 provided at the lower end of the front frame 90 is driven, and the game ball accommodated in the upper plate 27A is ejected toward the game area R1 on the game board 11. The decoration lamp 96 and the speaker 59S are driven according to the progress of the game. The above is the description of the mechanism plate side assembly.

  By the way, as shown in FIG. 2, a display control board 51 is provided on the rear surface of the game board 11 so as to overlap the rear side of the liquid crystal module constituting the display device 13. In addition, an electrical decoration control board 52 and an audio control board 50 are attached side by side below the display control board 51. And the main control board 49 is attached so that it may overlap with the back side of these electrical decoration control board 52, the audio | voice control board 50, and the display control board 51 (refer FIG. 6). Each of the control boards 49 to 52 is housed in a transparent resin case.

  Next, the electrical configuration of the pachinko gaming machine according to the present embodiment will be described with reference to FIGS. The main control board 49 includes, for example, a one-chip microcomputer formed by combining a CPU, a RAM, and a ROM as a main part.

  The one-chip microcomputer receives signals from sensors and the like for detecting game balls that have won the winning gates 14, 15, 20, 21 and the start gate 18, as well as an illumination control board 52, a voice control board 50, and a payout control. Each part is controlled by outputting a control signal to the substrate 58, the display control substrate 51 and the like. In addition, the one-chip microcomputer outputs game information related to the game situation of the pachinko gaming machine to a management device provided in the pachinko hall via the information output circuit.

  As shown in FIG. 7, the display control board 51 includes a control ROM 63 for storing control data and a control program for displaying an image used for presentation on the display device 13 on the display device 13, a special design, a background image, and the like. An image data ROM 66 for storing image data such as character images and character images. Then, based on the command data input from the main control board 49 via the I / O port 60, the display CPU 61 extracts predetermined control data and control program from the control ROM 63, and outputs a predetermined signal in the work area of the work RAM 64. Generate and output to VDP 62.

  The VDP 62 has a display control function and a high-speed drawing function for performing image display, reads necessary data from the image data ROM 66 based on a drawing command (predetermined signal) from the display control CPU 61, and displays the data on the display screen 34. Map data such as special symbols, background images, character images, and character images are created and stored in the VRAM 67 once. The image data stored in the VRAM 67 is output to the LCD control circuit 65 by the VDP 62. The LCD control circuit 65 converts the input image data into a video signal composed of a color signal (for example, RGB signal) and a synchronization signal, The data is output to the display device 13 (specifically, the TFT-LCD). The display device 13 displays an image on the display screen 34 based on the video signal. In FIG. 7, reference numeral 68 denotes a reset circuit that outputs a reset signal for initializing the display control MPU including the display CPU 61 and the work RAM 64. Reference numeral 69 denotes a clock circuit which outputs a reference clock signal to the display control MPU.

  The audio control board 50 controls the BGM generated from the speaker 59S and the production audio based on the command data from the main control board 49, and sets the audio data.

  Specifically, as shown in FIG. 8, the sound control board 50 includes a control ROM 203 that stores control data and a control program for generating sound. Then, the voice CPU 201 reads a control program and control data from the control ROM 203 based on command data input from the main control board 49 via the I / O port 200, generates a predetermined signal in the work RAM 202, and generates a voice. A signal is output to the synthesis circuit 204. The voice synthesis circuit 204 synthesizes a voice signal based on the signal from the voice CPU 201 and outputs it to the volume amplification circuit 205. The audio signal amplified by the volume amplifier circuit 205 is output to the left and right speakers 59S and 59S via the volume switch 206. Here, by operating the volume switch 206, the volume of the sound generated from the speaker 59S can be adjusted.

  In FIG. 8, reference numeral 208 denotes a reset circuit that outputs a reset signal for initializing the audio control MPU composed of the audio CPU 201 and the work RAM 202. Reference numeral 207 denotes a clock circuit that outputs a reference clock signal to the audio control MPU.

  The electrical decoration control board 52 as the “control device for gaming machine” of the present invention is based on the command data from the main control board 49, and the electrical decoration devices such as the decorative lamp 96 and the side lamps 22 and 22 (the present invention). A plurality of LEDs 22A, 22B, 96A to 96F included in the “operating device” of FIG.

  As shown in FIG. 9, the illumination control board 52 is a control program for controlling the LEDs 22A, 22B, 96A to 96F provided in the lamps 22, 96 (corresponding to “control program data” of the present invention). Is stored in the control ROM 103 (corresponding to "control storage means" of the present invention).

  An illumination CPU 101 (corresponding to “CPU” of the present invention) provided on the illumination control board 52 is controlled from the control ROM 103 based on command data input from the main control board 49 via the I / O port 100. Is read. Then, a predetermined signal is generated in the work RAM 102 based on the read control program, and the adder circuit 104 (corresponding to the “address designating means” of the present invention) and the pulse generating circuit 105 (the “pulse generating means of the present invention”). Is equivalent to “)”. The adder circuit 104 and the pulse generator circuit 105 constitute the “address designation signal changing means” of the present invention.

  The pulse generation circuit 105 outputs a predetermined pulse signal to the addition circuit 104 based on the signal from the electrical decoration CPU 101 as will be described in detail later. The adder circuit 104 outputs an address signal to the data ROM 106 based on the signal from the electrical decoration CPU 101 and the pulse signal from the pulse generation circuit 105.

  The data ROM 106 stores lighting data (corresponding to “operation data” in the present invention) of the plurality of LEDs 22A, 22B, 96A to 96F. The data ROM 106 is provided separately from the control ROM 103 and is detachably provided on the illumination control board 52. When changing the lighting data, the data ROM 106 may be replaced, so that the lighting data can be easily changed. The data ROM 106 corresponds to “operation data storage means” of the present invention.

  The data ROM 106 outputs the lighting data at the address specified by the address signal from the adder circuit 104 to the lamp control circuit 107 (corresponding to the “operation circuit” of the present invention). As shown in the figure, since the lighting data of the data ROM 106 is directly output to the lamp control circuit 107, the lighting data is once taken into the lighting CPU 101 and output from the lighting CPU 101 to the lamp control circuit 107. Compared to the above, the burden on the CPU 101 for electrical decoration can be reduced. In the data ROM 106, an input port for inputting an address signal corresponds to an “address signal input unit” of the present invention, and an output port for outputting lighting data corresponds to “data signal output” of the present invention.

  The lamp control circuit 107 turns on or off the plurality of LEDs 22A, 22B, 96A to 96F included in the lamps 22 and 96 based on the lighting data from the data ROM 106.

  Note that reference numeral 109 in FIG. 9 denotes a reset circuit, which outputs a reset signal for initializing the illumination control MPU composed of the illumination CPU 101 and the work RAM 102. Reference numeral 108 denotes a clock circuit which outputs a reference clock signal to the illumination control MPU.

  Now, each required part of the electrical decoration control board 52 will be described in detail.

  The illumination CPU 101 sets one of a plurality of lamp effect patterns based on command data from the main control board 49, and outputs various signals set in advance according to the effect patterns. That is, the illumination CPU 101 outputs a start address signal to the adder circuit 104. The pulse generation circuit 105 includes a signal for setting a period T of the pulse signal (see FIG. 14), that is, a time interval from the generation of one pulse signal to the generation of the next pulse signal. And a signal for setting the number of output times of the pulse signal. The start address, the pulse signal period T, and the number of pulse signal generations in each lamp effect pattern are set as shown in Table 1 below, for example.

  As shown in FIG. 10, the pulse generation circuit 105 receives the pulse signal from the oscillation circuit 120 that generates the pulse signal, outputs the pulse signal to the addition circuit 104, and counts the number of received pulse signals. And a counter circuit 121. The oscillation circuit 120 sets the period T (see FIG. 14) of the pulse signal based on the signal from the electrical decoration CPU 101. Specifically, the oscillation circuit 120 is provided with a frequency dividing circuit 122, which divides a reference pulse of an oscillation element (not shown) provided in the oscillation circuit 120 in accordance with a signal from the electrical decoration CPU 101. Thus, the period T of the pulse signal is changed. In the present embodiment, the period T of the pulse signal output from the oscillation circuit 120 is different from the period of the reference clock signal output from the clock circuit 108.

  When the adder circuit 104 receives the start address signal from the illumination CPU 101, the adder circuit 104 outputs the start address signal to the data ROM 106 in response to the input of the pulse signal from the pulse generation circuit 105. In addition, every time one pulse signal is input from the pulse generation circuit 105 after the start address signal is output, the address signal output earlier is set to a predetermined value (in this embodiment, one address of the address of the data ROM 106). (Corresponding values) are added and updated, and the updated address signal is output to the data ROM 106. Thereby, the address of the data ROM 106 is regularly specified.

  Here, the electrical decoration CPU 101 outputs only the start address signal, and since the adder circuit 104 sequentially generates and outputs the address signals output thereafter, the electrical decoration CPU 101 outputs a plurality of address signals. Compared to the case where individual address signals are output one by one, the processing load on the electrical decoration CPU 101 can be reduced. It is also possible to control the other circuit 110 while the adder circuit 104 generates and outputs an address signal.

  The data ROM 106 has a storage area R0 having a predetermined capacity, and the storage area R0 is divided into a plurality of address spaces of 1 byte, for example, as shown in FIG. Yes. One lighting data is stored in an address space corresponding to each address in the storage area R0.

  Each bit included in one lighting data (8 bits) corresponds to one LED. When the bit value of the lighting data is “1”, the LED is turned on, and when the bit value is “0”, the LED is turned off. That is, each bit corresponds to one LED, and the lighting states of the eight LEDs 22A, 22B, 96A to 96F are set at one time by one lighting data.

  For example, in the lighting data stored at address b in FIG. 12, the LEDs corresponding to the first, second, third and sixth bits are turned on, and the LEDs corresponding to the fourth, fifth, seventh and eighth bits are turned off. .

  The lamp control circuit 107 is connected to the data bus of the data ROM, and the LEDs 22A, 22B, 96A to 96F provided in the lamps 22 and 96 according to the lighting data from the data ROM 106, that is, the bit data corresponding to each LED. Switch power supply to and off. As shown in FIG. 11, the output port of the lamp control circuit 107 is composed of, for example, an 8-bit parallel port. One LED is connected to each bit of the output port. In the present embodiment, the first to third bits are connected to the upper left, left middle, and lower left LEDs 96A to 96C of the decorative lamp 96, and the fourth to sixth bits are the upper right, middle right, and lower right LEDs 96D of the decorative lamp 96. To 96F, the seventh bit is connected to the LED 22A of the left side lamp 22, and the eighth bit is connected to the LED 22B of the right side lamp 22. Based on the lighting data read from the data ROM 106, the power supply by the power supply device 54 is switched on and off for each bit of the output port. That is, when the bit value is “1”, the LED is turned on and power is supplied to the LED. When the bit value is “0”, the LED is turned off and the power supply to the LED is cut off. Thereby, the eight LEDs 22A, 22B, 96A to 96F can be individually turned on or off. The above is the description of the configuration of the electrical decoration control board 52.

  Next, the operation of the electrical decoration control board 52 configured as described above will be described with reference to the flowchart of FIG. When the power of the pachinko gaming machine is turned on, the illumination CPU 101 provided on the illumination control board 52 takes out the control program M shown in FIG.

  When the control program M is run, first, external command reception processing (S1) is performed. In this process (S1), command data is received from the main control board 49.

  Following the external command reception process (S1), an effect pattern determination process (S2) is performed. In this process (S2), a lamp effect pattern (see Table 1) is determined based on command data from the main control board 49. Then, based on this effect pattern, the following start address setting process (S3), execution step setting process (S4), and start timer process (S5) are performed.

  In the start address setting process (S3), a start address signal is set according to the production pattern.

  In the execution step setting process (S4), the period T of the pulse signal output from the pulse generation circuit 105 and the number of output of the pulse signal are set according to the effect pattern.

  In the start timer process (S5), a predetermined time is set according to the lamp effect pattern, and thereafter, the value of the start timer is counted up every time this process (S5) is performed.

  Next, as other processing, for example, other processing such as circuit control is performed (S6). Next, it is checked whether or not the value of the start timer has reached a predetermined time, that is, whether or not to start the lamp effect according to the determined effect pattern (S7). If the predetermined time has not been reached (No in S7), time counting by the start timer is continued. On the other hand, when the predetermined time is reached (Yes in S7), a default address setting process (S8) for setting the LEDs 22A, 22B, 96A to 96F provided in the lamps 22 and 96 to the default state is performed.

  In the default address setting process (S8), an address signal corresponding to the address a of the data ROM 106 is set in the adder circuit 104, and a pulse signal is generated once from the pulse generation circuit 105, and an address signal corresponding to the address a is generated. The data ROM 106 is output. And after making each LED22A, 22B, 96A-96F into a default state initially, the lamp production according to the production pattern is started. Note that an address signal corresponding to a default address may be output using a clock pulse generated by the clock circuit 108.

  Next, the operation of the illumination control board 52 and the LEDs 22A, 22B, 96A to 96F according to the present embodiment will be specifically described.

  For example, when the lamp effect pattern 1 (see Table 1) is executed, that is, in the start address setting process (S3), an address signal corresponding to the address b of the data ROM 106 is set as the start address signal. In the setting process (S4), when the number of output times of the pulse signal is set to “4” and the cycle T of the pulse signal is set to “1 second”, the following is performed.

  First, when a predetermined time set according to the production pattern has elapsed after receiving command data from the main control board 49, an address signal designating an address a is output as a default address.

  Next, an address signal designating the address b is set in the adder circuit 104, and a pulse signal is output from the pulse generation circuit 105. When a pulse signal is input to the adder circuit 104, an address signal designating an address b is output to the data ROM 106. One second after the address signal corresponding to the address b is output, when the second pulse signal is input to the adder circuit 104, an address signal designating an address c that is one address higher than the address b is output. . One second after the address signal corresponding to the address c is output, when the third pulse signal is input to the adder circuit 104, an address signal designating the address d that is one address higher than the address c is output. . Further, one second after the address signal corresponding to the address d is output, when the fourth pulse signal is input to the adder circuit 104, an address signal designating the address e that is advanced by one address from the address d is output. Is done. That is, address signals that specify four consecutive addresses b, c, d, and e are output in turn every second. When the address signal designating the address e is output, the pulse signal has been output “4” times, so that the output of the pulse signal from the pulse generation circuit 105 is stopped.

  This is seen from the player side as follows. Initially, all the LEDs 22A, 22B and 96A to 96F are in a default state, that is, in an extinguished state based on the lighting data “00000000” at the address a. Next, based on the lighting data “11100100” at address b, the upper left, middle left, lower left and lower right LEDs 96A to 96C, 96E of the decoration lamp 96 are lit for 1 second. In the next 1 second, based on the lighting data “11100110” at address c, the upper left, middle left, lower left and lower right LEDs 96A to 96C, 96E of the decoration lamp 96 and the LED 22A of the left side lamp 22 are turned on. . For the next one second, based on the lighting data “11001110” of the address d, the upper left, left middle, right middle and lower right LEDs 96A, 96B, 96E, 96F of the decoration lamp 96, and the LED 22A of the left side lamp 22 Lights up. Further, for the next one second, the LEDs 96A, 96B, and 96E in the upper left, middle left, and middle right of the decoration lamp 96 and the LEDs 22A of the left side lamp 22 are turned on based on the lighting data “11001010” of the address e. . That is, the combination of LEDs that are turned on every second is switched.

  Further, when the lamp effect pattern 3 (see Table 1) is executed, that is, in the start address setting process (S3), an address signal designating the address d of the data ROM 106 is set as the start address signal. In the setting process (S4), when the number of output times of the pulse signal is set to “3” and the cycle T of the pulse signal is set to “2 seconds”, the following is performed.

  First, when a predetermined time set according to the production pattern has elapsed after receiving command data from the main control board 49, an address signal designating an address a is output as a default address.

  Next, an address signal designating an address d is set in the adder circuit 104, and a pulse signal is output from the pulse generation circuit 105. When a pulse signal is input to the adder circuit 104, an address signal designating an address d is output to the data ROM 106. Two seconds after the address signal corresponding to the address d is output, when the second pulse signal is input to the adder circuit 104, an address signal designating the address e that is one address higher than the address d is output. . Further, when a third pulse signal is input to the adder circuit 104 two seconds after the address signal corresponding to the address e is output, an address signal designating the address f that is one address higher than the address e is output. Is done. That is, address signals specifying three consecutive addresses d, e, and f are sequentially output every 2 seconds. Since the pulse signal is output “3” times when the address signal corresponding to the address f is output, the output of the pulse signal from the pulse generation circuit 105 is stopped.

  This is seen from the player side as follows. That is, at first, all the LEDs 22A, 22B and 96A to 96F are turned off based on the lighting data of the address a. Next, based on the lighting data “11001110” of the address d, the upper left, left middle, right middle and lower right LEDs 96A, 96B, 96E, and 96F of the decorative lamp 96 and the LED 22A of the left side lamp 22 are lit for 2 seconds. To do. For the next 2 seconds, the LEDs 96A, 96B, and 96E in the upper left, middle left, and middle right of the decoration lamp 96 and the LEDs 22A of the left side lamp 22 are turned on based on the lighting data “11001010” of the address e. Further, for the next 2 seconds, based on the lighting data “01101101” of the address f, the LED lamps 96A, 96B, 96E, and 96F of the decoration lamp 96, and the LED 22B of the right side lamp 22 are displayed. And light up. That is, the combination of LEDs that are turned on every 2 seconds is switched.

  As described above, according to the present embodiment, the lighting data for lighting the LEDs 22A, 22B, 96A to 96F provided in the lamps 22 and 96 is data provided separately from the control ROM 103 storing the control program M. Since it is stored in the ROM 106, the storage area of the control program M can be made larger in the control ROM 103 than in the prior art. As a result, more control programs can be stored in the control ROM 103, and various lamp effects can be performed.

  Further, when performing the lamp effect, the illumination CPU 101 only needs to specify the first one of the plurality of lighting data, and needs to output an address signal that specifies the other lighting data. Therefore, the processing load on the electrical decoration CPU 101 can be reduced.

  Furthermore, even when the combination of lighting data is the same, that is, when the combination of the address signals output from the adder circuit 104 is the same as in the lamp effect pattern 1 and the lamp effect pattern 4, the cycle of the pulse signal By varying T, the time for switching the combination of LEDs to be lit can be varied, and the lighting mode of the lamp can be varied.

  When only the lighting data is changed by changing the model, etc., if the control program and the lighting data are stored in the same ROM, in addition to the lighting data to be changed, a control program that does not need to be changed is again read into the ROM. Need to write to. On the other hand, when the control program and the lighting data are stored in separate ROMs as in the present embodiment, the control program that does not need to be changed need not be written in the ROM, and only the lighting data to be changed is stored. What is necessary is just to newly write in ROM.

[Other Embodiments]
The present invention is not limited to the above-described embodiment. For example, the embodiments described below are also included in the technical scope of the present invention, and various other than the following can be made without departing from the scope of the invention. It can be changed and implemented.
(1) In the above-described embodiment, the present invention is applied to the electric decoration control board 52 provided in the pachinko gaming machine. You may apply to a control board.

(2) In the above embodiment, the reference pulse generated by the oscillation element provided in the pulse generation circuit 105 is divided by the frequency dividing circuit 122 according to the effect pattern and output to the adding circuit 104. The reference clock signal generated by the clock circuit 108 may be divided by the divider circuit 122 and output to the adder circuit 104.

(3) In the first embodiment, the decoration lamp 96 and the side lamp 22 are controlled by the same pulse generation circuit 105, addition circuit 104, data ROM 106, and lamp control circuit 107, but as shown in FIG. A light emitter (for example, a decorative lamp 96) provided in the glass frame 95 of the pachinko gaming machine and a light emitter (for example, the side lamp 22) provided in the game board 11 are separated into separate adder circuits 300A, 300B, Control may be performed by the pulse generation circuits 301A and 301B, the data ROMs 302A and 302B, and the lamp control circuits 303A and 303B. In this way, since the light emitters provided in the glass frame 95 and the light emitters provided in the game board 11 can be controlled separately, the effects produced by the lamps can be diversified.

(4) In the above embodiment, the address signal output from the adder circuit 104 is configured to add a value corresponding to one address of the address every time a pulse signal is input. A value corresponding to (for example, 2 addresses) may be added so that the address of the data ROM 106 specified by the address signal is increased by a plurality of addresses. Further, the value to be added is not limited to a positive value, and may be a negative value. In this way, the plurality of addresses in the data ROM 106 designated by the address signal can be reduced by a predetermined address.

(5) In the above embodiment, the number of pulse signal outputs is set for each lamp effect pattern, and when the number of pulse signal outputs reaches the set number of times, the output of the pulse signal from the pulse generation circuit 105 is stopped. However, a default time is set for each lamp production pattern, and when the default time is reached, the illumination CPU 101 outputs a stop signal that causes the pulse generation circuit 105 to stop the pulse signal. Good. In this case, there is no need to set the number of times the pulse signal is output.

(6) In the above embodiment, the present invention is applied to the illumination control board 52. However, the present invention is applied to the sound control board 50, the display control board 51, and the presentation control such as 7-segment and dot matrix. Also good.

22 Side lamp (actuator)
52 Lighting control board (control device for gaming machines)
96 Decorative lamp (actuator)
103 Control ROM (control storage means)
104 Adder circuit (address designation means)
105 Pulse generation circuit (pulse generation means)
106 Data ROM (operation data storage means)
107 Lamp control circuit (actuation circuit)
300A, 300B adder circuit (address designation means)
301A, 301B Pulse generation circuit (pulse generation means)
302A, 302B Data ROM (operation data storage means)
303A, 303B Lamp control circuit (operation circuit)
101 CPU for illumination
22A, 22B, 96A-96F LED
M control program

Claims (1)

A CPU for controlling the gaming machine;
Control storage means for storing control program data executed by the CPU;
An operating device provided in the gaming machine;
An actuation circuit for actuating the actuating device;
An operation data storage means provided separately from the control storage means and storing the operation data of the operation device;
An address signal input unit provided in the operation data storage means, to which an address designation signal corresponding to a control signal from the CPU is input;
A data signal output unit provided in the operating data storage means for outputting the operating data stored in the operating data storage means to the operating circuit based on the address designation signal;
Pulse generating means for generating a pulse signal;
Connected to the address signal input unit, triggered by the input of a control signal from the CPU, starts outputting the address designation signal to the operation data storage means, and a predetermined number of the address designation signals Addressing means for outputting one by one based on the pulse signal;
An address designation signal changing means for changing the address designation signal output by the address designation means based on the pulse signal;
The operating circuit operates the operating device according to the operating data,
The gaming machine control device, wherein the pulse generating means generates the pulse signal at an interval different from a clock pulse for operating the CPU.

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