JP4931828B2 - ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法 - Google Patents

ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法 Download PDF

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Publication number
JP4931828B2
JP4931828B2 JP2007553585A JP2007553585A JP4931828B2 JP 4931828 B2 JP4931828 B2 JP 4931828B2 JP 2007553585 A JP2007553585 A JP 2007553585A JP 2007553585 A JP2007553585 A JP 2007553585A JP 4931828 B2 JP4931828 B2 JP 4931828B2
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Japan
Prior art keywords
memory
dma
write
read
request
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Expired - Fee Related
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JP2007553585A
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English (en)
Japanese (ja)
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JP2008529181A5 (enExample
JP2008529181A (ja
Inventor
ドン、サン、フー
フラクス、ブライアン、キング
ホフスティ、ハーム、ピーター
修 高橋
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
JP2007553585A 2005-02-03 2006-01-25 ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法 Expired - Fee Related JP4931828B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/050,040 2005-02-03
US11/050,040 US7617338B2 (en) 2005-02-03 2005-02-03 Memory with combined line and word access
PCT/EP2006/050433 WO2006082154A2 (en) 2005-02-03 2006-01-25 System and method for a memory with combined line and word access

Publications (3)

Publication Number Publication Date
JP2008529181A JP2008529181A (ja) 2008-07-31
JP2008529181A5 JP2008529181A5 (enExample) 2008-11-27
JP4931828B2 true JP4931828B2 (ja) 2012-05-16

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ID=36097154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007553585A Expired - Fee Related JP4931828B2 (ja) 2005-02-03 2006-01-25 ライン・アクセスおよびワード・アクセスの結合を用いてメモリをアクセスするためのシステムおよび方法

Country Status (8)

Country Link
US (1) US7617338B2 (enExample)
EP (1) EP1849083B1 (enExample)
JP (1) JP4931828B2 (enExample)
CN (1) CN101111828B (enExample)
AT (1) ATE415664T1 (enExample)
DE (1) DE602006003869D1 (enExample)
TW (1) TWI362591B (enExample)
WO (1) WO2006082154A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7681014B2 (en) * 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US8015323B2 (en) * 2006-02-28 2011-09-06 Infineon Technologies Ag Acquisition of data and autonomous transfer of data through communication interface in automotive system
US20080201312A1 (en) * 2007-01-17 2008-08-21 Encirq Corporation Systems and methods for a devicesql parallel query
JP4356030B2 (ja) * 2007-05-17 2009-11-04 ソニー株式会社 情報処理装置および方法
US7941574B2 (en) * 2008-08-11 2011-05-10 International Business Machines Corporation CKD partial record handling
US7870309B2 (en) 2008-12-23 2011-01-11 International Business Machines Corporation Multithreaded programmable direct memory access engine
US7870308B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Programmable direct memory access engine
JP6146128B2 (ja) * 2013-05-20 2017-06-14 ヤマハ株式会社 データ処理装置
US9842630B2 (en) * 2013-10-16 2017-12-12 Rambus Inc. Memory component with adjustable core-to-interface data rate ratio

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07152733A (ja) * 1993-10-05 1995-06-16 Fujitsu Ltd ベクトル・データを処理するコンピュータ・システムおよび方法
JP2003044354A (ja) * 2001-07-26 2003-02-14 Matsushita Electric Ind Co Ltd メモリ制御装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3782335T2 (de) * 1987-04-22 1993-05-06 Ibm Speichersteuersystem.
US4918587A (en) * 1987-12-11 1990-04-17 Ncr Corporation Prefetch circuit for a computer memory subject to consecutive addressing
US4929246A (en) * 1988-10-27 1990-05-29 C. R. Bard, Inc. Method for closing and sealing an artery after removing a catheter
US5446845A (en) * 1993-09-20 1995-08-29 International Business Machines Corporation Steering logic to directly connect devices having different data word widths
US5784700A (en) * 1994-12-12 1998-07-21 Texas Instruments Incorporated Memory interface with address shift for different memory types
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
US6351784B1 (en) * 1998-12-28 2002-02-26 International Business Machines Corp. System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US7386671B2 (en) * 2000-06-09 2008-06-10 Texas Instruments Incorporated Smart cache
EP1182564A3 (en) * 2000-08-21 2004-07-28 Texas Instruments France Local memory with indicator bits to support concurrent DMA and CPU access
US6775727B2 (en) * 2001-06-23 2004-08-10 Freescale Semiconductor, Inc. System and method for controlling bus arbitration during cache memory burst cycles
US6920510B2 (en) * 2002-06-05 2005-07-19 Lsi Logic Corporation Time sharing a single port memory among a plurality of ports

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07152733A (ja) * 1993-10-05 1995-06-16 Fujitsu Ltd ベクトル・データを処理するコンピュータ・システムおよび方法
JP2003044354A (ja) * 2001-07-26 2003-02-14 Matsushita Electric Ind Co Ltd メモリ制御装置

Also Published As

Publication number Publication date
US7617338B2 (en) 2009-11-10
CN101111828A (zh) 2008-01-23
EP1849083A2 (en) 2007-10-31
JP2008529181A (ja) 2008-07-31
DE602006003869D1 (de) 2009-01-08
TW200632668A (en) 2006-09-16
US20060179176A1 (en) 2006-08-10
WO2006082154A3 (en) 2006-09-21
WO2006082154A2 (en) 2006-08-10
EP1849083B1 (en) 2008-11-26
ATE415664T1 (de) 2008-12-15
CN101111828B (zh) 2010-10-13
TWI362591B (en) 2012-04-21

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