JP4931413B2 - Image reading device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain stable image data through a CMOS image sensor, with a simple configuration. <P>SOLUTION: An image reader 1 includes an illumination part 14 for irradiating an imaging position 12c on a carrying line with illuminating light, an imaging lens for imaging the illuminating light reflected by a coin 20, a coin arrival sensor 41 for outputting an object detection trigger signal TR in response to detection of the coin 20, a CMOS image sensor 37 for starting exposure successively for respective pixel lines synchronously with generation of an exposure control signal AE to generate image data and starting output for respective pixel lines synchronously with generation of a vertical synchronizing signal VD, and a CMOS image sensor control circuit 42 for generating various control signals. The CMOS image sensor control circuit 42 generates the exposure control signal AE with output of the object detection trigger signal TR as a trigger and generates a lighting control signal LD between an exposure start timing for the last pixel line and generation of the vertical synchronizing signal VD. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to an image reading apparatus that reads an image of a reading object such as a coin or medal.

Conventionally, as a technique in such a field, there is a reading device described in Japanese Patent Application Laid-Open No. 2002-259977. The device described in this publication is an image reading device that is incorporated in a vending machine and reads information such as graphics stamped on coins. This vending machine is provided with a guide frame for guiding the coins inserted into the coin slot and a stopper for locking the coins in the guide frame. The image reading apparatus is an apparatus for imaging a coin locked by a stopper in a stationary state and outputting image data, and includes a CMOS image sensor as an imaging element.
Japanese Patent Laid-Open No. 2002-259977

  However, in a device that reads an image of a coin while conveying the coin at a high speed, when such a CMOS image sensor is used as an imaging device, there is a problem that stable image data cannot be obtained from the CMOS image sensor. Further, if it is attempted to obtain image data of an imaging target that moves at high speed using a CMOS image sensor, there arises a problem that a complicated configuration for controlling in accordance with the conveyance speed of the imaging target is required.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading apparatus capable of obtaining stable image data by a CMOS image sensor with a simple configuration when imaging a reading object to be conveyed.

In order to solve the above problems, an image reading apparatus according to the present invention is an image reading apparatus that reads an image of a surface of an object to be read that is conveyed along a predetermined conveyance path. An illumination unit that irradiates the imaging position with illumination light, an imaging lens that forms an image of illumination light reflected by the reading object at the imaging position, and a detection signal that detects that the reading object has arrived at the imaging position In synchronization with the generation of the exposure control signal and the detection unit that outputs, the image formed by the imaging lens starts to be exposed in order from the first pixel line to the last pixel line, so that the first pixel line to the last pixel line and it sets so as to be offset from each other to each exposure time to, in synchronism with the generation of the vertical synchronizing signal after the exposure start of the last pixel line sequentially shifted from a first pixel line to the last pixel line Exposure ends, comprising a CMOS image sensor to start outputting the image data for each pixel line in an order of starting exposure, a CMOS image sensor control circuit for generating a lighting control signal and the exposure control signal and the vertical synchronizing signal, a CMOS image sensor control The circuit generates an exposure control signal in response to the output of the detection signal, and generates a lighting control signal between the exposure start timing of the final pixel line and the generation timing of the vertical synchronization signal, and the imaging lens and the CMOS image The sensor is configured to store an image of the reading object in the image data from the first pixel line to the last pixel line .

  When the CMOS device resets a synchronizing signal such as a vertical synchronizing signal, unstable image data tends to be output at the beginning of resetting. This makes it difficult to capture an instantaneous state of the moving body by the CMOS image sensor, and as a result, a stable image of the read object being conveyed cannot be obtained. Paid attention. According to the image reading apparatus of the present invention, the illumination light applied to the reading object is reflected by the surface of the reading object at the imaging position and imaged by the imaging lens, and then the image formed is the CMOS. Images are taken by an image sensor. At this time, after the CMOS image sensor is controlled so that the exposure is sequentially started for each of the plurality of pixel lines of the CMOS element in response to the output of the detection signal of the reading object, the exposure of the final pixel line is started. Illumination light is irradiated at a timing before the generation of the vertical synchronization signal. Accordingly, it is possible to stably capture the entire image of the reading object moving at the imaging position, and it is possible to output stable imaging data regardless of the conveyance speed of the reading object. Here, “occurrence” of various signals means that the signals are turned on and are in a valid state (also referred to as “assertion”).

In addition, the CMOS image sensor control circuit generates a horizontal synchronization signal that defines an output period of image data at a constant period, and prevents the generation timing of the horizontal synchronization signal from being shifted due to the output of the detection signal. Is preferably maintained at a constant period . If such a CMOS image sensor control circuit is provided, the image data output period for each pixel line can be maintained within a certain period when a CMOS image sensor captures an object to be read, and immediately after the coin is detected. Disturbances in imaging data output to can be prevented.

  The final pixel line is preferably located at the outer edge of the image formation range of the reading object in the entire pixels of the CMOS image sensor. In this case, since one frame of image data can be generated and processed in accordance with the image of the reading object, it is possible to improve the image reading speed and to realize random imaging of the reading object.

  It is also preferable that the CMOS image sensor control circuit determines the generation timing of the lighting control signal based on a control signal synchronized with the exposure start timing of the plurality of pixel lines and the generation timing of the vertical synchronization signal. In this way, even if the frequency of a control signal such as a clock for controlling the CMOS image sensor is changed, the exposure time of all the pixel lines and the illumination light irradiation timing can be appropriately set, and the reading target More stable imaging of the entire image of the object is possible.

  According to the image reading apparatus of the present invention, stable image data obtained by the CMOS image sensor can be obtained with a simple configuration when imaging the reading object to be conveyed.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of an image reading apparatus according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
The image reading apparatus according to the first embodiment of the present invention is an apparatus that reads a pattern on the surface of a coin in order to determine whether or not the coin is true or false. For example, the image reading apparatus is incorporated in an ATM or the like. As shown in FIGS. 1 and 2, the image reading apparatus 1 includes a rectangular parallelepiped housing 10 made of resin, and a circular opening window 11 is provided on the top surface of the housing 10. In addition, a transparent plate 12 made of sapphire glass or the like is fitted into the opening window 11, and the 500 yen coin (reading object) 20 is imaged on the reading surface 12 b so as to coincide with the upper surface of the transparent plate 12. The image is arranged at 12c. And the conveying apparatus 30 for conveying the coin 20 to the transparent board 12 above the housing | casing 10 is provided.

  The conveying device 30 is provided adjacent to the upper surface of the image reading device 1, an endless belt 31 extending in the conveying direction A of the coin 20, a pair of pulleys 32 and 33 for circulatingly driving the endless belt 31. And a transport table 34 extending in the transport direction A. Accordingly, the endless belt 31 is driven by rotating the pulley 33 with a motor (not shown), and the coin 20 is transported on the transport path B formed between the transport table 34 and the endless belt 31 of the image reading apparatus 1. can do.

  An illumination unit 14 is provided in the housing 10 at a position close to the lower surface of the transparent plate 12. The illumination unit 14 is annularly arranged around the imaging position 12c of the transparent plate 12, and a plurality of light sources 15 (for example, surface mount type LEDs or lead type LEDs) that emit illumination light toward the outside, An annular reflecting mirror 16 is disposed around each light source 15 and reflects the irradiation light from each light source 15 toward the coin 20 at the imaging position 12c. Indirect illumination is achieved by such an illumination unit 14. That is, the light emitted from the light source 15 is once reflected by the reflecting mirror 16 and then illuminates the coin 20 from the back side. Moreover, the illumination part 14 is comprised so that irradiation light may be radiate | emitted by the lighting control signal sent from the CMOS image sensor control circuit 42 mentioned later.

  Further, a CMOS image sensor 37 for capturing an image of the surface of the coin 20 is provided inside the housing 10, and reflected light reflected by the coin 20 is provided between the CMOS image sensor 37 and the illumination unit 14. Is formed on the CMOS image sensor 37. Therefore, the light reflected by the coin 20 is collected on the CMOS image sensor 37 by the imaging lens 36, and an image of the coin 20 can be formed on the CMOS image sensor 37.

  The CMOS image sensor 37 accumulates charges in the pixels on the light receiving surface according to the image of the coin 20 imaged by the imaging lens 36, converts the accumulated charges into image data, and captures image data to be described later. It is a device that outputs to the control circuit 44. On the light receiving surface of the CMOS image sensor 37, a plurality of pixel lines (for example, 512) having a plurality of pixels in the horizontal direction are arranged in the vertical direction. The image data of the surface of the coin 20 imaged by the CMOS image sensor 37 is composed of a plurality of scanning lines corresponding to each pixel line. The operation of the CMOS image sensor 37 is controlled by various signals sent from the CMOS image sensor control circuit 42, and the resulting image data is output to the image data capture control circuit 44 (details will be described later).

  Further, a light emitting element (for example, LED) 38 that emits light toward the transparent plate 12 is provided below the transparent plate 12, and the light emitting element 38 is interposed above the transparent plate 12 via the transparent plate 12. A light receiving element (for example, a photodiode) 39 that receives light emitted from the light emitting element 38 is provided at the facing position. It is determined whether or not the coin 20 exists on the transport path B by the cooperation of the light emitting element 38 and the light receiving element 39. When the coin 20 does not exist at the coin arrival position 40, the light receiving element 39 receives light from the light emitting element 38, and a light reception signal is sent to a coin detection circuit described later. On the other hand, when the coin 20 is present at the coin arrival position 40, the light from the light emitting element 38 is blocked and the received light signal is interrupted. The coin arrival position 40 is set on the upstream side of the transparent plate 12 on the transport path B, and the coin 20 is positioned at the imaging position 12c at the moment when the transported coin 20 passes through the coin arrival position 40. It is set to be. And by using such a light emitting element 38 and the light receiving element 39, arrival of the coin 20 to the coin arrival position 40 and passage of the coin 20 to the coin arrival position 40 can be detected.

  Next, the internal configuration of the image reading apparatus 1 will be described in more detail with reference to FIG.

  As shown in the figure, a coin detection circuit 43 is connected to the light receiving element 39. The coin detection circuit 43, the light emitting element 38, and the light receiving element 39 constitute a coin arrival sensor (detection unit) 41 that detects the arrival of coins. The coin detection circuit 43 generates an object detection trigger signal (detection signal) TR for the coin 20 in accordance with the light reception signal received from the light receiving element 39. The coin detection circuit 43 generates and outputs an on-state object detection trigger signal TR when a light reception signal is sent from the light receiving element 39. That is, if the coin 20 is present at the coin arrival position 40, the object detection trigger signal TR is set to a low level (ON state), and if the coin 20 is not present at the coin arrival position 40, the object detection trigger is detected. The signal TR is set to a high level (off state). Therefore, at the time when the coin 20 passes the coin arrival position 40, the pulse signal of the object detection trigger signal TR changes from the OFF state to the ON state, and when the coin 20 reaches the imaging position 12c (see FIG. 1). The pulse signal of the object detection trigger signal TR changes from the on state to the off state.

  The CMOS image sensor 37 captures an image of the coin 20 and generates a charge signal for each pixel line, and analog-to-digital conversion of the charge signal output from the CMOS image sensor 37a to generate image data. And an AD converter 37b to be generated. A CMOS image sensor control circuit 42 is connected to the CMOS image sensor 37a, and the CMOS image sensor 37a receives a clock signal CL, an exposure control signal AE, and a vertical synchronization signal VD sent from the CMOS image sensor control circuit 42. The operation is controlled by the horizontal synchronizing signal HD. The clock signal CL, the exposure control signal AE, the vertical synchronization signal VD, and the horizontal synchronization signal HD are pulse signals having two levels, an on state and an off state.

  Specifically, the CMOS image sensor 37a sequentially outputs the charges accumulated in each pixel line to the AD converter 37b in synchronization with the vertical synchronization signal VD being turned on, and the AD converter 37b Are converted into image data and output. At this time, the CMOS image sensor 37 outputs image data of one pixel line in synchronization with one cycle of the horizontal synchronization signal HD. That is, the horizontal synchronization signal HD defines the output period of image data for each pixel line. The clock signal CL is a signal for defining the discharge timing of image data of each pixel of the CMOS image sensor 37.

  The CMOS image sensor 37a generates a charge signal for one frame by sequentially starting the exposure of the image of the coin 20 in each pixel line in synchronization with the exposure control signal AE being turned on. As described above, the generated charge signal is converted into image data by the AD converter 37b after the generation of the vertical synchronization signal VD. That is, the CMOS image sensor 37a starts accumulating the charge of the first pixel line at the timing when the exposure control signal AE is turned on, and then waits for a certain time (for example, one cycle of the horizontal synchronization signal HD) for the second time. Accumulation of charge on the pixel line is started. In this way, the CMOS image sensor 37a starts exposure up to the final pixel line at regular intervals. In addition, the CMOS image sensor 37a ends the exposure operation of the first pixel line started as described above at the timing when the vertical synchronization signal VD is generated, and then for a certain time (for example, one cycle of the horizontal synchronization signal HD). ), The exposure operation of each pixel line is sequentially terminated.

FIG. 4 is a diagram showing the positional relationship between the light receiving surface and pixel lines of the CMOS image sensor 37a and the imaging range of the coin 20. As shown in FIG. As shown in the figure, the range W _P in the pixel line array direction of the formed light-receiving surface Ac by the overall pixel of a CMOS image sensor 37a, so that the image I _m of the coin 20 in the imaging position 12c is imaged The imaging lens 36 is set. In the positional relation between such light-receiving surface and the imaging range, the first pixel line P1 of the CMOS image sensor 37a, the range W located close above the outer edge of the _P, the second pixel line P2 is first It is adjacent to the lower side of one pixel line P1. Further, the third pixel and subsequent lines located adjacent to the forward, final pixel line PN _L of, located near the outer edge of the lower range W _P. That is, the range covered by the first pixel line P1~ last pixel line PN _L substantially coincides with the range W _P of the imaging of the coin 20. By thus setting the first pixel line PN _L pixel lines P1~ final, the image data of one frame generated in a range W _P and the pixel line PN _L of the first pixel line P1~ final Thus, the image of the coin 20 can be efficiently stored.

  An image data capture control circuit 44 is connected to the AD converter 37 b of the CMOS image sensor 37. The image data capture control circuit 44 receives the clock signal CL, the horizontal synchronization signal HD, and the vertical synchronization signal VD from the CMOS image sensor control circuit 42, and the object detection trigger signal TR from the coin detection circuit 43. Has been drawn. The image data take-in control circuit 44 receives the image data from the AD converter 37b, and sends the image data to the data storage unit 45b of the image processing unit 45 for determining the coin 20 and determining the authenticity via the data bus BU. Write. The data bus BU is a data bus for transferring data between the external device of the image processing unit 45 and the CPU 45a and the data storage unit 45b in the image processing unit 45. The image data take-in control circuit 44 sends a bus release request signal SB1 to the CPU 45a operating as a bus master on the data bus BU when the object detection trigger signal TR is turned on. When the image data take-in control circuit 44 receives the bus release permission signal SB2 from the CPU 45a, it sends a write control signal SB3 to the data storage unit 45b and simultaneously sends image data to the data storage unit 45b via the data bus BU. Is output. As a result, the image data is written from the image data take-in control circuit 44 to the data storage unit 45b.

  The CMOS image sensor control circuit 42 is a circuit that controls the operation of the CMOS image sensor 37 as already outlined. As shown in FIG. 5, the CMOS image sensor control circuit 42 includes a counter 51, a control signal generation unit 52, an HD synchronization reset unit 53, a VD reception control unit 54, an image output control unit 55, and a TR reception control unit 57. ing.

The counter 51 generates a counter value based on a clock OS from an oscillator such as a crystal oscillator and sends it to the control signal generator 52. This counter value is composed of upper n bits U _{1 to} U _n and lower m bits L _{1 to} L _m and is counted up at a constant period according to the clock OS. The counter 51 receives the HD synchronization reset section 53 from the counter reset signal RST, which resets only the upper n bits _U 1 ~U _n.

The control signal generating unit 52 constantly monitors the counter values U _{1 to} U _n and L _{1 to} L _m generated by the counter 51, and based on the counter values, the lighting control signal LD, the clock signal CL, and the exposure control signal AE. , A vertical synchronizing signal VD and a horizontal synchronizing signal HD are generated. That is, the control signal generation unit 52, the upper n bits U ₁ ~U _n of the counter value to generate a clock signal CL for each timing for increasing 1. The control signal generation unit 52, the upper n bits _U 1 ~U _n is a predetermined number _K 1 (> 1) to generate a horizontal synchronizing signal HD in every timing to increase. In this way, the control signal generation unit 52 generates the clock signal CL and the horizontal synchronization signal HD at a constant cycle.

Further, the control signal generator 52 in a constant cycle after the upper n bits U ₁ ~U _n is reset (e.g., 513 cycles of the horizontal synchronizing signal) to generate a vertical synchronizing signal VD and the exposure control signal AE. At this time, the control signal generation unit 52 first turns on the exposure control signal AE immediately after the horizontal synchronizing signal HD is turned on to reset the upper n bits U ₁ ~U _n is then exposed with a constant period of the The control signal AE is turned on. At the same time, the control signal generator 52, a specific number of times the upper n bits U ₁ ~U _n is reset (e.g., 512 times) immediately after the horizontal synchronizing signal HD is turned on, turns on the vertical synchronizing signal VD, then Turns on the vertical synchronizing signal VD at the above-mentioned fixed period. Therefore, the exposure control signal AE is turned on when the upper n bits of the counter value are reset, and exposure in the CMOS image sensor 37 can be started in response to the generation of the counter reset signal RST. In addition, since the period between the generation timing of the exposure control signal AE and the generation timing of the vertical synchronization signal VD is always kept constant, the exposure time for each pixel line of the CMOS image sensor 37 can be secured.

Further, the control signal generator 52 receives the counter reset signal RST, and after the exposure control signal AE is first turned on, the timing at which the exposure of the final pixel line is started, and thereafter the vertical synchronization signal VD is first received. The lighting control signal LD is generated between the turn-on timing. For example, when the exposure start timing of each pixel line is shifted by one period of the horizontal synchronization signal HD, the timing at which the exposure of the final pixel line is started is expressed by the following formula from the time when the exposure control signal AE is turned on:
ΔT = T _HD × (N _L −1)
(In the above formula, T _HD represents the period of the horizontal synchronizing signal HD, and N _L represents the number of pixel lines up to the last pixel line)
Is the timing after the time ΔT has elapsed.

  The HD synchronization reset unit 53 generates a counter reset signal RST for resetting the counter value in the counter 51 after the coin 20 arrives at the imaging position 12c. The HD synchronization reset unit 53 includes an object detection trigger signal TR received from the coin detection circuit 43, a horizontal synchronization signal HD drawn from the control signal generation unit 52, and a trigger reception permission signal received from a TR reception control unit 57 described later. A counter reset signal RST is generated based on TA. Specifically, when receiving the trigger acceptance permission signal TA, the HD synchronization reset unit 53 resets the counter immediately after the horizontal synchronization signal HD is first generated after the object detection trigger signal TR is turned on. A signal RST is generated and output to the counter 51. By doing so, even if the object detection trigger signal TR is generated, the upper n bits of the counter value are reset immediately after the horizontal synchronization signal HD is turned on, so the generation timing of the horizontal synchronization signal HD is shifted. Without a constant period.

  The VD reception control unit 54 receives the object detection trigger signal TR from the coin detection circuit 43 and controls reception of the object detection trigger signal TR. Specifically, when the object detection trigger signal TR is turned on, the VD reception control unit 54 continues to output the VD reception signal to the AND circuit 56 in an on state. Further, the VD reception control unit 54 notifies the TR reception control unit 57 that a trigger reception signal output from the image output control unit 55 described later is in an on state. The TR reception control unit 57 outputs the trigger reception permission signal TA to the HD synchronization reset unit 53 while the trigger reception signal is in the ON state, thereby receiving the object detection trigger signal TR from the coin detection circuit 43. Control to accept. On the other hand, the TR reception control unit 57 stops the output of the trigger reception permission signal TA to the HD synchronization reset unit 53 while the trigger reception signal is in the off state, thereby causing the object detection trigger from the coin detection circuit 43 to be stopped. Control is performed so as not to accept the signal TR. As described above, when the HD synchronization reset unit 53 does not accept the object detection trigger signal TR from the coin detection circuit 43, the counter value reset operation in the counter 51 is not performed.

  The image output control unit 55 receives a signal after performing an AND operation on the VD reception signal from the VD reception control unit 54 and the vertical synchronization signal VD from the control signal generation unit 52 via the AND circuit 56. To do. The signal from the AND circuit 56 is output in the on state if both the VD reception signal and the vertical synchronization signal VD are on, and in the off state if either the VD reception signal or the vertical synchronization signal VD is off. Therefore, the image output control unit 55 receives the output signal in the on state every time the vertical synchronization signal VD is generated after the object detection trigger signal TR is received. The image output control unit 55 outputs the trigger reception signal in an off state until the output signal from the AND circuit 56 is first turned on after the object detection trigger signal TR is received, and during other periods. Then, the trigger acceptance signal is output in the ON state. As a result, the reset interval in the counter 51 is set to be approximately one cycle or more of the vertical synchronization signal VD. As a result, the exposure time of the CMOS image sensor 37 is secured and stable image data can be output.

  Next, generation timings of various signals in the image reading apparatus 1 will be described with reference to FIGS.

As shown in FIGS. 6A to 6B, the exposure control signal AE is turned on when the object detection trigger signal TR is turned on when the arrival of the coin 20 is detected by the coin arrival sensor 41. Then, exposure of the image of the coin 20 in the CMOS image sensor 37 is started. Thereafter, at the timing when the vertical synchronization signal VD is turned on (see FIG. 6C), image data is sequentially output from each pixel line of the CMOS image sensor 37a. Here, the exposure of the first pixel line in the CMOS image sensor 37 is performed at a time TP1 from when the exposure control signal AE is turned on to when the vertical synchronization signal VD is turned on, and then the second time is sequentially shifted by a certain time. exposure time TP2～TPN _L of ~ final pixel line is set (see FIG. 6 (e)).

  Further, the relationship between the horizontal synchronization signal HD and each signal will be described in more detail with reference to FIG. As shown in FIGS. 7A to 7B, even when the object detection trigger signal TR is generated, the generation timing of the horizontal synchronization signal HD is always maintained at a constant period. The exposure control signal AE is turned on immediately after the horizontal synchronization signal HD is first turned on after the object detection trigger signal TR is generated. Further, the vertical synchronization signal VD is turned on immediately after the horizontal synchronization signal HD is turned on a specific number of times (for example, 512 times) after the object detection trigger signal TR is generated. In this case, the exposure of the first pixel line is performed in a period TP1 immediately after the generation of the exposure control signal AE until immediately after the generation of the vertical synchronization signal VD (see FIG. 7E). After the exposure of the first pixel line is completed, image data is output from the first pixel line in one cycle TS1 of the horizontal synchronization signal HD. Further, the exposure and image data output after the second pixel line are shifted by one cycle of the horizontal synchronizing signal HD. Thus, the exposure time of each pixel line is made constant by generating the exposure control signal AE and the vertical synchronization signal VD with reference to the horizontal synchronization signal HD. Furthermore, since the time difference between the generation timings of the vertical synchronization signal VD and the horizontal synchronization signal HD is constant, the image data is not disturbed immediately after the coin 20 is detected, and stable image data output is realized.

  According to the image reading apparatus 1 described above, the illumination light applied to the coin 20 is reflected by the surface of the coin 20 at the imaging position 12c and imaged by the imaging lens 36, and then the image formed is formed. Images are taken by the CMOS image sensor 37. At this time, after the CMOS image sensor 37 is controlled so that exposure is sequentially started for each of the plurality of pixel lines of the CMOS image sensor 37a, triggered by the output of the object detection trigger signal TR which is a detection signal of the coin 20, the final Illumination light is irradiated at the timing after the start of the exposure of the pixel line and before the generation of the vertical synchronization signal VD. As a result, the entire image of the coin 20 moving at the imaging position 12c can be stably captured, and stable imaging data can be output regardless of the conveyance speed of the coin 20. In addition, by starting exposure in accordance with the arrival of the coin 20, there is no need for a complicated control mechanism that is controlled in accordance with the conveyance speed of the imaging target, and the apparatus configuration can be simplified.

  Further, the CMOS image sensor control circuit 42 generates the horizontal synchronization signal HD that defines the output period of the image data at a constant period, and maintains the generation timing of the horizontal synchronization signal HD when the object detection trigger signal TR is output. If such a CMOS image sensor control circuit 42 is provided, when the coin 20 is imaged by the CMOS image sensor 37, the output period of the image data for each pixel line can be maintained within a certain period, and the coin can be detected. It is possible to prevent disturbance of imaging data output immediately after.

Further, a plurality of pixel lines P1 to PN _L covers a substantially matching range with the imaging range of the coin 20 on the light receiving surface of the CMOS image sensor 37a. As a result, since one frame of image data can be generated and processed in accordance with the image of the coin 20, the image reading speed can be improved, and thus random imaging of the reading object can be realized.

(Second Embodiment)
Next, a second embodiment of the present invention will be described focusing on differences from the first embodiment.

  The image reading apparatus 101 according to the second embodiment of the present invention shown in FIG. 8 has a circuit configuration different from that of the image reading apparatus 1 according to the first embodiment. Specifically, the CMOS image sensor 37a includes a CMOS. An image sensor control circuit 142 is connected. The CMOS image sensor control circuit 142 includes a main control circuit 142a that generates a clock signal CL, an exposure control signal AE, a vertical synchronization signal VD, and a horizontal synchronization signal HD for controlling the operation of the CMOS image sensor 37a, and an illumination unit. 14 includes a lighting control circuit 142b that generates a lighting control signal LD that controls the emission timing of irradiation light.

FIG. 9 shows a block diagram of the main control circuit 142a. The main control circuit 142a has the same configuration as the CMOS image sensor control circuit 42 already described, except that the function of the control signal generation unit 152 is different. The control signal generator 152 constantly monitors the counter values U _{1 to} U _n and L _{1 to} L _m generated by the counter 51, and based on the counter values, the clock signal CL, the exposure control signal AE, and the vertical synchronization signal VD. And a horizontal synchronizing signal HD. The functions of generating the clock signal CL, the exposure control signal AE, the vertical synchronization signal VD, and the horizontal synchronization signal HD are the same as those of the control signal generation unit 52 described above. That is, the control signal generation unit 152 does not have a function of generating the lighting control signal LD, and the lighting control circuit 142b generates the lighting control signal LD.

  As shown in FIG. 10, the lighting control circuit 142b includes a counter 151, a count enable control unit 156, AND circuits 153 and 154, and a lighting control signal generation unit 155, and is output from the main control circuit 142a. The clock signal CL, the vertical synchronization signal VD, the horizontal synchronization signal HD, and the object detection trigger signal TR output from the coin detection circuit 43 are input to generate the lighting control signal LD.

  The count enable control unit 156 receives the vertical synchronization signal VD and the object detection trigger signal TR, generates a count enable signal CE having two states of on and off, and outputs the count enable signal CE to the AND circuits 153 and 154. Specifically, the count enable control unit 156 detects the timing at which the vertical synchronization signal VD is first turned on after the object detection trigger signal TR in the on state is input, and turns on the count enable signal CE at that timing. Set to state and output. When the count enable signal CE is turned on and the next vertical synchronization signal VD is inputted in the on state, the count enable control unit 156 changes the count enable signal CE to the off state and outputs it at that timing. In addition, the count enable control unit 156 outputs a counter reset signal for resetting the counter value counted by the counter 151 to the counter 151 every time the ON state object detection trigger signal TR is input.

  The count enable signal CE output from the count enable control unit 156 is input to the AND circuits 153 and 154, and the AND circuit 153 outputs a signal obtained by performing an AND operation on the count enable signal CE and the clock signal CL. The AND circuit 154 outputs signals obtained by performing AND operation on the count enable signal CE and the horizontal synchronization signal HD to the counter 151, respectively. Note that the lighting control circuit 142b may include only one of the AND circuits 153 and 154, but in order to reduce the capacity of the counter 151, it is preferable to include at least an AND circuit 154.

  On the other hand, the counter 151 counts a signal output from either the AND circuit 153 or 154 to generate a counter value CNT and outputs the counter value CNT to the lighting control signal generation unit 155. With such a configuration, the counter 151 causes the clock signal between the time when the first vertical synchronization signal VD is generated and the time when the second vertical synchronization signal VD is generated after the object detection trigger signal TR is turned on. The number of pulses of CL or horizontal synchronizing signal HD is counted. Hereinafter, a case where the counter 151 counts the horizontal synchronization signal HD will be described as an example.

The lighting control signal generation unit 155 sets the generation timing and pulse width of the lighting control signal LD based on the count value CNT input from the counter 151, and illuminates the lighting control signal LD having the generation timing and pulse width. To the unit 14. Specifically, the lighting control signal generating unit 155, the count value CNT is set to timing of generation of the lighting control signal LD at the timing reaches the count CNT ₁ predetermined, the pulse width of the lighting control signals LD horizontal It is set to be a predetermined count number ΔCNT times the period of the synchronization signal HD.

  Here, the generation timing of various signals generated by the image reading apparatus 101 will be described with reference to FIG. First, after the arrival of the coin 20 is detected and the object detection trigger signal TR is turned on (FIG. 11 (a)), the counter 51 of the main control circuit 142a is reset and the vertical synchronization signal VD is generated simultaneously. Thereafter, the vertical synchronization signal VD is generated at a constant cycle (for example, 513 cycles of the horizontal synchronization signal HD) (FIG. 11B).

  In contrast, the count enable control unit 156 of the lighting control circuit 142b generates the first vertical synchronization signal VD and the second vertical synchronization signal VD after the object detection trigger signal TR is turned on. Count enable signal CE is generated between them (FIG. 11 (c)).

The lighting control signal generator 155 of the lighting control circuit 142b generates the generation timing and pulse of the lighting control signal LD based on the count number of the horizontal synchronization signal HD (FIG. 11 (d)) while the count enable signal is turned on. Set the width. That is, the lighting control signal generation unit 155 sets the generation timing of the lighting control signal LD so as to be synchronized with the timing at which the count value CNT in the counter 151 coincides with CNT ₁ and sets the pulse width of the lighting control signal LD to the count value. The time is set while CNT increases by ΔCNT (FIG. 11 (e)). Note that these count numbers CNT ₁ and ΔCNT are generated when the lighting control signal LD is generated between the exposure start timing of the final pixel line PN _L (see FIG. 4) and the second vertical synchronization signal VD. Is set in advance so that Here, the exposure start timing of the last pixel line PN _L is a horizontal synchronizing signal after the occurrence of the already mentioned manner exposure start signal AE (Fig. 11 (a) synchronized with the first occurrence of the vertical synchronization signal VD in) Since the generation timing of the vertical synchronization signal VD is determined in accordance with the cycle of HD and is synchronized with the generation timing of every predetermined cycle of the horizontal synchronization signal HD, the count numbers CNT ₁ and ΔCNT are set to appropriate values that meet the above conditions in advance. It is possible to determine.

According to the image reading apparatus 101 described above, even if the frequency of the control signal such as the clock signal CL, the vertical synchronization signal VD, and the horizontal synchronization signal HD for controlling the CMOS image sensor 37a is changed, all the pixel lines P1. the to PN _L of exposure time and the irradiation timing of the illumination light can be set properly, the coin 20 as compared with the case of controlling the irradiation timing of the illumination light by using a timer function using conventional IC such as More stable imaging of the whole image is possible.

Figure 12 is a timing chart showing the image reading object detection trigger signal TR generated in the apparatus 101, the lighting control signals LD, and the exposure time of each pixel line P1 to PN _L. Thus, the image in the reading apparatus 101, the irradiation timing of the illumination light regardless of the frequency of the clock signal CL are housed within the exposure time TP1～TPN _L of all pixel lines P1 to PN _L, the coin 20 The entire image is captured stably (FIG. 14 (a)).

On the other hand, in FIG. 13 shows an object detection trigger signal TR generated by using the timer function, the lighting control signals LD, and a timing chart showing the exposure time for each pixel line P1 to PN _L. Here, it is assumed that the generation timing of the lighting control signal LD is set by measuring the time after the generation of the object detection trigger signal TR using a real-time timer function. In such a case, when the frequency of the clock signal CL is increased by the substitution or the like of the CMOS imaging device 37a, an exposure time TP1～TPN _L of each pixel line P1 to PN _L (FIG. 13 (c)) and their The shift is shortened, and the generation timing of the lighting control signal LD is outside the exposure time of some pixel lines (FIG. 13B). As a result, the image of the coin 20 to be imaged is an image. A part of the upper part of FIG. 14 is missing (FIG. 14B).

  In addition, this invention is not limited to embodiment mentioned above. For example, the lighting control signal generation unit 155 sets the generation timing and the pulse width of the lighting control signal LD based on the count value CNT obtained by counting the horizontal synchronization signal HD. You may set based on. In this case, the illumination light irradiation timing can be set with higher accuracy.

1 is a perspective view showing an embodiment of an image reading apparatus according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the image reading apparatus in FIG. 1. FIG. 2 is a block diagram of the image reading apparatus in FIG. 1. It is a figure which shows the positional relationship of the light-receiving surface and pixel line of the CMOS image sensor of FIG. 1, and the imaging range of a coin. It is a block diagram of the CMOS image sensor control circuit of FIG. FIG. 2 is a diagram illustrating generation timings of various signals in the image reading apparatus of FIG. 1, (a) is an object detection trigger signal, (b) is an exposure control signal, (c) is a vertical synchronization signal, and (d) is a diagram. The lighting control signal LD, (e) is a timing chart showing the exposure time for each pixel line. FIG. 2 is a diagram illustrating generation timings of various signals in the image reading apparatus of FIG. 1 in more detail, (a) is an object detection trigger signal, (b) is a horizontal synchronization signal, (c) is an exposure control signal, (d ) Is a vertical synchronizing signal, and (e) is a timing chart of the exposure time and image data output time for each pixel line. It is a block diagram of the image reading apparatus which is 2nd Embodiment of this invention. It is a block diagram of the main control circuit of FIG. It is a block diagram of the lighting control circuit of FIG. FIG. 9 is a diagram illustrating generation timings of various signals in the image reading apparatus in FIG. 8, (a) is an object detection trigger signal, (b) is a vertical synchronization signal, (c) is a count enable control signal, and (d). Is a timing chart showing a horizontal synchronization signal, and (e) is a lighting control signal. FIG. 9 is a diagram illustrating generation timings of various signals in the image reading apparatus of FIG. 8, (a) is an object detection trigger signal, (b) is a lighting control signal, and (c) is an exposure time for each pixel line. It is a timing chart. It is a figure which shows the production | generation timing of the various signals in the comparative example of this invention, (a) is a target object detection trigger signal, (b) is a lighting control signal, (c) is a timing which shows the exposure time for every pixel line. It is a chart. (A) is a figure which shows the image of the image of the coin imaged with the image reader of FIG. 8, (b) is a figure which shows the image of the image of the coin imaged in the comparative example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Image reader, B ... Conveyance path, 12c ... Imaging position, 14 ... Illumination part, 20 ... Coin (reading object), 36 ... Imaging lens, 37 ... CMOS image sensor, 41 ... Coin arrival sensor (detection part) ), 42 ... CMOS image sensor control circuit 44 image data acquisition control circuit, P1 to PN L _... pixel lines, VD ... vertical synchronization signal, HD ... horizontal sync signal, TR ... object detection trigger signal (detection signal), LD ... lighting control signal, W P _... imaging range, AE ... exposure control signal.

Claims (4)

In an image reading apparatus that reads an image of the surface of a reading object conveyed along a predetermined conveyance path,
In synchronization with the generation of the lighting control signal, an illumination unit that irradiates illumination light to the imaging position on the conveyance path;
An imaging lens that forms an image of the illumination light reflected by the reading object at the imaging position;
A detection unit that detects that the reading object has arrived at the imaging position and outputs a detection signal;
In synchronism with the generation of the exposure control signal, the image formed by the imaging lens is sequentially exposed from the first pixel line to the final pixel line, so that each of the first pixel line to the final pixel line is started. sets the exposure period to be shifted from each other, the final pixel in synchronism with the generation of exposure after the start of the vertical sync signal on line sequentially shifted by exposing ends of the first pixel line to the last pixel line, wherein A CMOS image sensor that starts outputting image data for each pixel line in the order of exposure start;
A CMOS image sensor control circuit that generates the lighting control signal, the exposure control signal, and the vertical synchronization signal;
The CMOS image sensor control circuit generates the exposure control signal in response to the output of the detection signal, and outputs the lighting control signal between the exposure start timing of the final pixel line and the generation timing of the vertical synchronization signal. It is generated,
The imaging lens and the CMOS image sensor are configured to store an image of the reading object in image data from the first pixel line to the final pixel line. Image reading device. The CMOS image sensor control circuit generates a horizontal synchronization signal that defines an output period of the image data at a constant period, and the generation timing of the horizontal synchronization signal is not shifted by the output of the detection signal. Maintain the horizontal sync signal at a fixed period ,
The image reading apparatus according to claim 1. The final pixel line is located at the outer edge of the imaging range of the reading object in the entire pixels of the CMOS image sensor.
The image reading apparatus according to claim 1, wherein the image reading apparatus is an image reading apparatus. The CMOS image sensor control circuit determines the generation timing of the lighting control signal based on a control signal synchronized with the exposure start timing of the plurality of pixel lines and the generation timing of the vertical synchronization signal;
The image reading apparatus according to claim 1, wherein the image reading apparatus is an image reading apparatus.

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