JP4929610B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor having a deep planar type main junction such as a MOSFET (insulated gate field effect transistor), IGBT (insulated gate bipolar transistor), super junction semiconductor device, BJT (bipolar junction transistor), thyristor, or diode. More particularly, the present invention relates to a semiconductor device whose characteristics are improved by gettering heavy metal impurity ions made of an undesirable transition metal such as copper or iron outside the region of the semiconductor device, and a method for manufacturing the same.

  In the process of semiconductor single crystal growth, wafer processing of the single crystal material, and impurity introduction and diffusion steps in the wafer process for forming semiconductor device (chip) regions on the single crystal wafer It is inevitable that not only impurities but also heavy metal impurities and various crystal defects are introduced. Among impurities to be introduced, in particular, heavy metal impurity ions made of transition metals such as copper and iron contained in the inside or surface of the wafer and contained in the doping material itself are introduced into the wafer by the above-described process. In many cases, a deep level is formed near the center of the band gap of the semiconductor crystal. As a result, it is known that when such heavy metal impurity ions are taken in and fixed in stacking faults existing in the pn junction formed in the impurity introduction and diffusion process, the pn junction leakage current is increased. Yes.

Furthermore, when these heavy metal impurities adhere to the wafer surface, the heavy metal impurities generally have a very large diffusion coefficient in silicon, so it is very easy even in the wafer process even at a temperature lower than the normal diffusion temperature. It will diffuse deep into the wafer in a short time. Depending on conditions, penetration diffusion from the wafer surface to the wafer back surface is also possible.
In order to remove the heavy metal impurities that are easily diffused deep into the wafer in this way and become electrically active from the semiconductor element formation region of the semiconductor substrate, and to make this semiconductor element formation region a more complete crystal region, Conventionally, various methods for forming various gettering sinks as shown in FIG. 2 (stacking defects 101 by sandblasting, crystal transition defects 102 by laser irradiation or ion implantation, and crystal strain 103 using a difference in thermal expansion coefficient such as a silicon nitride film) And defects 104 caused by oxygen precipitation are widely known. Such a gettering sink formation technique basically separates contaminating impurities or crystal defects from the semiconductor element formation region, moves them to a place having a small influence on properties (gettering sink), and fixes them ( This is a method for improving the characteristics of the semiconductor element and the yield rate by gettering and capturing. The gettering sink described above can be divided into intrinsic gettering and extrinsic gettering as described below.

The gettering sink 104 formed by utilizing the precipitation of oxygen contained in a large amount in a silicon wafer manufactured by the CZ pulling method is called intrinsic gettering (intrinsic gettering). In intrinsic gettering, the micro atoms and stacking faults formed by the oxygen atoms incorporated in the silicon crystal being precipitated inside by heat treatment are used. Such stacking faults have the property of effectively gettering the heavy metal impurity atoms. The intrinsic gettering (intrinsic gettering) method is characterized in that the oxygen concentration in the portion close to the surface of the wafer is removed by outward diffusion, and heavy metal is gettered by the precipitated oxygen inside the wafer.
This method is widely used in semiconductor elements such as CMOS integrated circuits and bipolar ICs as shown in FIG. 3, and is a general method. Interstitial oxygen present in the wafer substrate 200 produced mainly by the chocolate ski method (CZ method) is precipitated in the wafer bulk by heat treatment, and the oxygen precipitates or crystal defects induced thereby are gettering sinks. While being used as (IG) 202, on the other hand, in the vicinity of the wafer surface where the semiconductor element is formed, the interstitial oxygen is diffused outward by performing heat treatment in a non-oxidizing atmosphere, and the denominated zone (DZ) 201 is obtained. This is a method for improving the semiconductor element characteristics and the yield rate by using the DZ as the semiconductor element formation region 204.

On the other hand, a method of forming a strain field by forming a high-concentration impurity diffusion layer, polycrystalline silicon, a damage layer, etc. on the back surface of the wafer and fixing heavy metal impurity atoms there is extrinsic gettering (extrinsic) There are various methods as shown in FIG. Also in the semiconductor element shown in FIG. 3, processing called exogenous gettering (EG-extrinsic gettering) 203 is performed on the back side of the wafer.
The following are known documents related to gettering.
There is a description of an invention that effectively getsters contaminants such as heavy metals by forming a gettering region in an element isolation region by ion implantation (Patent Document 1). Document relating to an invention for preventing re-release of gettered heavy metal (Patent Document 2). An invention for forming a region having a high gettering effect due to a high impurity concentration region is known (Patent Document 3). An invention is described in which a high impurity concentration layer is formed in order to getter heavy metal impurities contained in an element formation layer (Patent Document 4).
JP 11-297703 A Japanese Patent No. 3296304 JP 2000-315736 A Japanese Patent No. 3539374

  However, since the depth of a defect-free layer called a denuded zone (DZ) that can be formed by heat treatment in a non-oxidizing atmosphere is usually only about several μm deep from the surface, the perspective view of FIG. SJ (Super Junction) -MOSFET and other RB (Reverse Blocking) -IGBT as shown in FIG. 1 in the bulk direction of the wafer 300 in a pn junction over a depth of several tens to several hundreds of μm In a high voltage semiconductor device in which 301 is formed, the effect can hardly be expected. In addition, if a deep DZ (defect-free layer) that exceeds several μm depth and reaches several tens of μm or several hundred μm is formed, a large amount of heat treatment temperature and heat treatment time are required. From a practical point of view, it must be said that it is practically impossible. Further, assuming that the semiconductor element having the above-described deep pn junction is fabricated in the bulk while maintaining the normal shallow DZ depth, in this semiconductor element, the depletion layer spreads by applying a reverse bias to the pn junction. Since the intrinsic gettering sink 302 remains in the depletion layer region, the gettering sink itself becomes a source of pn junction leakage current and the semiconductor element characteristics are deteriorated.

Furthermore, when the wafer is ground in the wafer 400 thinning step after the latter half of the wafer process (FIG. 5C) of the semiconductor device as shown in the cross-sectional views of FIGS. At the same time, the layer including the gettering sink 401 formed by sand blasting, ion implantation, etc. formed by the arrow 404 shown in FIG. 5A and effective against the contaminated metal 402 in FIG. 5B is also removed. As a result, the gettering ability of the metal impurity 403 mixed in the wafer process after thinning the wafer 400 (FIG. 5D) is reduced, and as a result, the impurity metal 403 diffuses into the semiconductor active region. As a result, there is a negative effect that the semiconductor element characteristics and non-defective product rate are lowered by fixing.
In short, a deep pn junction is formed in the bulk direction (depth direction) of the wafer, such as SJ (Super Junction) -MOSFET or RB (Reverse Blocking) -IGBT, and the wafer is thin. In a high-voltage semiconductor device that involves an etching process, it is difficult to form an effective intrinsic gettering sink (IG), and an extrinsic gettering sink (EG) formed on the back surface of the wafer is also formed after the wafer thinning process. That the effect is lost by the removal means that there is a cause of occurrence of problems such as the above-mentioned characteristics and a decrease in the yield rate.

  The present invention has been made in view of the above points, and can easily produce a gettering sink that does not affect a pn junction or a surface device functional region formed in a wafer bulk, and a thinning step in a wafer process. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device that have effective gettering ability and can prevent deterioration in semiconductor element characteristics and reduction in yield rate.

According to the present invention of claim 1, wherein the range of patent claims, on one main surface of the silicon semiconductor substrate to the (100) surface orientation, by wet anisotropic etching, the outer periphery of the semiconductor element forming region A trench having a {111} plane as a side wall and a {100} plane as a bottom is formed, and a hillock is formed on the bottom, and then the trench is backfilled with polysilicon or a silicon epitaxial layer. A manufacturing process in which a required functional region is sequentially formed in an element formation region and the required functional region is sequentially formed in the semiconductor element formation region is formed after the required functional region is formed on one main surface, and then the other main surface The above object can be achieved by forming a semiconductor device in which a required functional region is formed on the other main surface after grinding .

According to the present invention of claim 2, wherein the range of patent claims, wherein the trench, the claims are formed by etching with TMAH (tetramethylammonium hydroxide) aqueous ammonia solution or 15% or less of low density Preferably, the method of manufacturing a semiconductor device according to claim 1 is used.
According to the third aspect of the present invention, the trench has a pattern along a direction [110] and an equivalent direction <110> on a silicon semiconductor substrate having a main surface of (100). Claims formed by wet anisotropic etching with an alkaline solution so that the trench sidewalls are parallel to the surface (111) and its equivalent surface {111} after forming an etching mask having It is good also as a manufacturing method of the semiconductor device of claim | item 1 or 2 .

According to the present invention of claim 4 , the trench is constituted by a plane including a (111) plane, a (1-1-1) plane, and a bottom plane (100) plane of the trench side wall, and the bottom plane More preferably, the method of manufacturing a semiconductor device according to any one of claims 1 to 3 , wherein a polysilicon or epitaxial silicon film is formed on a (100) plane.
According to the present invention of claim 5 , by adjusting the depth of the inverted trapezoidal trench and the mask opening width in wet anisotropic silicon etching with an alkaline solution, the (100) plane at the bottom of the trench is adjusted. It is desirable to use the method for manufacturing a semiconductor device according to any one of claims 1 to 4 for controlling the width of the semiconductor device.
According to the present invention as set forth in claim 6, the semiconductor according to any one of claims 1 to 5 , wherein a thermal oxidation treatment is applied after filling the trench with a silicon layer. It is preferable to adopt a method for manufacturing an apparatus.

  According to the present invention, a gettering sink that does not affect the pn junction and surface device functional region formed in the wafer bulk can be easily manufactured, and the gettering capability is effective even after the thinning process in the wafer process. It is possible to provide a semiconductor device and a method for manufacturing the same that can prevent deterioration in element characteristics and reduction in yield rate.

1 is a cross-sectional view of a reverse blocking insulated gate bipolar transistor (hereinafter abbreviated as reverse blocking IGBT) according to the present invention, FIG. 6 is a perspective view of a principal part of a wafer including a semiconductor device according to the present invention, and FIG. FIG. 8 is an essential part cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention in the order of steps, FIG. 8 is a SEM photograph showing a trench etching state in the method of manufacturing a semiconductor device of the present invention, and FIG. 9 is an enlarged view of a trench portion of FIG. It is a SEM photograph figure.
In order to achieve the above object, a semiconductor device according to the present invention, for example, SJ (super junction) -MOSFET, RB (Reverse blocking) -IGBT, or the like in the wafer bulk direction (depth direction). In the middle of the wafer process of the semiconductor device in which a deep pn junction is formed, the region in which the semiconductor element characteristics are not affected or finally removed even if crystal defects exist, ie, isolation Wet silicon using an alkaline solution such as an aqueous ammonia solution or an aqueous solution of TMAH (tetramethylammonium hydroxide) having a selective etching property with respect to the crystal direction from directly above the wafer surface region of the layer region (cutting region including the scribe line region). Trench (reverse by anisotropic etching) Forming a groove) shape type, by crystal defects such as stacking faults and dislocations within the trenches (grooves) are filled with epitaxial silicon thin film or polycrystalline silicon thin film that contains a large number to form a gettering sink.

  FIG. 6 shows a schematic perspective view of a wafer for explaining the principle of the present invention. Etching is performed so as to introduce crystal defects (hillocks) in the trench bottom surface 3 in the vicinity of the surface on the isolation region (including the scribe line) 5, and then the epitaxial silicon is filled to form a pattern so as to surround the semiconductor element formation region 4. Make a gettering sink 5-1. In some cases, an additional oxidation treatment is performed to widen the dislocation network to increase the defect density, thereby further improving the gettering ability. Contaminated metals, interstitial oxygen, interstitial silicon, atomic vacancies and the like mixed in the subsequent wafer process are taken into (gettering) and fixed in the gettering sink 5-1. As a result of such gettering, there is an effect that the deterioration of the semiconductor device characteristics and the non-defective product rate due to the metal contamination, interstitial oxygen, interstitial silicon, atomic vacancies and the like are greatly improved.

FIG. 1 is a schematic cross-sectional view showing a reverse blocking IGBT according to the present invention. Since the gettering sink 5-1 is partially formed in the isolation region 5 including the scribe line, the deterioration of the semiconductor element characteristics and the yield rate are shown. There is no decline. Also, instead of setting a new location for the gettering sink 5-1, the area to be removed as an existing scribe line called the separation area 5 is also used as the gettering sink area, so that the throughput (chip from the wafer) The effect is that there is no reduction in the number of removals.
Furthermore, since a gettering sink 5-1 is formed relatively close to the surface (bottom surface of the trench) for a thick wafer at the beginning, the gettering sink is also obtained after the back surface is ground and removed in the wafer thinning process. All of the 5-1 is not removed, and the gettering ability is maintained.

In the formation of the trench 5-2 by wet anisotropic silicon etching using the alkaline solution, when an aqueous ammonia solution is used, pyramidal irregularities called hillocks 6 are formed at almost all concentrations in the (100) plane 3 on the bottom of the trench 5-2. Occurs. FIG. 8 and FIG. 9 which is an enlarged view thereof show an SEM photograph of the trench 5-2 in which hillocks 6 are positively generated on the bottom surface of the trench 5-2 by wet anisotropic silicon etching with an aqueous ammonia solution. In these photographic drawings, the above-mentioned hillock 6 is a pyramidal protrusion in the trench. When the TMAH solution is used, the flatness of the surface depends on the solution concentration. When the solution concentration is low, the density of hillocks 6 increases. Specifically, hillocks 6 are easily generated at a concentration of 15% or less, and the density is increased.
When the inside of the trench 5-2 in which the hillock 6 is formed on the bottom surface is filled with the epitaxial silicon 5-3, an epitaxial stacking fault or a crystal defect such as a dislocation occurs from the hillock 6 as a starting point. Crystal defects having a density corresponding to the hillock 6 density are introduced into the filled epitaxial silicon 5-3. Further, by controlling the concentration of alkali solution used for etching and the etching temperature, the size and density of dislocations to be introduced can be controlled to quantitatively control the gettering ability. When the trench 5-2 is filled with a polysilicon film, epitaxial stacking faults are not introduced, but a crystal grain boundary serves as a gettering sink, so that gettering capability is obtained.

Further, after the hillock 6 is formed on the bottom surface, the trench 5-2 is filled with the epitaxial silicon thin film 5-3 or the polysilicon thin film that contains a large amount of crystal defects such as stacking faults and dislocations. In addition, the gettering ability can be further increased by performing thermal oxidation treatment and expanding the dislocation network by interstitial silicon generated by the thermal oxidation.
Since the epitaxial stacking fault generated from the hillock 6 is formed on the (111) plane and the {111} plane 9 equivalent to the (111) plane, the side wall of the trench formed by alkali wet etching intersects with the epitaxial stacking fault. There is nothing. That is, since the epitaxial stacking fault is formed in parallel to the pn junction 10-1 formed in parallel to the trench sidewall and does not penetrate, the junction leakage current can be greatly reduced.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 is a schematic cross-sectional view showing a reverse blocking IGBT according to the present invention. Wet anisotropy with an aqueous ammonia solution having a main surface of (100) 8 wafers, opening a trench mask along the [110] direction and the equivalent direction <110>, and having selective etching properties with respect to the crystal direction An inverted trapezoidal trench 5-2 is formed by silicon etching. Etching is not performed until the {111} planes 9 on both side walls intersect, and the (100) bottom surface is exposed in the trench 5-2, and hillocks 6 are actively formed on the bottom surface. The appearance density of the hillock 6 can be controlled by changing the concentration of the aqueous ammonia solution. Thereafter, when the trench 5-2 is filled with the epitaxial silicon film 5-3, the trench 5-2 starts with the hillock 6 and contains an extrinsic gettering (IE) sink 5-1 containing a large amount of epitaxial stacking faults. Is formed. Since the gettering sink 5-1 is gettered with heavy metals mixed during the wafer process, metal contamination is suppressed in the semiconductor element formation region 4, the P ⁺ isolation layer 7, and the pn junction 10, so that the junction is greatly increased. There is an effect that the leak and the yield rate are improved. This Excitrinic Gettering (IE) sink 5-1 is a P ⁺ for preventing the punch-through by the depletion layer reaching the dicing surface when a reverse bias is applied in the reverse blocking IGBT, that is, expressing the reverse blocking capability. The separation layer is also formed for the purpose, and is filled with epitaxial silicon 5-3 introduced with a p-type dopant such as boron, and further spread by diffusion by heat treatment to form the P ⁺ separation layer 7. As shown in FIG. 1, the trench sidewall is the {111} plane 9, while the epitaxial stacking fault is also formed in the {111} plane 9, so that the stacking fault is parallel to the trench sidewall as described above. Penetration through the pn junction 10-1 formed in the first step is suppressed, and as a result, an increase in leakage current can be greatly reduced. Thereafter, a MOS gate structure 11 and a breakdown voltage structure 12 positioned between the MOS gate structure 11 and the P ⁺ isolation layer 7 are formed in the semiconductor element formation region 4 surrounded by the trench 5-2. After the main surface is polished to a required thickness, a p + collector layer 13 and a collector electrode (not shown) are formed to complete the reverse blocking IGBT.

Next, the manufacturing method of the semiconductor device concerning this invention is demonstrated using FIG.
This embodiment is a reverse blocking IGBT having a withstand voltage of 600V. An oxide film 22 having a thickness of 0.15 μm or a nitride film having a thickness of 0.03 μm on one (100) main surface 21 of the FZ-n type silicon substrate 20 having a thickness of 525 μm and an impurity concentration of 1.5 × 10 ¹⁴ cm ^−3. Gettering having a pattern along the direction [110] and an equivalent direction <110> with an opening width of 100 μm on the outer periphery of the semiconductor element formation region 23 in which a MOS structure and a breakdown voltage structure are formed in a later step. An etching mask for the region 24 is formed (FIG. 7A).
Next, using a 5% solution of TMAH (tetramethylammonium hydroxide), the trench 26 having a (100) bottom surface 25 with a side wall of {111} plane and a depth of 88 μm is formed by etching at 80 ° C. for 3 hours. To do. (FIG. 7B). The density and size of hillocks can be controlled by adjusting the liquid type, concentration, and liquid temperature. Hillocks are pyramidal protrusions composed of crystal planes, and are easily exposed to the (100) bottom surface 25 by wet anisotropic etching from the (100) surface 21 of silicon (FIG. 8 and FIG. 9 which is an enlarged view thereof). Shows a pyramid-shaped hillock).

After the epitaxial silicon 27 doped with boron is deposited and formed by a normal silicon epitaxial growth technique (FIG. 7C), CMP is performed to flatten the surface using the etching mask oxide film 22 as a stop detection film. . The epitaxial silicon deposition layer 27 has both functions of a P ⁺ isolation layer and a gettering layer that have a reverse blocking breakdown structure (FIG. 7D). In the case of a boron-doped polysilicon deposition layer, boron is diffused by heat treatment to form a P ⁺ isolation layer.
Hereinafter, in the case of forming the reverse blocking IGBT, the manufacturing process after the formation of the gettering sink described above will be described, but since it is the same as the known technique, it will be simply described. After removing the etching mask oxide film 22, a gate oxide film 11-1 and a polysilicon gate electrode 11-2 are formed on one main surface 21 side surrounded by the P ⁺ isolation layer 7 as shown in FIG. To do. Then the polysilicon 200 minutes at 1100 ° C. The ^{p +} well layer of the gate electrode 11-2 and the insulating oxide film as a mask and the p base layer (channel layer) 11-3 respectively 120 minutes ion implantation of boron at 1150 ° C. And by the required drive diffusion. At this stage, an effect of reducing the density of crystal defects formed in the operation region of the IGBT by the gettering layer 5-1 can be obtained. Next, an n ⁺ emitter layer 11-4 and a second p ⁺ layer are formed by ion implantation of arsenic and boron, respectively, and the implanted ions are activated by annealing heat treatment at 1000 ° C. for 30 minutes. Next, a non-illustrated emitter electrode and a passivation film made of a polyimide film or the like are formed by the same method and pattern as a normal planar gate type IGBT. Furthermore, in order to reduce the reverse leakage current of the IGBT, an electron beam may be introduced at 6 Mrad. In order to increase the speed, electron beam irradiation or helium irradiation which functions as a lifetime killer may be performed.

Next, the back surface is shaved so that the silicon substrate 1 has a thickness of about 100 μm, and chemical etching or chemical mechanical polishing (CMP) is added to remove stress such as a grinding strain layer formed by the grinding. Finally, the thickness of the FZ silicon substrate is set to about 80 μm, and the p ⁺ type separation layer 7 is exposed on the cut surface.
Next, boron having a dose of 5 × 10 ¹³ cm ⁻² is ion-implanted into the back surface, and low-temperature annealing is performed at about 350 ° C. for about 1 hour, and the peak concentration of activated boron is 1 × 10 ¹⁷ cm ^−3. The back surface p ⁺ collector layer 13 having a thickness of about 1 μm is formed. As a result, the back surface p ⁺ collector layer 13 and the p ⁺ type isolation layer 7 are conductively connected.
Next, when a collector electrode (not shown) is formed to be in ohmic contact and the silicon substrate is cut at the center of the gettering layer, a reverse blocking IGBT according to an embodiment of the present invention is manufactured.

The principal part sectional view of reverse blocking IGBT concerning the present invention, Configuration diagram showing various conventional gettering methods, Schematic sectional view of conventional CMOS and bipolar IC, A perspective view of a conventional superjunction semiconductor device, Manufacturing process diagram of a conventional semiconductor device showing the gettering effect when back grinding is involved, The perspective view which shows the gettering structure concerning this invention, Sectional drawing which shows the manufacturing method of the gettering structure concerning this invention, SEM photograph showing anisotropic etching for gettering structure according to the present invention FIG. 8 is an enlarged SEM photograph of FIG.

Explanation of symbols

1, 20 Silicon substrate 5, 24 Separation region,
5-1 Gettering sink 5-2, 26 Trench 5-3, 27 Epitaxial silicon 3, 25 Trench bottom surface 4, 23 Semiconductor element formation region 6 Hillock 7 P ⁺ Isolation layer 8, 21 Main surface of semiconductor substrate, (100) Surface 9 {111} surface 10, 10-1 pn junction 11 MOS structure 11-1 gate oxide film 11-2 polysilicon electrode 11-3 p base region, channel formation region 11-4 n emitter region 12 breakdown voltage structure 13 collector layer 22 Oxide film.

Claims (6)

One main surface of a silicon semiconductor substrate having a (100) surface as a main surface is formed by wet anisotropic etching on the outer periphery of the semiconductor element formation region with the {111} surface as a side wall and the {100} surface as a bottom surface. said bottom surface hillocks formed on to form a trench and backfilled subsequent said trench polysilicon or silicon epitaxial layer, then, sequentially forming a desired functional area in the semiconductor device forming region, said semiconductor element A manufacturing process for sequentially forming a required functional region in a forming region forms the required functional region on one main surface, then forms the required functional region on the other main surface after grinding the other main surface. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the trench is formed by anisotropic etching using an aqueous ammonia solution or a TMAH (tetramethylammonium hydroxide) aqueous solution having a low concentration of 15% or less. In the trench, after forming an etching mask having a pattern along a direction [110] and an equivalent direction <110> on a silicon semiconductor substrate whose main surface is a (100) plane, the trench side wall is a (111) plane. 3. The method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor device is formed by wet anisotropic etching with an alkaline solution so as to be parallel to a {111 } plane equivalent thereto. The trench is constituted by a plane including a {111} plane equivalent to a (111) plane and a bottom (100) plane as a trench sidewall, and polysilicon or epitaxial silicon is formed on the bottom (100) plane. A method for manufacturing a semiconductor device according to any one of claims 1 to 3 . By adjusting the depth and the mask opening width of the inverted trapezoid-shaped trench in the wet anisotropic silicon etching using an alkali solution, according to claim 1 to 4, characterized in that to control the width of the (100) plane of the trench bottom A manufacturing method of a semiconductor device given in any 1 paragraph. After filling the trench with a silicon layer, a method of manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that applying a thermal oxidation process.