JP4925363B2 - Polarity switching circuit and power supply unit - Google Patents

Polarity switching circuit and power supply unit Download PDF

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JP4925363B2
JP4925363B2 JP2008522467A JP2008522467A JP4925363B2 JP 4925363 B2 JP4925363 B2 JP 4925363B2 JP 2008522467 A JP2008522467 A JP 2008522467A JP 2008522467 A JP2008522467 A JP 2008522467A JP 4925363 B2 JP4925363 B2 JP 4925363B2
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output terminal
switch
voltage
power supply
input terminal
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JPWO2008001644A1 (en
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正 松本
祥二 小伊勢
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Panasonic Corp
Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H02H11/003—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection using a field effect transistor as protecting element in one of the supply lines

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Description

本発明は、2本の給電導体に直流電圧を与える直流電源へ接続され、この直流電源の極性と給電導体の極性との整合を図るための極性切換回路、及びこの極性切換回路を備える給電ユニットに関するものである。   The present invention is connected to a DC power supply that applies a DC voltage to two power supply conductors, a polarity switching circuit for matching the polarity of the DC power supply and the polarity of the power supply conductor, and a power supply unit including the polarity switching circuit It is about.

近来、住宅やビル等の施設内において、直流電源にて動作する電気機器が多数使用されることに伴って、2本の給電導体で構成される一つの給電システムに複数の電気機器を並列に接続する必要性が高くなっており、給電システムに接続される電気機器が増加するにつれて、この給電システムに直流電源を追加することが要求される。この場合は、直流電源の極性を、給電システムの極性に対応させるための極性切換回路を使用することが望まれる。   In recent years, with the use of many electric devices that operate with a DC power source in facilities such as houses and buildings, multiple electric devices are connected in parallel to a single power supply system that consists of two power supply conductors. As the necessity for connection increases and the number of electrical devices connected to the power supply system increases, it is required to add a DC power source to the power supply system. In this case, it is desirable to use a polarity switching circuit for making the polarity of the DC power supply correspond to the polarity of the power feeding system.

日本特許公開公報特開平５−３０６４１号は、直流電源で動作する負荷に正しい極性で直流電圧源を接続するための極性切換回路を開示している。この極性切換回路は、給電ラインと直流電源との間に配置され、直流電源に接続される一対の入力端子と、負荷に接続される一対の出力端子とを備え、入力端子の極性の極性が不明、即ち、入力端子の一方が直流電源の正極か負極のどちらに接続されているかが不明であっても、出力端子の一方には必ず直流電源の正極が接続されるように、極性を切り替えるように構成されている。このため、出力端子の一方は負荷の正極に接続される正極端子に、他方は負荷の負極に接続される負極端子と設定され、負荷に対して正しく接続されていることが必要となる。従って、直流電源を給電ラインに追加する場合に、直流電源と負荷とを正しい極性で接続する場合、工事を行う者は、出力端子を間違えることなく給電導体の正極と負極側にと接続する必要があり、この極性の確認が面倒であるという問題がある。一方、この極性切換回路が予め全ての負荷に対して含まれている場合は、この極性切換回路の特性を活用して、極性の確認を行わずに直流電源を追加することができるが、一般に、一つの給電システムに接続される負荷の数はここに接続される直流電源の数より多いため、全ての負荷にこのような極性切換回路を設けることは、システム全体のコスト上昇の要因となり、更には多種多様な負荷を接続できるというシステムの自由度を損なうという問題がある。
Japanese Patent Application Laid-Open No. 5-30641 discloses a polarity switching circuit for connecting a DC voltage source with a correct polarity to a load operating with a DC power supply. This polarity switching circuit is disposed between the power supply line and the DC power source, and includes a pair of input terminals connected to the DC power source and a pair of output terminals connected to the load, and the polarity of the polarity of the input terminal is Even if it is unknown, that is, whether one of the input terminals is connected to the positive electrode or the negative electrode of the DC power supply, the polarity is switched so that the positive electrode of the DC power supply is always connected to one of the output terminals. It is configured as follows. For this reason, one of the output terminals is set as a positive electrode terminal connected to the positive electrode of the load, and the other is set as a negative electrode terminal connected to the negative electrode of the load, and needs to be correctly connected to the load. Therefore, when a DC power supply is added to the power supply line, if the DC power supply and the load are connected with the correct polarity, the person performing the work must connect the positive and negative sides of the power supply conductor without making a mistake in the output terminal. There is a problem that confirmation of this polarity is troublesome. On the other hand, when this polarity switching circuit is included in advance for all loads, a DC power supply can be added without checking the polarity by utilizing the characteristics of this polarity switching circuit. Since the number of loads connected to one power supply system is larger than the number of DC power supplies connected thereto, providing such a polarity switching circuit for all loads is a factor in increasing the cost of the entire system. Furthermore, there is a problem that the degree of freedom of the system that various loads can be connected is impaired.

本発明は上記の問題点に鑑みて為されたものであり、その目的とするところは、負荷が接続されている給電システムの極性を確認せずとも、直流電源を正しい極性で給電システムに追加することができる極性切換回路を提供することである。

本発明に係る極性切換回路は、直流電源と負荷との間に介在して、負荷に繋がる2本の給電導体へ直流電源を接続するものであり、
上記直流電源の正極に接続される正入力端子ＩＮ＋と、
上記直流電源の負極に接続される負入力端子ＩＮ−と、
上記2本の給電導体の一方に接続される第1出力端子OUT1と、
上記2本の給電導体の他方に接続される第２出力端子OUT２と、
上記正入力端子と上記第1出力端子との間に挿入した第1スイッチＳＷ１と、
上記正入力端子と上記第2出力端子との間に挿入した第2スイッチＳＷ2と、
上記負入力端子と上記第1出力端子との間に挿入した第3スイッチＳＷ3と
上記負入力端子と上記第２出力端子との間に挿入した第4スイッチＳＷ4とを備える。The present invention has been made in view of the above problems, and the object of the present invention is to add a DC power supply to the power supply system with the correct polarity without checking the polarity of the power supply system to which the load is connected. It is to provide a polarity switching circuit that can do this.

The polarity switching circuit according to the present invention is interposed between the DC power supply and the load, and connects the DC power supply to the two power supply conductors connected to the load.
A positive input terminal IN + connected to the positive electrode of the DC power source;
A negative input terminal IN− connected to the negative electrode of the DC power supply;
A first output terminal OUT1 connected to one of the two feeding conductors;
A second output terminal OUT2 connected to the other of the two feeding conductors;
A first switch SW1 inserted between the positive input terminal and the first output terminal;
A second switch SW2 inserted between the positive input terminal and the second output terminal;
A third switch SW3 inserted between the negative input terminal and the first output terminal; and a fourth switch SW4 inserted between the negative input terminal and the second output terminal.

上記第１スイッチＳＷ１と第4スイッチＳＷ４は、上記第1出力端子ＯＵＴ１に印加される電圧が上記第2出力端子に印加される電圧よりも高い場合に導通して、上記正入力端子IN＋（直流電源の正極）を上記第1出力端子ＯＵＴ１に接続すると共に、上記負入力端子IN-（直流電源の負極）を上記第2出力端子ＯＵＴ２に接続するように構成される。   The first switch SW1 and the fourth switch SW4 are turned on when the voltage applied to the first output terminal OUT1 is higher than the voltage applied to the second output terminal, and the positive input terminal IN + (DC The positive input of the power source is connected to the first output terminal OUT1, and the negative input terminal IN− (the negative electrode of the DC power supply) is connected to the second output terminal OUT2.

上記第2スイッチＳＷ２と上記第3スイッチＳＷ３は、上記第1出力端子ＯＵＴ１に印加される電圧が上記第2出力端子ＯＵＴ２に印加される電圧よりも小さい場合に導通して、上記正入力端子IN＋（直流電源の正極）を上記第2出力端子に接続すると共に、上記負入力端子IN-（直流電源の負極）を上記第1出力端子に接続するように構成される。 The second switch SW2 and the third switch SW3 are turned on when the voltage applied to the first output terminal OUT1 is smaller than the voltage applied to the second output terminal OUT2, and the positive input terminal IN + (Positive electrode of DC power supply) is connected to the second output terminal, and the negative input terminal IN− (negative electrode of DC power supply) is connected to the first output terminal.

従って、2本の給電導体へ負荷と直流電源が既に接続されている給電システムに、新たな直流電源を追加する場合、このシステムにおける一方の給電導体が正極とされている場合は、この給電導体に接続される1出力端子へ、追加の直流電源の正極の出力が与えられ、この第1出力端子が負極とされておれば、ここへ追加の直流電源の負極が与えられる。即ち、本発明の極性切換回路では、第1出力端子と第2出力端子が接続されている極性を認識し、この極性に直流電源の出力の極性を合致させることができる。このため、給電システムに直流電源を追加する際に、極性切換回路の出力端子の極性を予め確認することなく、極性切換回路を既存の給電システムに接続することができて、接続工事を容易に行うことができる。   Therefore, when a new DC power supply is added to a power supply system in which a load and a DC power supply are already connected to two power supply conductors, if one power supply conductor in this system is positive, this power supply conductor The output of the positive electrode of the additional DC power supply is given to the one output terminal connected to, and if the first output terminal is set as the negative electrode, the negative electrode of the additional DC power supply is given here. That is, the polarity switching circuit of the present invention can recognize the polarity at which the first output terminal and the second output terminal are connected, and can match the polarity of the output of the DC power supply with this polarity. For this reason, when adding a DC power supply to the power feeding system, the polarity switching circuit can be connected to the existing power feeding system without checking the polarity of the output terminal of the polarity switching circuit in advance. It can be carried out.

この極性切換回路は直流電源と組み合わせて給電ユニットとして用意しておけば、接続工事に際して、極性を全く気にすることなく、直流電源と共に既存の給電システムに組み込むことができる。   If this polarity switching circuit is prepared as a power supply unit in combination with a DC power supply, it can be incorporated into an existing power supply system together with the DC power supply without worrying about the polarity at the time of connection work.

好ましい実施形態においては、上記第１スイッチは、制御端Ｇを有する第1スイッチング素子を備え、この第1スイッチング素子はこの制御端と上記正入力端子との間に所定値未満の電圧が印加された時に導通するように構成される。同様に、上記第2スイッチは、制御端Ｇを有する第２スイッチング素子を備え、この第２スイッチング素子はこの制御端と上記正入力端子との間に所定値未満の電圧が印加された時に導通するように構成され、上記第３スイッチは、制御端Ｇを有する第３スイッチング素子を備え、この第３スイッチング素子はこの制御端と上記正入力端子との間に所定値を超える電圧が印加された時に導通するように構成され、上記第４スイッチは、制御端Ｇを有する第４スイッチング素子を備え、この第４スイッチング素子はこの制御端と上記正入力端子との間に所定値を超える電圧が印加された時に導通するように構成される。   In a preferred embodiment, the first switch includes a first switching element having a control terminal G, and a voltage less than a predetermined value is applied between the control terminal and the positive input terminal. It is configured to conduct when Similarly, the second switch includes a second switching element having a control terminal G, and the second switching element is turned on when a voltage less than a predetermined value is applied between the control terminal and the positive input terminal. The third switch includes a third switching element having a control terminal G, and a voltage exceeding a predetermined value is applied between the control terminal and the positive input terminal. The fourth switch includes a fourth switching element having a control terminal G, and the fourth switching element has a voltage exceeding a predetermined value between the control terminal and the positive input terminal. Configured to conduct when is applied.

上記第1スイッチング素子の制御端と上記第3スイッチング素子の制御端が共に上記第2出力端子ＯＵＴ２に接続され、上記第２スイッチング素子の制御端と上記第４スイッチング素子の制御端が共に上記第１出力端子ＯＵＴ１に接続される。上記第1スイッチは、上記の第1スイッチング素子の制御端に上記正極からの上記所定値以上の制御電圧を与えた後に所定時間遅延させて、この制御端に上記所定値未満の電圧を与える第1遅延回路（Ｒ１、Ｃ１）を備える。上記第2スイッチは、上記の第２スイッチング素子の制御端に上記正極からの上記所定値以上の制御電圧を与えた後に所定時間遅延させて、この制御端に上記所定値未満の電圧を与える第2遅延回路（Ｒ２、Ｃ２）を備える。   The control terminal of the first switching element and the control terminal of the third switching element are both connected to the second output terminal OUT2, and the control terminal of the second switching element and the control terminal of the fourth switching element are both connected to the second output terminal OUT2. 1 is connected to the output terminal OUT1. The first switch delays a predetermined time after applying a control voltage higher than the predetermined value from the positive electrode to the control terminal of the first switching element, and applies a voltage less than the predetermined value to the control terminal. 1 delay circuit (R1, C1) is provided. The second switch delays a predetermined time after applying a control voltage higher than the predetermined value from the positive electrode to the control terminal of the second switching element, and applies a voltage less than the predetermined value to the control terminal. Two delay circuits (R2, C2) are provided.

従って、上記第1出力端子に印加される電圧が上記第2出力端子に印加される電圧よりも大きい時は、第１スイッチング素子の制御端には低い電圧が印加され、第２スイッチング素子の制御端には高い電圧が印加される。これにより、第1スイッチング素子が導通して、第2スイッチング素子を遮断させることで、第1出力端子に直流電源の正極が接続される。同様に、上記第1出力端子に印加される電圧が上記第2出力端子に印加される電圧よりも小さい時には、第1スイッチング素子が遮断し、第2スイッチ素子が導通して、第2出力端子に直流電源の正極が接続される。
一方、上記第1出力端子と上記第2出力端子にそれぞれ印加される電圧が等しい時、上記第1遅延回路と上記第2遅延回路が共に動作するが、上記第1遅延回路による遅延よりも上記第2遅延回路による遅延時間が長くなるように構成される。即ち、給電システムに最初に直流電源を接続する場合で、未だ給電導体の極性が決定されていない場合は、第１遅延回路での遅延が第2遅延回路よりも短いため、第1スイッチング素子の制御端に印加される電圧が所定値未満に降下するのが早められ、第1スイッチング素子が第2スイッチング素子よりも早く導通して、第1出力端子に直流電源正極を与えることが優先的に行われる。一度、第1出力端子に正極が印加されると、第2スイッチング素子の制御端には所定値以上の制御電圧が加えられて第2スイッチング素子が遮断され、第1出力端子を正極とし、第2出力端子を負極に決定する。
このように、給電システムに始めて直流電源を接続する場合は、第1出力端子に接続される給電導体を優先的に正極とすることができ、給電システムの標準化が達成でき、標準化された極性に基づいて、負荷を給電システムに接続することができる。
好ましくは、上記第1スイッチング素子及び第2スイッチング素子がゲート・ソース間に寄生容量を有するＦＥＴで構成される。第1スイッチング素子のソースが上記正入力端子に結合されると共にドレインが第1出力端子に接続され、ソース電圧がゲート電圧よりも所定値以上の時に導通して、上記の正入力端子を上記第1出力端子に接続される。この場合、上記第1遅延回路は、上記寄生容量Ｃ１と、この寄生容量と直列に上記正入力端子と上記第2出力端子との間に挿入された第1抵抗Ｒ１とで構成されて、第1抵抗Ｒ１と寄生容量Ｃ１との間の接続点がゲートＧに接続される。上記第２スイッチング素子のソースが上記正入力端に結合されると共にドレインが第２出力端子に接続され、ソース電圧がゲート電圧よりも所定値以上の時に導通して、上記の正入力端子ＩＮ＋が上記第２出力端子ＯＵＴ２に接続される。上記第２遅延回路（Ｒ２、Ｃ２）は、上記寄生容量Ｃ２と、この寄生容量と直列に上記正入力端子ＩＮ＋と上記第１出力端子ＯＵＴ１との間に挿入された第２抵抗Ｒ２とで構成されて、第２抵抗と寄生容量との間の接続点がゲートＧに接続される。上記第1抵抗Ｒ１の抵抗値が第2抵抗Ｒ２の抵抗値よりも小さくて、第1遅延回路の時定数を第2遅延回路の時定数よりも小さくすることで、上記第1遅延回路による遅延よりも上記第2遅延回路による遅延時間が長くなるように構成される。このように、ＦＥＴが本来的に備える寄生容量を利用して各遅延回路が構成でき、最小の部品点数で上の機能を有する切換回路が構成できる。
また、ＦＥＴでの許容ゲート・ソース電圧を超える電圧が直流電源から供給される場合は、ＦＥＴを保護するための分圧抵抗が使用される。即ち、上記正入力端子IN+と上記第2出力端子との間で上記第1抵抗R1と直列に第1分圧抵抗が接続され、第1抵抗R1と上記第1分圧抵抗R１１との間の接続点に上記第1スイッチング素子のゲートが接続される。同様に、上記正入力端子IN+と上記第１出力端子との間で上記第２抵抗R２と直列に第２分圧抵抗が接続され、第２抵抗R２と上記第２分圧抵抗R21との間の接続点に上記第２スイッチング素子のゲートが接続される。この構成により、ＦＥＴである第1スイッチング素子及び第2スイッチング素子のゲート・ソース電圧を所定値以下に分圧することができ、ＦＥＴを保護することができる。
更に、本発明の極性切換回路の出力が誤って短絡した場合にＦＥＴの温度上昇を押さえてＦＥＴを保護するために、上記第1分圧抵抗R11と上記正入力端子IN+との間に第1ツェナーダイオードが挿入され、上記第２分圧抵抗R２１と上記正入力端子IN+との間に第2ツェナーダイオードが挿入することが好ましい。 Therefore, when the voltage applied to the first output terminal is larger than the voltage applied to the second output terminal, a low voltage is applied to the control terminal of the first switching element, and the control of the second switching element is performed. A high voltage is applied to the ends. As a result, the first switching element is turned on and the second switching element is cut off, so that the positive electrode of the DC power supply is connected to the first output terminal. Similarly, when the voltage applied to the first output terminal is smaller than the voltage applied to the second output terminal, the first switching element is cut off, the second switch element is turned on, and the second output terminal Is connected to the positive electrode of the DC power source.
On the other hand, when the voltages applied to the first output terminal and the second output terminal are equal, the first delay circuit and the second delay circuit operate together, but the delay is more than the delay by the first delay circuit. The delay time by the second delay circuit is configured to be long. That is, when the DC power supply is first connected to the power supply system and the polarity of the power supply conductor has not yet been determined, the delay in the first delay circuit is shorter than that in the second delay circuit. It is preferential that the voltage applied to the control terminal falls earlier than the predetermined value, the first switching element conducts earlier than the second switching element, and the DC power supply positive electrode is applied to the first output terminal. Done. Once a positive electrode is applied to the first output terminal, a control voltage of a predetermined value or more is applied to the control terminal of the second switching element to cut off the second switching element, and the first output terminal is used as the positive electrode. 2 Determine the output terminal to be negative.
In this way, when connecting a DC power supply for the first time to the power supply system, the power supply conductor connected to the first output terminal can be preferentially used as the positive electrode, standardization of the power supply system can be achieved, and the standardized polarity can be achieved. Based on this, the load can be connected to the power supply system.
Preferably, the first switching element and the second switching element are composed of FETs having a parasitic capacitance between the gate and the source. Drain with the source of the first switching element is coupled to the positive input pin is connected to the first output terminal, and conducts when the predetermined value or more than the source voltage is a gate voltage, the positive input terminal of the Connected to the first output terminal. In this case, the first delay circuit includes the parasitic capacitor C1 and a first resistor R1 inserted between the positive input terminal and the second output terminal in series with the parasitic capacitor. 1 A connection point between the resistor R1 and the parasitic capacitance C1 is connected to the gate G. The source of the second switching element is coupled to the positive input terminal and the drain is connected to the second output terminal. The source is turned on when the source voltage is a predetermined value or higher than the gate voltage, and the positive input terminal IN + is Connected to the second output terminal OUT2. The second delay circuit (R2, C2) includes the parasitic capacitor C2 and a second resistor R2 inserted between the positive input terminal IN + and the first output terminal OUT1 in series with the parasitic capacitor. Thus, the connection point between the second resistor and the parasitic capacitance is connected to the gate G. The resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2, and the time constant of the first delay circuit is made smaller than the time constant of the second delay circuit. The delay time by the second delay circuit is longer than that. In this way, each delay circuit can be configured using the parasitic capacitance inherent in the FET, and a switching circuit having the above functions can be configured with a minimum number of components.
Further, when a voltage exceeding the allowable gate-source voltage in the FET is supplied from the DC power supply, a voltage dividing resistor for protecting the FET is used. That is, a first voltage dividing resistor is connected in series with the first resistor R1 between the positive input terminal IN + and the second output terminal, and between the first resistor R1 and the first voltage dividing resistor R11. The gate of the first switching element is connected to the connection point. Similarly, a second voltage dividing resistor is connected in series with the second resistor R2 between the positive input terminal IN + and the first output terminal, and between the second resistor R2 and the second voltage dividing resistor R21. Is connected to the gate of the second switching element. With this configuration, the gate-source voltages of the first switching element and the second switching element, which are FETs, can be divided to a predetermined value or less, and the FETs can be protected.
Further, in order to protect the FET by suppressing the temperature rise of the FET when the output of the polarity switching circuit of the present invention is accidentally shorted, the first voltage dividing resistor R11 and the positive input terminal IN + Preferably, a Zener diode is inserted, and a second Zener diode is inserted between the second voltage dividing resistor R21 and the positive input terminal IN +.

本発明の第１の実施形態に係る極性切換回路の回路図。1 is a circuit diagram of a polarity switching circuit according to a first embodiment of the present invention. 同上の極性切換回路を内蔵した給電ユニットを示すブロック図。The block diagram which shows the electric power feeding unit which incorporated the polarity switching circuit same as the above. 同上の給電ユニットの一使用形態を示す概略図。Schematic which shows one usage pattern of an electric power feeding unit same as the above. 同上の極性回路の変更態様を示す回路図。The circuit diagram which shows the change aspect of a polarity circuit same as the above. 同上の極性回路の変更態様を示す回路図。The circuit diagram which shows the change aspect of a polarity circuit same as the above. 同上の極性回路の変更態様を示す回路図。The circuit diagram which shows the change aspect of a polarity circuit same as the above. 同上の極性回路の変更態様を示す回路図。The circuit diagram which shows the change aspect of a polarity circuit same as the above. 本発明の第２の実施形態に係る極性切換回路の回路図。The circuit diagram of the polarity switching circuit which concerns on the 2nd Embodiment of this invention. 本発明の第３の実施形態に係る極性切換回路の回路図。The circuit diagram of the polarity switching circuit which concerns on the 3rd Embodiment of this invention.

本発明に係る極性切換回路は、直流電圧で駆動される負荷に直流電圧を供給する直流電圧給電システムに使用され、直流電源をこの給電システムに追加する場合に、負荷が接続されている２本の給電導体の極性を検出して、直流電源の極性を給電導体の極性に合致させるものである。この極性切換回路２０は、通常、図２に示すように、直流電源１０を含む給電ユニット４０に組み込まれる。この給電ユニット４０は、図３に示すような給電システムにおいて、複数が互いに並列に接続されて、給電導体１Ａ、１Ｂに接続された複数の負荷２に直流電圧、例えば、１２Vの電圧を供給する。   The polarity switching circuit according to the present invention is used in a DC voltage power supply system that supplies a DC voltage to a load driven by a DC voltage. When a DC power supply is added to the power supply system, the two connected to the load are connected. The polarity of the power supply conductor is detected, and the polarity of the DC power supply is matched with the polarity of the power supply conductor. The polarity switching circuit 20 is usually incorporated in a power supply unit 40 including a DC power supply 10 as shown in FIG. In the power supply system as shown in FIG. 3, the power supply unit 40 is connected in parallel to each other, and supplies a DC voltage, for example, a voltage of 12 V, to the plurality of loads 2 connected to the power supply conductors 1A and 1B. .

給電ユニット４０中の直流電源１０は、商用ＡＣ電源へスイッチ１２を介して接続され、ＡＣ電圧をＤＣ電圧に変換し、変換されたＤＣ電圧が極性切換回路２０を介して給電導体１Ａ、１Ｂへ供給される。負荷２としては、この給電導体を利用して情報通信を行うことができるものが使用でき、この場合は、図３に示すように、給電システムには終端装置３が接続され、給電ユニット４０には、図２に示すように、給電導体１Ａ、１Ｂに流れる高周波の通信信号と極性切換回路２０とを分離するインピーダンス調整部３０が設けられる。

＜第１の実施形態＞
図１は、本発明の第１の実施形態に係る極性切換回路を示し、４つのＭＯＳＦＥＴで構成されるスイッチＳＷ１〜ＳＷ４が、正負入力端子ＩＮ＋、ＩＮ−と、第１及び第２出力端子ＯＵＴ１、ＯＵＴ２との間で、ブリッジ接続される。正入力端子ＩＮ＋は、直流電源１０の正極に接続され、負入力端子ＩＮ−は直流電源の負極に接続される。第１スイッチＳＷ１は、正入力端子ＩＮ＋と第１出力端子ＯＵＴ１との間に挿入されて、ソースＳを正入力端子ＩＮ＋に接続して、ドレインＤを第１出力端子ＯＵＴ１に接続する。第２スイッチＳＷ２は、正入力端子ＩＮ＋と第２出力端子ＯＵＴ２との間に挿入されて、ソースＳを正入力端子ＩＮ＋に接続して、ドレインＤを第２出力端子ＯＵＴ２に接続する。第３スイッチSW3は、負入力端子ＩＮ―と第１出力端子ＯＵＴ１との間に挿入されて、ソースＳを負入力端子ＩＮ−に接続して、ドレインＤを第１出力端子ＯＵＴ１に接続する。第４スイッチSW4は、負入力端子ＩＮ―と第２出力端子ＯＵＴ２との間に挿入されて、ソースＳを負入力端子ＩＮ−に接続して、ドレインＤを第２出力端子ＯＵＴ２に接続する。

第１スイッチSW1及び第２スイッチを構成するMOSFETであるスイッチング素子は、ゲート電圧よりソース電圧が高い場合に、導通するP型トランジスタであり、第３スイッチSW3及び第４スイッチSW4を構成するMOSFETであるスイッチング素子は、ゲート電圧がソース電圧より高い場合に、導通するＮ型トランジスタである。The DC power supply 10 in the power supply unit 40 is connected to a commercial AC power supply via the switch 12 to convert the AC voltage into a DC voltage, and the converted DC voltage is supplied to the power supply conductors 1A and 1B via the polarity switching circuit 20. Supplied. As the load 2, a load capable of performing information communication using this power supply conductor can be used. In this case, as shown in FIG. 3, a termination device 3 is connected to the power supply system, and the power supply unit 40 is connected to the power supply unit 40. As shown in FIG. 2, an impedance adjusting unit 30 that separates the high-frequency communication signal flowing through the power supply conductors 1 </ b> A and 1 </ b> B from the polarity switching circuit 20 is provided.

<First Embodiment>
FIG. 1 shows a polarity switching circuit according to a first embodiment of the present invention, in which switches SW1 to SW4 composed of four MOSFETs are connected to positive and negative input terminals IN + and IN− and first and second output terminals OUT1. , OUT2 is bridge-connected. The positive input terminal IN + is connected to the positive electrode of the DC power supply 10, and the negative input terminal IN− is connected to the negative electrode of the DC power supply. The first switch SW1 is inserted between the positive input terminal IN + and the first output terminal OUT1, and connects the source S to the positive input terminal IN + and connects the drain D to the first output terminal OUT1. The second switch SW2 is inserted between the positive input terminal IN + and the second output terminal OUT2, and connects the source S to the positive input terminal IN + and connects the drain D to the second output terminal OUT2. The third switch SW3 is inserted between the negative input terminal IN− and the first output terminal OUT1, and connects the source S to the negative input terminal IN− and connects the drain D to the first output terminal OUT1. The fourth switch SW4 is inserted between the negative input terminal IN− and the second output terminal OUT2, and connects the source S to the negative input terminal IN− and connects the drain D to the second output terminal OUT2.

The switching elements that are the MOSFETs constituting the first switch SW1 and the second switch are P-type transistors that conduct when the source voltage is higher than the gate voltage, and the MOSFETs that constitute the third switch SW3 and the fourth switch SW4. Some switching elements are N-type transistors that conduct when the gate voltage is higher than the source voltage.

第１スイッチＳＷ１を構成するＭＯＳＦＥＴであるスイッチング素子のゲートＧは、第３スイッチＳＷ３のスイッチング素子のゲートＧと共に、第２出力端子ＯＵＴ２に接続され、第２スイッチＳＷ２を構成するスイッチング素子のゲートＧは、第４スイッチＳＷ４のスイッチング素子のゲートＧと共に、第１出力端子ＯＵＴ１に接続される。各スイッチング素子のゲートは、各スイッチのオン・オフを決定するための電圧が印加される制御端であり、ソース電圧とゲート電圧との大小関係に基づいて、各スイッチのオン・オフ制御がなされる。
各スイッチを構成するスイッチング素子は、それぞれ、ゲート・ソース間に寄生容量C１〜C4を本来的に有するもので、第１スイッチSW1及び第２スイッチSW2での寄生容量C1、C2はそれぞれ１０００ｐF、第３スイッチ素子SW3及び第４スイッチSW4での寄生容量C３、C4はそれぞれ３００ｐFである。この値は、単なる例示に過ぎず、必要に応じて変更することが可能であり、C1、C２とC３、C4の間の大小関係もP型とN型のスイッチの間で逆転する場合もある。
各スイッチング素子には、それぞれ抵抗Ｒ１〜Ｒ４が寄生容量Ｃ１〜Ｃ４と直列に接続されて、遅延回路を形成し、抵抗と寄生容量との接続点が各スイッチング素子のゲートに接続される。各遅延回路は、寄生容量への充電速度を調整することで、各スイッチング素子が導通するタイミングを変化させるものであり、後述するように、給電システムへ最初に給電ユニットを接続する際に、給電導体１Ａ、１Ｂの極性を決定するために、第１スイッチＳＷ１と第２スイッチの一方を優先的に動作させるように設定されている。
本発明の極性切換回路２０は、既に稼働している給電システムに、給電ユニットを追加する場合に、第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２に出力する電圧を、給電導体１Ａ、１Ｂの極性に応じた電圧に合致させるものであり、作業者が給電導体の極性を予め調べる必要を無くして、給電ユニット４０の追加接続作業を容易にするものである。
以下に、既に稼働している給電システムに給電ユニットを追加した場合の極性切換回路の動作について説明する。この説明では、給電導体１Ａが＋１２Vの電圧が印加されている正極であり、給電導体１Ｂが０Ｖの電圧が印加されている負極であり、直流電源が１２Vの直流電圧を供給するものとする。
１）第１出力端子ＯＵＴ１が、正極の給電導体１Ａに接続され、第２出力端子ＯＵＴ２が負極の給電導体１Ｂに接続された場合
この場合、第１スイッチＳＷ１と第２スイッチＳＷ２のソースＳには、共に、直流電源からの正極電圧１２Vが印加され、第３スイッチＳＷ３と第４スイッチのソースＳには、共に直流電源からの０Ｖが印加される。一方、給電システムからは、第１出力端子ＯＵＴ１に１２Vが印加され、第２出力端子ＯＵＴ２に０Ｖが印加される。
このため、第１スイッチＳＷ１では、第２出力端子ＯＵＴ２からの０Ｖがゲート電圧となって、ゲート電圧（０Ｖ）＜ソース電圧（１２V）の関係が満たされ、第１スイッチＳＷ１がオンし、第２スイッチＳＷ２では、ゲート電圧とソース電圧が共に１２Vとなり、オン条件（ゲート電圧＜ソース電圧）が満たされずにオフとなり、第２スイッチＳＷ２がオフとなる。また、第３スイッチＳＷ３では、ソース電圧とゲート電圧が共に０Ｖとなり、オン条件である（ゲート電圧＞ソース電圧）が満たされずに、オフとなり、第４スイッチＳＷ４では、ゲート電圧（１２V）＞ソース電圧（０Ｖ）となって、第４スイッチＳＷ４がオンする。従って、第１スイッチＳＷ１と第４スイッチＳＷ４だけがオンされて、直流電源の正極電圧１２Vが第１出力端子ＯＵＴ１に印加され、直流電源の負極電圧０Ｖが第２出力端子ＯＵＴ２に印加されることになり、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。
２）第１出力端子ＯＵＴ１が、負極の給電導体１Ｂに接続され、第２出力端子ＯＵＴ２が正極の給電導体１Ｂに接続された場合
この場合、第１スイッチＳＷ１と第２スイッチＳＷ２のソースＳには、共に、直流電源からの正極電圧１２Vが印加され、第３スイッチＳＷ３と第４スイッチのソースＳには、共に直流電源からの０Ｖが印加される。一方、給電システムからは第１出力端子ＯＵＴ１には０Ｖが印加され、第２出力端子ＯＵＴ２には１２Vが印加される。
このため、第１スイッチＳＷ１では、第２出力端子ＯＵＴ２からの１２Vがゲート電圧となり、オン条件（ゲート電圧＜ソース電圧）が満たされずに、オフする。第２スイッチＳＷ２では、ゲート電圧（０Ｖ）＜ソース電圧（１２V）となって、オンする。また、第３スイッチＳＷ３では、ゲート電圧（１２V）＞ソース電圧（０Ｖ）となってオンする。第４スイッチＳＷ４では、ゲート電圧とソース電圧が共に０Ｖとなって、オン条件（ゲート電圧＞ソース電圧）が満たされずに、オフする。従って、第２スイッチＳＷ２と第３スイッチＳＷ３だけがオンされて、直流電源の正極電圧１２Vが第２出力端子ＯＵＴ２に印加され、直流電源の負極電圧０Ｖが第１出力端子ＯＵＴ２に印加されることになり、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。
３）最初に給電ユニットを給電システムに接続する場合
この場合、給電導体１Ａ、１Ｂは共に０Ｖであり、この状態で給電ユニット４０の第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２を給電導体に接続すると、第１出力端子ＯＵＴ１及び第２出力端子ＯＵＴ２には、実質的な電圧が印加されない。接続直後は、第１スイッチＳＷ１、第２スイッチＳＷ２の各ゲートＧへ、正極入力端子ＩＮ＋から寄生容量Ｃ１、Ｃ２を介して１２Vが印加され、各寄生容量Ｃ１、Ｃ２の充電が開始される。接続直後においては、第１スイッチＳＷ１及び第２スイッチＳＷ２は共にゲート電圧が１２V及びソース電圧が１２Vとなるため、共にオフされているが、寄生容量Ｃ１、Ｃ２への充電に伴って、ゲート電圧が１２Vよりも低くなると、オンされる。ここで、各スイッチにおける各充電回路は、寄生容量Ｃ１、Ｃ２とこれに接続される抵抗Ｒ１、Ｒ２とで構成されており、Ｒ１＝１ｋΩ、Ｒ２を２ｋΩとして第１スイッチの充電回路の時定数を第２スイッチよりも早くしている。このため、第１スイッチＳＷのゲート電圧の低下が第２スイッチよりも早くなることで、第１スイッチが早くオンする。この結果、第１出力端子ＯＵＴ１には直流電源からの１２Vが印加されることになり、これに伴って、第２スイッチＳＷ２のゲートが１２Vに固定され、第２スイッチＳＷのオフが確定される。第３スイッチＳＷ３は接続直後からゲート電圧及びソース電圧が共に０Ｖに固定されるため、オフが維持される。一方、第４スイッチＳＷ４は、接続直後ではゲート電圧及びソース電圧が共に０Ｖであるため、オフしているが、第１スイッチＳＷ１がオンして第１出力端子ＯＵＴ１の電圧が１２Vとなることに伴って、ゲート電圧が１２Vとなることで、オン条件（ゲート電圧＜ソース電圧）が満たされて、オンされる。従って、始めて給電ユニットを給電システムに接続する場合は、第１出力端子ＯＵＴ１が優先的に直流電源の正極１２Vが印加されることになる。
尚、抵抗Ｒ１、Ｒ２の関係をＲ１＜Ｒ２であれば、接続直後で第２スイッチＳＷ２が先にオンし、第２スイッチＳＷ２と第３スイッチＳＷ３がオンし、第１スイッチＳＷ１と第４スイッチＳＷ４がオフして、第２出力端子ＯＵＴ２に１２Vの正極を与え、第１出力端子ＯＵＴ１に０Ｖの負極が与えられることになる。
この実施形態では、抵抗Ｒ１とＲ２との抵抗値に明白な差を付けて、第１スイッチＳＷ１を第２スイッチＳＷ２よりも早くオンさせるように設定しているが、各スイッチの充電回路の間には、抵抗や寄生容量のばらつきにより、時定数の差があることが予想されるため、このようなばらつきを利用して、第１スイッチＳＷ１と第４スイッチＳＷ４の組と、第２スイッチＳＷ２と第３スイッチＳＷ３との組との何れか一方が優先的にオンされて、給電導体１Ａ、１Ｂのどちらか一方を正極とすることが決定される。その後に、給電ユニット４０を追加する場合は、上述したように、給電導体１Ａ、１Ｂの極性が判断されて、追加する給電ユニットの出力極性が既存の給電システムの極性に合致される。
ところで、第１スイッチＳＷ１と第２スイッチＳＷ２の充電回路の時定数は、抵抗Ｒ１、Ｒ２、寄生容量Ｃ１、Ｃ２のばらつきによって、異なることが予想されるが、万一、両方の時定数が一致する場合は、第３スイッチＳＷ３と第４スイッチＳＷ４での充電回路の時定数が同様に、抵抗と寄生容量のばらつきによって、異なることで、第１スイッチＳＷ１と第４スイッチＳＷ４の組と、第２スイッチＳＷ２と第３スイッチＳＷ３との組との何れか一方が優先的にオンされて、給電導体１Ａ、１Ｂのどちらか一方を正極とすることが決定される。
即ち、給電ユニットの接続後に、第１スイッチＳＷ１と第２スイッチＳＷ２が一時的に何れもオン状態となって、第１出力端子ＯＵＴ１及び第２出力端子ＯＵＴ２とに１２Vの電圧が印加されるような場合は、この電圧がそれぞれ、抵抗Ｒ３、Ｒ４と寄生容量Ｃ３、Ｃ４とへ負入力端子ＩＮ―（０Ｖ）との間で印加されて、各充電回路の寄生容量Ｃ３、Ｃ４を充電することになる。この場合、第３スイッチＳＷ３及び第４スイッチＳＷ４のソース電圧は負入力端子と同電位の０Ｖであることから、第４スイッチＳＷ４の充電回路の時定数が第３スイッチＳＷ３の充電回路の時定数よりも小さければければ、寄生容量Ｃ３、Ｃ４への充電速度が異なり、第４スイッチＳＷ４のゲート電圧が０Ｖからの上昇速度が第３スイッチＳＷ３よりも早くなることで、第４スイッチＳＷ４が先にオンとなり、第２出力端子ＯＵＴ２を負極に決定する。この結果、第３スイッチＳＷ３のゲート電圧が０Ｖに固定され、ソース電圧（０Ｖ）と等しくなることで、第３スイッチＳＷ３がオフされる。同時に第１スイッチＳＷ１のゲート電圧が０Ｖに固定されることで、第１スイッチＳＷ１のオンが確定され、これに伴って第１出力端子ＯＵＴ１が１２Vに固定されることで、第２スイッチＳＷ２のゲート電圧が１２Vに固定されて、第２スイッチＳＷ２のオフが確定する。これにより、第１出力端子ＯＵＴ１へは直流電源からの正極が与えられる。同様に、第３スイッチＳＷ３の充電回路の時定数が第４スイッチＳＷ４の充電回路の時定数よりも小さければければ、寄生容量Ｃ３、Ｃ４への充電速度が異なることで、第３スイッチＳＷ３がオンとなり、これに伴って、第４スイッチＳＷ４と第１スイッチＳＷ１がオフされ、第２スイッチＳＷ２がオンとなって、第２出力端子ＯＵＴ２に直流電源からの正極が与えられる。
このように、第１スイッチと第２スイッチとの充電回路の時定数や、第３スイッチと第４スイッチの充電回路の時定数には、抵抗Ｒ１〜Ｒ４、寄生容量Ｃ１〜Ｃ４のばらつきにより、差が生じることが予想されるため、その差異によって、直流電源の正極を第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２との何れか一方へ優先的に割り当てることが可能である。しかしながら、本実施形態においては、一貫した安定動作を与える意味で、Ｒ１＜Ｒ２とするか、或いは、Ｒ１＝Ｒ２でＲ３＞Ｒ４（Ｒ３＝２ＫΩ、Ｒ４＝１ｋΩ）として、第１出力端子ＯＵＴ１に直流電源の正極を出力するようにしている。勿論、Ｒ１＞Ｒ２或いは、Ｒ１＝Ｒ２でＲ３＜Ｒ４として、第２出力端子ＯＵＴ２に直流電源の正極を出力するようにしてもよい。
図４〜図６は、上述の極性切換回路の変更態様を示すもので、図４の変更態様では、第１スイッチＳＷ１及び第２スイッチＳＷ２のみに、抵抗Ｒ１、Ｒ２を接続して充電回路を形成して、Ｒ１とＲ２の値を異なえた例を示し、図５及び図６の変更態様では、第３スイッチＳＷ３と第４スイッチＳＷ４のみに、抵抗Ｒ３、Ｒ４を接続して充電回路を形成して、Ｒ３とＲ４の値を異なえた例を示す。
尚、上記の実施形態及び変更態様では、スイッチング素子の寄生容量を利用して対応するスイッチへ充電回路を付加した例を示したが、本発明は必ずしもこれのみに限定されるものではなく、例えば、インダクタと抵抗との組み合わせで充電回路を形成するようにしてもよい。
図７は、上述の実施形態の極性切換回路の更に他の変更態様を示す。この変更態様では、各充電回路を構成する抵抗R1〜R4に対してそれぞれ、分圧抵抗をR11、R21、R３１、R４１を接続して、各スイッチング素子のゲートに印加される電圧を低く抑えている。この構成は、直流電源１０の出力電圧が、例えば、２４Vであり、スイッチング素子として使用するMOSFETでの許容ゲート・ソース電圧を超える場合に、スイッチング素子を保護するために有用である。
以下、各分圧抵抗の具体的な接続関係を説明する。第１スイッチSW1では、第１分圧抵抗R11が、正入力端子ＩＮ＋と第２出力端子OUT2との間で、第１抵抗R1と直列に接続され、第１分圧抵抗R１１と第１抵抗R1の間の接続点にスイッチング素子のゲートGが接続される。第２スイッチSW２では、第２分圧抵抗R２１が、正入力端子ＩＮ＋と第１出力端子OUT１との間で、第２抵抗R２と直列に接続され、第２分圧抵抗R２１と第２抵抗R２の間の接続点にスイッチング素子のゲートGが接続される。第３スイッチSW３では、第３分圧抵抗R３1が、負入力端子ＩＮ−と第２出力端子OUT2との間で、第３抵抗R３と直列に接続され、第３分圧抵抗R３１と第３抵抗R３の間の接続点にスイッチング素子のゲートGが接続される。第４スイッチSW４では、第４分圧抵抗R４1が、負入力端子ＩＮ−と第１出力端子OUT１との間で、第４抵抗R４と直列に接続され、第４分圧抵抗R４１と第４抵抗R４の間の接続点にスイッチング素子のゲートGが接続される。
更に、この変更態様では、各分圧抵抗R11、R21、R31、R41にそれぞれ、ツェナーダイオードZD１、ZD2、ZD3、ZD4を直列に接続している。即ち、第１ツェナーダイオードZD1が、第１分圧抵抗R11と正入力端子IN+との間に挿入され、第２ツェナーダイオードZD２が、第２分圧抵抗R２１と正入力端子IN+との間に挿入され、第３ツェナーダイオードZD３が、第３分圧抵抗R３１と負入力端子IN―との間に挿入され、第４ツェナーダイオードZD４が、第４分圧抵抗R４１と負入力端子IN−との間に挿入される。
＜第２の実施形態＞
図８は、本発明の第２の実施形態に係る極性切換回路を示す。この実施形態では各スイッチSW1〜SW4として、バイポーラトランジスタを使用し、第１出力端子OUT1及び第２出力端子OUT2の電位を検出して各スイッチを制御する制御回路１００を備える。
第１スイッチSW1はＮＰＮ型バイポーラトランジスタであり、コレクタが正入力端IN+に結合されると共にエミッタが第１出力端子OUT1に接続され、ベース電圧が閾値以上となった時に導通して、正入力端子IN＋を第１出力端子OUT1に接続する。第２スイッチSW２はＮＰＮ型バイポーラトランジスタであり、コレクタが正入力端IN+に結合されると共にエミッタが第２出力端子OUT2に接続され、ベース電圧が閾値以上となった時に導通して、正入力端子IN+を上記第２出力端子OUT2に接続する。第３スイッチSW３はＰＮＰ型バイポーラトランジスタであり、コレクタが負入力端IN-に結合されると共にエミッタが第１出力端子OUT１に接続され、ベース電圧が閾値未満となった時に導通して、負入力端子IN-を第１出力端子OUT1に接続する。第４スイッチSW4はＰＮＰ型バイポーラトランジスタであり、コレクタが負入力端に結合されると共にエミッタが第２出力端子OUT2に接続され、ベース電圧が閾値未満となった時に導通して、負入力端子IN-を第２出力端子に接続する。
制御回路１００は、第1出力端子ＯＵＴ１に印加される第１電位と、第2出力端子ＯＵＴ２に印加される第２電位とを検出して各スイッチSW1〜SW4を制御する様に構成され、以下の機能を達成する。
i)第１電位が第2電位よりも大きい場合に、第１スイッチSW1と第３スイッチSW３の各ベースに閾値以上の制御電圧を与えるとともに、第２スイッチSW２と第4スイッチSW4の各ベースに閾値未満の制御電圧を与える。
ii)第1電位が第2電位よりも小さい場合に、第１スイッチSW1と第３スイッチSW３の各ベースに閾値未満の制御電圧を与えると共に、第２スイッチSW2と第4スイッチSW4の各ベースに閾値以上の制御電圧を与える。
iii)第１電位と第2電位とが同電位の場合に、第１スイッチSW1と第３スイッチSW３の各ベースに閾値未満の制御電圧を与えるとともに、第２スイッチSW２と第4スイッチングSW4の各ベースに閾値未満の制御電圧を与える。
この機能を実現するため、制御回路１００は、第1出力端子ＯＵＴ１に印加される第１電位を検出して、第１電位が所定値以上の場合は、第１検知信号を出力する第１検知手段（コンパレータ）１０１と、第２出力端子ＯＵＴ２に印加される第２電位を検出して、第２電位が所定値以上の場合は、第２検知信号を出力する第２検知手段（コンパレータ）１０２と、第１検知信号と第2検知信号の両方が同時に存在しない時のみに、所定の制御電圧を判定手段（ORゲート）１３０に与える論理手段（NORゲート）１１０とを備える。第2検知電圧は、第２スイッチSW２と第4スイッチSW4の各ベースへ共通して与えられるもので、上記の閾値以上と設定される。
判定手段１３０は、上記の制御電圧と第１検知電圧との少なくも一方を受けた時に、ベース電圧の閾値を超える駆動電圧を上記第１スイッチSW1と第３スイッチSW３のベースに与えるように構成される。
この制御回路１００には、抵抗R5、コンデンサC5、コンパレータ１２１で構成され遅延手段１２０が設けられ、論理手段（NORゲート）１１０から出力される制御電圧を遅延させた後に、これを判定手段１３０へ出力する。
本実施形態に係る極性切換回路の動作を以下に説明する。この説明では、理解を容易とするために、便宜上、直流電源の出力電圧及び給電システムでの動作電圧を１２Vとし、第１検知手段１０１や第２検知手段１０２や論理手段１１０や判定手段１３０からの出力を、１２Vまたは０Vとするものであり、実際は回路設計の観点から異なる値とすることができる。
１）第１出力端子ＯＵＴ１が、正極の給電導体１Ａに接続され、第２出力端子ＯＵＴ２が負極の給電導体１Ｂに接続された場合
第１出力端子OUT1に印加される電圧が１２V、第２出力端子OUT2に印加される電圧が０Vであり、第１検知手段１０１、第２検知手段１０２での基準値が１２V未満とすると、第１検知手段１０１は、第１検知信号として１２Vの電圧信号を出力し、第２検知手段１０２の出力が０Vとなり第２検知信号を出力しない。この結果、論理手段１１０の出力が０Vとなり、制御電圧を出力しない。このため、遅延手段１２０は動作せず、０Vの出力が判定手段１３０に入力される。判定手段１３０は、第１検知手段１０１からの１２Vの第１検知信号を受けて、１２Vの駆動電圧を第１スイッチSW1と第３スイッチSW３のベースに与える。これによって、第１スイッチSW1がオンし、第３スイッチSW３がオフされる。一方、第２スイッチSW２と第４スイッチSW4のベースには、第２検知手段１０２からの出力が０Vであるため、第２検知信号が与えられず、第２スイッチSW２がオフし、第４スイッチSW4がオンとなる。この結果、第１スイッチSW１と第４スイッチSW4のみがオンとなり、正入力端子ＩＮ+が第１出力端子OUT1に接続され、負入力端子ＩＮ-が第2出力端子OUT2に接続され、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。
２）第１出力端子ＯＵＴ１が、負極の給電導体１Ｂに接続され、第２出力端子ＯＵＴ２が正極の給電導体１Ｂに接続された場合
第1検知手段１０１の出力が０Vで第1検知信号を出力せず、第2検知手段１０２は１２Vの第2検知信号を出力する。この場合、論理手段１１０の出力は０Vであり、制御電圧が出力されず、遅延回路１２０が動作せず、判定手段１３０の一方の入力は０Vである。判定手段１３０の他方の入力には、第1検知手段１０１から出力される０Vが入力されているため、判定手段１３０は０Ｖを出力して、駆動電圧を第1スイッチSW1と第３スイッチSW３のベースに与えない。この結果、第1スイッチSW1がオフし、第３スイッチSW３がオンされる。一方、第2検知手段１０２からの１２Vの第2検知信号が第２スイッチSW２と第4スイッチSW4のベースに与えられ、第２スイッチSW２がオンし、第4スイッチSW4がオフする。この結果、第２スイッチSW２と第３スイッチSW３のみがオンとなり、正入力端子ＩＮ+が第２出力端子OUT２に接続され、負入力端子ＩＮ-が第１出力端子OUT１に接続され、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。
３）最初に給電ユニットを給電システムに接続する場合
この場合、給電導体１Ａ、１Ｂは共に０Ｖであり、この状態で給電ユニット４０の第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２を給電導体に接続すると、第１出力端子ＯＵＴ１及び第２出力端子ＯＵＴ２は共に０Vの電圧となり、第１検知手段101と第2検知手段１０２は共に０Vを出力し、第1検知信号と第2検知信号を出力しない。その結果、論理手段１１０は１２Vの制御電圧を出力し、この出力が遅延回路１２０を介して、判定手段１３０に送られる。遅延手段１２０は１２Vの制御電圧を遅延させて判定手段１３０に出力する結果、判定手段１３０には、最初、遅延手段１２０から０Vの出力と、第1検知手段１０１から０Vが入力され、判定手段１３０は０Vを出力して駆動電圧を与えないが、その後に、遅延手段１２０から１２Vの制御電圧が判定手段１３０に入力されると、判定手段１３０は１２Vの駆動電圧を出力する。その結果、第1スイッチSW1がオンされ、第３スイッチSW３がオフされる。一方、第2検知手段１０２からの０V出力により、第３スイッチSW３がオフされ、第4スイッチSW4がオンとされる。従って、始めて給電ユニットを給電システムに接続する場合は、第1スイッチSW1と第4スイッチSW4のみがオンとされて、第１出力端子ＯＵＴ１へ優先的に直流電源の正極１２Vが印加されることになる。
＜第３の実施形態＞
図９は、本発明の第３の実施形態に係る極性切換回路を示す。この実施形態では各スイッチSW1〜SW4として、電磁リレーを使用し、第2の実施形態と同様の制御回路１００を備える。 The gate G of the switching element which is a MOSFET constituting the first switch SW1 is connected to the second output terminal OUT2 together with the gate G of the switching element of the third switch SW3, and the gate G of the switching element constituting the second switch SW2. Are connected to the first output terminal OUT1 together with the gate G of the switching element of the fourth switch SW4. The gate of each switching element is a control terminal to which a voltage for determining on / off of each switch is applied, and the on / off control of each switch is performed based on the magnitude relationship between the source voltage and the gate voltage. The
The switching elements constituting each switch inherently have parasitic capacitances C1 to C4 between the gate and the source. The parasitic capacitances C1 and C2 in the first switch SW1 and the second switch SW2 are 1000 pF, respectively. Parasitic capacitances C3 and C4 in the three switch element SW3 and the fourth switch SW4 are 300 pF, respectively. This value is only an example and can be changed as necessary, and the magnitude relationship between C1, C2 and C3, C4 may also be reversed between P-type and N-type switches. .
In each switching element, resistors R1 to R4 are connected in series with parasitic capacitances C1 to C4 to form a delay circuit, and a connection point between the resistance and the parasitic capacitance is connected to the gate of each switching element. Each delay circuit changes the timing at which each switching element becomes conductive by adjusting the charging speed to the parasitic capacitance. As will be described later, when the power supply unit is first connected to the power supply system, In order to determine the polarities of the conductors 1A and 1B, one of the first switch SW1 and the second switch is set to operate with priority.
The polarity switching circuit 20 according to the present invention, when adding a power supply unit to a power supply system that is already in operation, supplies the voltages output to the first output terminal OUT1 and the second output terminal OUT2 to the polarities of the power supply conductors 1A and 1B. Therefore, it is not necessary for the operator to check the polarity of the power supply conductor in advance, and the additional connection work of the power supply unit 40 is facilitated.
The operation of the polarity switching circuit when a power supply unit is added to a power supply system that is already in operation will be described below. In this description, it is assumed that the power supply conductor 1A is a positive electrode to which a voltage of + 12V is applied, the power supply conductor 1B is a negative electrode to which a voltage of 0V is applied, and the DC power supply supplies a DC voltage of 12V.
1) When the first output terminal OUT1 is connected to the positive feed conductor 1A and the second output terminal OUT2 is connected to the negative feed conductor 1B. In this case, the source S of the first switch SW1 and the second switch SW2 In both cases, the positive voltage 12V from the DC power supply is applied, and 0V from the DC power supply is applied to the sources S of the third switch SW3 and the fourth switch. On the other hand, from the power feeding system, 12V is applied to the first output terminal OUT1, and 0V is applied to the second output terminal OUT2.
Therefore, in the first switch SW1, 0V from the second output terminal OUT2 becomes the gate voltage, the relationship of gate voltage (0V) <source voltage (12V) is satisfied, the first switch SW1 is turned on, In the two switch SW2, the gate voltage and the source voltage are both 12V, the on condition (gate voltage <source voltage) is not satisfied, and the second switch SW2 is turned off. In the third switch SW3, both the source voltage and the gate voltage are 0V, and the on condition (gate voltage> source voltage) is not satisfied, and the third switch SW3 is turned off. In the fourth switch SW4, the gate voltage (12V)> source The voltage (0V) is set, and the fourth switch SW4 is turned on. Accordingly, only the first switch SW1 and the fourth switch SW4 are turned on, the positive voltage 12V of the DC power supply is applied to the first output terminal OUT1, and the negative voltage 0V of the DC power supply is applied to the second output terminal OUT2. Thus, a DC power supply is added to the power feeding system with a polarity corresponding to the polarity of the power feeding system already in operation.
2) When the first output terminal OUT1 is connected to the negative power supply conductor 1B and the second output terminal OUT2 is connected to the positive power supply conductor 1B. In this case, the source S of the first switch SW1 and the second switch SW2 In both cases, the positive voltage 12V from the DC power supply is applied, and 0V from the DC power supply is applied to the sources S of the third switch SW3 and the fourth switch. On the other hand, from the power feeding system, 0 V is applied to the first output terminal OUT1, and 12 V is applied to the second output terminal OUT2.
For this reason, in the first switch SW1, 12V from the second output terminal OUT2 becomes the gate voltage, and the on condition (gate voltage <source voltage) is not satisfied, and the first switch SW1 is turned off. The second switch SW2 is turned on because the gate voltage (0V) <the source voltage (12V). Further, the third switch SW3 is turned on with the gate voltage (12V)> the source voltage (0V). In the fourth switch SW4, both the gate voltage and the source voltage become 0 V, and the on condition (gate voltage> source voltage) is not satisfied, and the fourth switch SW4 is turned off. Accordingly, only the second switch SW2 and the third switch SW3 are turned on, the positive voltage 12V of the DC power supply is applied to the second output terminal OUT2, and the negative voltage 0V of the DC power supply is applied to the first output terminal OUT2. Thus, a DC power supply is added to the power feeding system with a polarity corresponding to the polarity of the power feeding system already in operation.
3) When connecting the power supply unit to the power supply system for the first time In this case, the power supply conductors 1A and 1B are both 0 V, and in this state, the first output terminal OUT1 and the second output terminal OUT2 of the power supply unit 40 are connected to the power supply conductor. Then, a substantial voltage is not applied to the first output terminal OUT1 and the second output terminal OUT2. Immediately after the connection, 12V is applied to each gate G of the first switch SW1 and the second switch SW2 from the positive input terminal IN + via the parasitic capacitances C1 and C2, and charging of the parasitic capacitances C1 and C2 is started. Immediately after the connection, the first switch SW1 and the second switch SW2 are both turned off because the gate voltage is 12V and the source voltage is 12V. However, the gate voltage is increased as the parasitic capacitors C1 and C2 are charged. Is turned on when is lower than 12V. Here, each charging circuit in each switch is composed of parasitic capacitances C1 and C2 and resistors R1 and R2 connected thereto, and R1 = 1 kΩ, R2 is 2 kΩ, and the time constant of the charging circuit of the first switch. Is faster than the second switch. For this reason, the first switch is turned on earlier because the gate voltage drop of the first switch SW becomes faster than the second switch. As a result, 12V from the DC power supply is applied to the first output terminal OUT1, and accordingly, the gate of the second switch SW2 is fixed at 12V, and the OFF of the second switch SW is determined. . Since the gate voltage and the source voltage are both fixed to 0V immediately after connection, the third switch SW3 is kept off. On the other hand, the fourth switch SW4 is off because the gate voltage and the source voltage are both 0V immediately after the connection, but the first switch SW1 is turned on and the voltage of the first output terminal OUT1 becomes 12V. Accordingly, when the gate voltage becomes 12 V, the on condition (gate voltage <source voltage) is satisfied and the gate voltage is turned on. Therefore, when the power supply unit is connected to the power supply system for the first time, the positive electrode 12V of the DC power supply is preferentially applied to the first output terminal OUT1.
If the relationship between the resistors R1 and R2 is R1 <R2, immediately after the connection, the second switch SW2 is turned on first, the second switch SW2 and the third switch SW3 are turned on, and the first switch SW1 and the fourth switch are turned on. SW4 is turned off, and a positive electrode of 12V is applied to the second output terminal OUT2, and a negative electrode of 0V is applied to the first output terminal OUT1.
In this embodiment, the first switch SW1 is set to be turned on earlier than the second switch SW2 with a clear difference between the resistance values of the resistors R1 and R2. Is expected to have a difference in time constant due to variations in resistance and parasitic capacitance. Therefore, using such variations, a set of the first switch SW1 and the fourth switch SW4 and a second switch SW2 are used. And the third switch SW3 are preferentially turned on, and it is determined that one of the power supply conductors 1A and 1B is used as a positive electrode. Thereafter, when the power supply unit 40 is added, the polarity of the power supply conductors 1A and 1B is determined as described above, and the output polarity of the power supply unit to be added is matched with the polarity of the existing power supply system.
By the way, the time constants of the charging circuits of the first switch SW1 and the second switch SW2 are expected to be different depending on variations in the resistances R1, R2 and the parasitic capacitances C1, C2, but in the unlikely event both time constants coincide. In this case, the time constant of the charging circuit in the third switch SW3 and the fourth switch SW4 is also different due to variations in resistance and parasitic capacitance, so that the set of the first switch SW1 and the fourth switch SW4, It is determined that one of the pair of the second switch SW2 and the third switch SW3 is turned on preferentially, and one of the power supply conductors 1A and 1B is set as the positive electrode.
That is, after the power supply unit is connected, both the first switch SW1 and the second switch SW2 are temporarily turned on so that a voltage of 12V is applied to the first output terminal OUT1 and the second output terminal OUT2. In this case, this voltage is applied between the resistors R3, R4 and the parasitic capacitors C3, C4 between the negative input terminal IN- (0V) to charge the parasitic capacitors C3, C4 of each charging circuit. become. In this case, since the source voltage of the third switch SW3 and the fourth switch SW4 is 0 V, which is the same potential as the negative input terminal, the time constant of the charging circuit of the fourth switch SW4 is the time constant of the charging circuit of the third switch SW3. Is smaller than the charging speed of the parasitic capacitances C3 and C4, the gate voltage of the fourth switch SW4 rises from 0V faster than the third switch SW3, so that the fourth switch SW4 is turned on first. And the second output terminal OUT2 is determined as a negative electrode. As a result, the gate voltage of the third switch SW3 is fixed at 0V and becomes equal to the source voltage (0V), so that the third switch SW3 is turned off. At the same time, the gate voltage of the first switch SW1 is fixed to 0V, so that the first switch SW1 is turned on. Accordingly, the first output terminal OUT1 is fixed to 12V, so that the second switch SW2 is turned on. The gate voltage is fixed at 12V, and OFF of the second switch SW2 is determined. Thereby, the positive electrode from the DC power supply is applied to the first output terminal OUT1. Similarly, if the time constant of the charging circuit of the third switch SW3 is smaller than the time constant of the charging circuit of the fourth switch SW4, the charging speed to the parasitic capacitances C3 and C4 is different, so that the third switch SW3 is As a result, the fourth switch SW4 and the first switch SW1 are turned off, the second switch SW2 is turned on, and the positive electrode from the DC power supply is applied to the second output terminal OUT2.
Thus, the time constant of the charging circuit of the first switch and the second switch and the time constant of the charging circuit of the third switch and the fourth switch are due to variations in the resistors R1 to R4 and the parasitic capacitances C1 to C4. Since a difference is expected to occur, the positive electrode of the DC power supply can be preferentially assigned to one of the first output terminal OUT1 and the second output terminal OUT2 due to the difference. However, in the present embodiment, R1 <R2 or R3 = R2 (R3 = 2KΩ, R4 = 1kΩ) and R1 <R2 in order to provide consistent and stable operation. The positive electrode of the DC power supply is output. Of course, R1> R2 or R1 = R2 and R3 <R4 may be set, and the positive electrode of the DC power supply may be output to the second output terminal OUT2.
4 to 6 show a modification of the above-described polarity switching circuit. In the modification of FIG. 4, resistors R1 and R2 are connected only to the first switch SW1 and the second switch SW2, and the charging circuit is changed. An example in which the values of R1 and R2 are different from each other is shown. In the modified embodiment of FIGS. 5 and 6, resistors R3 and R4 are connected only to the third switch SW3 and the fourth switch SW4 to form a charging circuit. An example in which the values of R3 and R4 are different will be shown.
In the above-described embodiment and modification, the example in which the charging circuit is added to the corresponding switch using the parasitic capacitance of the switching element is shown, but the present invention is not necessarily limited to this, for example, A charging circuit may be formed by a combination of an inductor and a resistor.
FIG. 7 shows still another modification of the polarity switching circuit of the above-described embodiment. In this modification, voltage dividing resistors R11, R21, R31, and R41 are connected to the resistors R1 to R4 constituting each charging circuit, respectively, so that the voltage applied to the gate of each switching element is kept low. Yes. This configuration is useful for protecting the switching element when the output voltage of the DC power supply 10 is, for example, 24 V and exceeds the allowable gate-source voltage in the MOSFET used as the switching element.
Hereinafter, a specific connection relationship of each voltage dividing resistor will be described. In the first switch SW1, the first voltage dividing resistor R11 is connected in series with the first resistor R1 between the positive input terminal IN + and the second output terminal OUT2, and the first voltage dividing resistor R11 and the first resistor R1. The gate G of the switching element is connected to the connection point between the two. In the second switch SW2, the second voltage dividing resistor R21 is connected in series with the second resistor R2 between the positive input terminal IN + and the first output terminal OUT1, and the second voltage dividing resistor R21 and the second resistor R2 are connected. The gate G of the switching element is connected to the connection point between the two. In the third switch SW3, the third voltage dividing resistor R31 is connected in series with the third resistor R3 between the negative input terminal IN− and the second output terminal OUT2, and the third voltage dividing resistor R31 and the third resistor are connected. The gate G of the switching element is connected to the connection point between R3. In the fourth switch SW4, the fourth voltage dividing resistor R41 is connected in series with the fourth resistor R4 between the negative input terminal IN− and the first output terminal OUT1, and the fourth voltage dividing resistor R41 and the fourth resistor are connected. The gate G of the switching element is connected to the connection point between R4.
Further, in this modification, the respective voltage dividing resistors R11, R21, R31, R41, connects the Zener diode ZD1, ZD2, ZD3, ZD4 in series. That is, the first Zener diode ZD1 is inserted between the first voltage dividing resistor R11 and the positive input terminal IN +, and the second Zener diode ZD2 is inserted between the second voltage dividing resistor R21 and the positive input terminal IN +. The third Zener diode ZD3 is inserted between the third voltage dividing resistor R31 and the negative input terminal IN-, and the fourth Zener diode ZD4 is inserted between the fourth voltage dividing resistor R41 and the negative input terminal IN-. Inserted into.
<Second Embodiment>
FIG. 8 shows a polarity switching circuit according to the second embodiment of the present invention. In this embodiment, a bipolar transistor is used as each of the switches SW1 to SW4, and a control circuit 100 that detects the potentials of the first output terminal OUT1 and the second output terminal OUT2 and controls each switch is provided.
The first switch SW1 is an NPN-type bipolar transistor. The collector is coupled to the positive input terminal IN + and the emitter is connected to the first output terminal OUT1. The first switch SW1 is turned on when the base voltage exceeds the threshold value, and the positive input terminal. Connect IN + to the first output terminal OUT1. The second switch SW2 is an NPN-type bipolar transistor. The collector is coupled to the positive input terminal IN + and the emitter is connected to the second output terminal OUT2. The second switch SW2 conducts when the base voltage exceeds the threshold value, and the positive input terminal. Connect IN + to the second output terminal OUT2. The third switch SW3 is a PNP-type bipolar transistor, whose collector is coupled to the negative input terminal IN− and whose emitter is connected to the first output terminal OUT1. Connect the terminal IN− to the first output terminal OUT1. The fourth switch SW4 is a PNP-type bipolar transistor. The collector is coupled to the negative input terminal and the emitter is connected to the second output terminal OUT2. The fourth switch SW4 conducts when the base voltage becomes less than the threshold, and the negative input terminal IN. -Is connected to the second output terminal.
The control circuit 100 is configured to detect the first potential applied to the first output terminal OUT1 and the second potential applied to the second output terminal OUT2 to control the switches SW1 to SW4. To achieve the function.
i) When the first potential is higher than the second potential, a control voltage higher than the threshold is applied to the bases of the first switch SW1 and the third switch SW3, and the bases of the second switch SW2 and the fourth switch SW4 are applied. Give a control voltage below the threshold.
ii) When the first potential is smaller than the second potential, a control voltage less than the threshold is applied to the bases of the first switch SW1 and the third switch SW3, and the bases of the second switch SW2 and the fourth switch SW4 are applied. Give a control voltage above the threshold.
iii) When the first potential and the second potential are the same potential, a control voltage less than a threshold value is applied to each base of the first switch SW1 and the third switch SW3, and each of the second switch SW2 and the fourth switching SW4 Apply a control voltage below the threshold to the base.
In order to realize this function, the control circuit 100 detects the first potential applied to the first output terminal OUT1, and outputs a first detection signal when the first potential is equal to or higher than a predetermined value. The second detection means (comparator) 102 that detects the second potential applied to the means (comparator) 101 and the second output terminal OUT2 and outputs a second detection signal when the second potential is greater than or equal to a predetermined value. And a logic means (NOR gate) 110 that applies a predetermined control voltage to the determination means (OR gate) 130 only when both the first detection signal and the second detection signal do not exist at the same time. The second detection voltage is commonly applied to the bases of the second switch SW2 and the fourth switch SW4, and is set to be equal to or higher than the above threshold.
The determination unit 130 is configured to apply a drive voltage exceeding a threshold value of the base voltage to the bases of the first switch SW1 and the third switch SW3 when receiving at least one of the control voltage and the first detection voltage. Is done.
The control circuit 100 is provided with a delay means 120 including a resistor R5, a capacitor C5, and a comparator 121. The control circuit 100 delays the control voltage output from the logic means (NOR gate) 110 and then sends this to the determination means 130. Output.
The operation of the polarity switching circuit according to this embodiment will be described below. In this description, for ease of understanding, for convenience, the output voltage of the DC power supply and the operating voltage in the power supply system are set to 12 V, and the first detection means 101, the second detection means 102, the logic means 110, and the determination means 130 are used. Is set to 12V or 0V, and can actually be a different value from the viewpoint of circuit design.
1) When the first output terminal OUT1 is connected to the positive feed conductor 1A and the second output terminal OUT2 is connected to the negative feed conductor 1B, the voltage applied to the first output terminal OUT1 is 12V, and the second output When the voltage applied to the terminal OUT2 is 0V and the reference value in the first detection means 101 and the second detection means 102 is less than 12V, the first detection means 101 outputs a voltage signal of 12V as the first detection signal. The second detection means 102 outputs 0V and does not output the second detection signal. As a result, the output of the logic means 110 becomes 0V and no control voltage is output. For this reason, the delay unit 120 does not operate, and an output of 0 V is input to the determination unit 130. The determination unit 130 receives the 12V first detection signal from the first detection unit 101 and applies a 12V drive voltage to the bases of the first switch SW1 and the third switch SW3. As a result, the first switch SW1 is turned on and the third switch SW3 is turned off. On the other hand, since the output from the second detection means 102 is 0 V at the base of the second switch SW2 and the fourth switch SW4, the second detection signal is not given, the second switch SW2 is turned off, and the fourth switch SW4 is turned on. As a result, only the first switch SW1 and the fourth switch SW4 are turned on, the positive input terminal IN + is connected to the first output terminal OUT1, the negative input terminal IN− is connected to the second output terminal OUT2, and is already operating. A DC power supply is added to the power supply system with a polarity corresponding to the polarity of the power supply system.
2) When the first output terminal OUT1 is connected to the negative power supply conductor 1B and the second output terminal OUT2 is connected to the positive power supply conductor 1B, the first detection signal is output at 0V and the first detection signal is output. Instead, the second detection means 102 outputs a 12V second detection signal. In this case, the output of the logic means 110 is 0V, no control voltage is output, the delay circuit 120 does not operate, and one input of the determination means 130 is 0V. Since 0V output from the first detection unit 101 is input to the other input of the determination unit 130, the determination unit 130 outputs 0V, and the drive voltage is supplied to the first switch SW1 and the third switch SW3. Do not give to the base. As a result, the first switch SW1 is turned off and the third switch SW3 is turned on. On the other hand, a 12V second detection signal from the second detection means 102 is applied to the bases of the second switch SW2 and the fourth switch SW4, the second switch SW2 is turned on, and the fourth switch SW4 is turned off. As a result, only the second switch SW2 and the third switch SW3 are turned on, the positive input terminal IN + is connected to the second output terminal OUT2, and the negative input terminal IN- is connected to the first output terminal OUT1, and is already in operation. A DC power supply is added to the power supply system with a polarity corresponding to the polarity of the power supply system.
3) When connecting the power supply unit to the power supply system for the first time In this case, the power supply conductors 1A and 1B are both 0 V, and in this state, the first output terminal OUT1 and the second output terminal OUT2 of the power supply unit 40 are connected to the power supply conductor. Then, both the first output terminal OUT1 and the second output terminal OUT2 become 0V, and both the first detection means 101 and the second detection means 102 output 0V, and do not output the first detection signal and the second detection signal. . As a result, the logic unit 110 outputs a control voltage of 12V, and this output is sent to the determination unit 130 via the delay circuit 120. The delay unit 120 delays the control voltage of 12V and outputs the delayed control voltage to the determination unit 130. As a result, the determination unit 130 initially receives 0V from the delay unit 120 and 0V from the first detection unit 101. 130 outputs 0V and does not give a driving voltage, but when a control voltage of 12V is input from the delay means 120 to the determining means 130 after that, the determining means 130 outputs a driving voltage of 12V. As a result, the first switch SW1 is turned on and the third switch SW3 is turned off. On the other hand, the third switch SW3 is turned off and the fourth switch SW4 is turned on by the 0V output from the second detection means 102. Therefore, when the power supply unit is connected to the power supply system for the first time, only the first switch SW1 and the fourth switch SW4 are turned on, and the positive electrode 12V of the DC power supply is preferentially applied to the first output terminal OUT1. Become.
<Third Embodiment>
FIG. 9 shows a polarity switching circuit according to the third embodiment of the present invention. In this embodiment, an electromagnetic relay is used as each of the switches SW1 to SW4, and a control circuit 100 similar to that of the second embodiment is provided.

第1スイッチSW1は駆動コイルを有する常開のリレーであり、共通端子（COM）が上記の正入力端子ＩＮ＋に接続され、ＮＯ接点が上記の第1出力端子に接続され、駆動コイルが励磁された時に、NO接点が閉じて、正入力端子ＩＮ+を第1出力端子OUT1に接続する。第２スイッチSW２は駆動コイルを有する常開のリレーであり、共通端子（COM）が正入力端子ＩＮ＋に接続され、ＮＯ接点が第２出力端子OUT2に接続され、駆動コイルが励磁された時に、NO接点が閉じて、正入力端子ＩＮ+を第２出力端子OUT2に接続する。第３スイッチSW３は駆動コイルを有する常閉のリレーであり、共通端子（COM）が負入力端子ＩＮ−に接続され、ＮＣ接点が第1出力端子OUT1に接続され、駆動コイルが励磁された時に、NC接点が開いて負入力端子ＩＮ-を第1出力端子OUT1から切断する。第４スイッチSW4は駆動コイルを有する常閉のリレーであり、共通端子（COM）が負入力端子ＩＮ−に接続され、ＮＣ接点が第２出力端子OUT2に接続され、駆動コイルが励磁された時に、NC接点が開いて、正入力端子ＩＮ+を第２出力端子OUT2から切断する。

制御回路１００は、第2の実施形態と同様に、第1出力端子OUT1に印加される第１電位を検出して、第１電位が所定以上の場合は、第１検知電圧を出力する第１検知手段１０１と、第２出力端子OUT2に印加される第２電位を検出して、第２電位が所定以上の場合は、第２の検知電圧を出力する第２の検知手段１０２と、第１検知信号と第2の検知信号の両方が同時に存在しない時のみに、所定の制御電圧を判定手段１３０に与える論理手段とを備える。この制御回路１００は、第1電位が第2電位よりも大きい場合に、第１スイッチSW1と第３スイッチSW３の駆動コイルを励磁し、第１電位より第2電位が大きい場合に、第２スイッチSW２と第４スイッチSW4の駆動コイルを励磁する。更に、この制御回路１００には、第１電位と第2電位とが同電位の場合に、第1出力端子OUT1及び第2出力端子OUT2をそれぞれ給電導体１A、１Bに接続した時点より所定の時間遅延させて、第１スイッチSW1と第３スイッチSW３の駆動コイルを励磁する遅延手段１２０が設けられる。第2の検知手段１０２からの第2の検知電圧は、第２スイッチSW２と第4スイッチSW4の励磁コイルに印加され、判定手段１３０は、制御電圧と上記の第１検知電圧との少なくも一方を受けた時に、第１スイッチSW1及び第３スイッチSW３の励磁コイルを励磁させる駆動電圧を与えるように構成され、遅延手段１２０は、この制御電圧を遅延させて判定手段１３０に与える回路（Ｒ５、Ｃ５）を備える。

本実施形態に係る極性切換回路の動作を以下に説明する。この説明では、理解を容易とするために、便宜上、直流電源の出力電圧及び給電システムでの動作電圧を１２Vとし、第１検知手段１０１や第２検知手段１０２や論理手段１１０や判定手段１３０からの出力を、１２Vまたは０Vとするものであり、実際は回路設計の観点から異なる値とすることができる。

１）第１出力端子ＯＵＴ１が、正極の給電導体１Ａに接続され、第２出力端子ＯＵＴ２が負極の給電導体１Ｂに接続された場合
第１出力端子OUT1に印加される電圧が１２V、第２出力端子OUT2に印加される電圧が０Vであり、第１検知手段１０１、第２検知手段１０２での基準値が１２V未満とすると、第１検知手段１０１は、第１検知信号として１２Vの電圧を出力し、第２検知手段１０２は出力が０Vとなって、第２検知信号を出力しない。この結果、論理手段１１０は０Vを出力し、遅延手段１２０は動作しない。判定手段１３０は、第１検知手段１０１からの０Vの入力と遅延手段１２０からの０Vの出力を受けて１２Vの駆動電圧を第１スイッチSW1と第３スイッチSW３の駆動コイルに与える。これによって、第1スイッチSW１のNO接点が閉じると共に、第３スイッチSW３のNC接点が開いて、正入力端子ＩＮ+が第1出力端子OUT1に接続され、負入力端子ＩＮ-が第1出力端子OUT１から切断される。一方、第２スイッチSW２と第３スイッチSW３の各駆動コイルは、第2検知手段１０２からの出力が０Vであるため、励磁されず、第２スイッチSW２のNO接点は開いたまま、第４スイッチSW4のNC接点は閉じた状態に維持され、負入力端子ＩＮ-が第2出力端子OUT2に接続される。この結果、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。

２）第１出力端子ＯＵＴ１が、負極の給電導体１Ｂに接続され、第２出力端子ＯＵＴ２が正極の給電導体１Ｂに接続された場合
第1検知手段１０１は０Vを出力して、第1検知信号を出力せず、第2検知手段１０２は１２Vの第2検知信号を出力する。これに伴って、論理手段１１０は０Vを出力し、制御電圧を与えないため、遅延回路１２０が動作しない。従って、判定手段１３０は０Ｖを出力して、第1スイッチSW1と第3スイッチSW3の駆動コイルが励磁されない。
この結果、第1スイッチSW1及び第3スイッチSW3は動作せず、第1出力端子OUT1が正入力端子ＩＮ+が切断され、負入力端子ＩＮ−が第1出力端子OUT1に接続される。一方、第2検知手段１０２からの１２Vの第2検知信号によって、第2スイッチSW2と第4スイッチSW4の駆動コイルが励磁され、第２スイッチSW２のNO接点が閉じ、第4スイッチSW4のNC接点が開くことで、正入力端子ＩＮ＋が第2出力端子OUT2に接続され、負入力端子ＩＮ-が第2出力端子OUT2から切断される。この結果、既に稼働している給電システムの極性に応じた極性で直流電源が給電システムに追加される。

３）最初に給電ユニットを給電システムに接続する場合
この場合、給電導体１Ａ、１Ｂは共に０Ｖであり、この状態で給電ユニット４０の第１出力端子ＯＵＴ１と第２出力端子ＯＵＴ２を給電導体に接続すると、第１出力端子ＯＵＴ１及び第２出力端子ＯＵＴ２は共に０Vの電圧となり、第１検知手段101と第2検知手段１０２は第1検知信号と第2検知信号を出力しない。その結果、論理手段１１０は１２Vの制御電圧を出力し、この出力が遅延回路１２０を介して、判定手段１３０に送られる。遅延手段１２０は１２Vの制御電圧を遅延させて判定手段１３０に出力する結果、判定手段１３０には、最初、遅延手段１２０から０V出力と、第1検知手段１０１から０Vの第１検知信号とが入力され、判定手段１３０の出力は０Ｖで駆動電圧を出力しないが、その後に、遅延手段１２０から１２Vの制御電圧が判定手段１３０に入力されて、判定手段１３０は１２Vの駆動電圧を出力する。その結果、第1スイッチSW1と第３スイッチSW３の駆動コイルが励磁され、第1スイッチSW１のNO接点が閉じ、第３スイッチSW３のNC接点が開き、正入力端子ＩＮ+が第1出力端子OUT1に接続され、負入力端子ＩＮ-が第1出力端子OUT2から切断される。

一方、第2検知手段１０２からの０Vの出力によって、第２スイッチSW２と第4スイッチSW4の駆動コイルは励磁されず、第２スイッチSW２のNO接点は開いたまま、第４スイッチSW4のNC接点は閉じた状態に維持され、負入力端子ＩＮ-が第2出力端子OUT2に接続される。従って、始めて給電ユニットを給電システムに接続する場合は、正入力端子ＩＮ＋が第1出力端子OUT1に接続されると共に、負入力端子ＩＮ-が第2出力端子OUT2に接続され、第１出力端子ＯＵＴ１へ優先的に直流電源の正極１２Vが印加されることになる。The first switch SW1 is a normally open relay having a drive coil, the common terminal (COM) is connected to the positive input terminal IN +, the NO contact is connected to the first output terminal, and the drive coil is excited. The NO contact closes and the positive input terminal IN + is connected to the first output terminal OUT1. The second switch SW2 is a normally open relay having a drive coil. When the common terminal (COM) is connected to the positive input terminal IN +, the NO contact is connected to the second output terminal OUT2, and the drive coil is excited, The NO contact closes and the positive input terminal IN + is connected to the second output terminal OUT2. The third switch SW3 is a normally closed relay having a drive coil. When the common terminal (COM) is connected to the negative input terminal IN-, the NC contact is connected to the first output terminal OUT1, and the drive coil is excited. The NC contact is opened and the negative input terminal IN- is disconnected from the first output terminal OUT1. The fourth switch SW4 is a normally closed relay having a drive coil. When the common terminal (COM) is connected to the negative input terminal IN-, the NC contact is connected to the second output terminal OUT2, and the drive coil is excited. The NC contact opens, and the positive input terminal IN + is disconnected from the second output terminal OUT2.

As in the second embodiment, the control circuit 100 detects the first potential applied to the first output terminal OUT1, and outputs the first detection voltage when the first potential is greater than or equal to a predetermined value. Detecting the second potential applied to the detection means 101 and the second output terminal OUT2, and if the second potential is greater than or equal to a predetermined value, the second detection means 102 for outputting the second detection voltage; And a logic unit that applies a predetermined control voltage to the determination unit 130 only when both the detection signal and the second detection signal do not exist simultaneously. The control circuit 100 excites the drive coils of the first switch SW1 and the third switch SW3 when the first potential is greater than the second potential, and the second switch when the second potential is greater than the first potential. Excites the drive coil of SW2 and the fourth switch SW4. Further, the control circuit 100 has a predetermined time from when the first output terminal OUT1 and the second output terminal OUT2 are connected to the feed conductors 1A and 1B, respectively, when the first potential and the second potential are the same potential. Delay means 120 for exciting the drive coils of the first switch SW1 and the third switch SW3 with delay is provided. The second detection voltage from the second detection means 102 is applied to the exciting coils of the second switch SW2 and the fourth switch SW4, and the determination means 130 determines at least one of the control voltage and the first detection voltage. The delay unit 120 is configured to apply a drive voltage for exciting the excitation coils of the first switch SW1 and the third switch SW3 when the signal is received, and the delay unit 120 delays the control voltage and supplies it to the determination unit 130 (R5, C5).

The operation of the polarity switching circuit according to this embodiment will be described below. In this description, for ease of understanding, for convenience, the output voltage of the DC power supply and the operating voltage in the power supply system are set to 12 V, and the first detection means 101, the second detection means 102, the logic means 110, and the determination means 130 are used. Is set to 12V or 0V, and can actually be a different value from the viewpoint of circuit design.

1) When the first output terminal OUT1 is connected to the positive feed conductor 1A and the second output terminal OUT2 is connected to the negative feed conductor 1B, the voltage applied to the first output terminal OUT1 is 12V, and the second output When the voltage applied to the terminal OUT2 is 0V and the reference value of the first detection means 101 and the second detection means 102 is less than 12V, the first detection means 101 outputs a voltage of 12V as the first detection signal. Then, the second detection means 102 outputs 0V and does not output the second detection signal. As a result, the logic means 110 outputs 0V and the delay means 120 does not operate. The determination unit 130 receives the 0V input from the first detection unit 101 and the 0V output from the delay unit 120 and applies a 12V drive voltage to the drive coils of the first switch SW1 and the third switch SW3. As a result, the NO contact of the first switch SW1 is closed, the NC contact of the third switch SW3 is opened, the positive input terminal IN + is connected to the first output terminal OUT1, and the negative input terminal IN− is the first output terminal. Disconnected from OUT1. On the other hand, the drive coils of the second switch SW2 and the third switch SW3 are not excited because the output from the second detection means 102 is 0V, and the NO switch of the second switch SW2 remains open, and the fourth switch. The NC contact of SW4 is kept closed, and the negative input terminal IN− is connected to the second output terminal OUT2. As a result, a DC power supply is added to the power supply system with a polarity corresponding to the polarity of the power supply system that is already in operation.

2) When the first output terminal OUT1 is connected to the negative power supply conductor 1B and the second output terminal OUT2 is connected to the positive power supply conductor 1B, the first detection means 101 outputs 0V, and the first detection signal The second detection means 102 outputs a 12V second detection signal. Along with this, the logic means 110 outputs 0 V and does not give a control voltage, so that the delay circuit 120 does not operate. Accordingly, the determination unit 130 outputs 0 V, and the drive coils of the first switch SW1 and the third switch SW3 are not excited.
As a result, the first switch SW1 and the third switch SW3 do not operate, the first output terminal OUT1 is disconnected from the positive input terminal IN +, and the negative input terminal IN− is connected to the first output terminal OUT1. On the other hand, the drive coil of the second switch SW2 and the fourth switch SW4 is excited by the 12V second detection signal from the second detection means 102, the NO contact of the second switch SW2 is closed, and the NC contact of the fourth switch SW4. Is opened, the positive input terminal IN + is connected to the second output terminal OUT2, and the negative input terminal IN− is disconnected from the second output terminal OUT2. As a result, a DC power supply is added to the power supply system with a polarity corresponding to the polarity of the power supply system that is already in operation.

3) When connecting the power supply unit to the power supply system for the first time In this case, the power supply conductors 1A and 1B are both 0 V, and in this state, the first output terminal OUT1 and the second output terminal OUT2 of the power supply unit 40 are connected to the power supply conductor. Then, both the first output terminal OUT1 and the second output terminal OUT2 have a voltage of 0 V, and the first detection means 101 and the second detection means 102 do not output the first detection signal and the second detection signal. As a result, the logic unit 110 outputs a control voltage of 12V, and this output is sent to the determination unit 130 via the delay circuit 120. The delay unit 120 delays the control voltage of 12V and outputs the delayed control voltage to the determination unit 130. As a result, the determination unit 130 initially receives the 0V output from the delay unit 120 and the first detection signal of 0V from the first detection unit 101. The determination unit 130 outputs 0V and does not output a driving voltage. However, after that, a 12V control voltage is input to the determination unit 130 from the delay unit 120, and the determination unit 130 outputs a 12V driving voltage. As a result, the drive coils of the first switch SW1 and the third switch SW3 are excited, the NO contact of the first switch SW1 is closed, the NC contact of the third switch SW3 is opened, and the positive input terminal IN + is the first output terminal OUT1. And the negative input terminal IN− is disconnected from the first output terminal OUT2.

On the other hand, the drive coil of the second switch SW2 and the fourth switch SW4 is not excited by the 0V output from the second detection means 102, and the NO contact of the second switch SW2 is kept open, and the NC contact of the fourth switch SW4. Is kept closed, and the negative input terminal IN- is connected to the second output terminal OUT2. Therefore, when the power feeding unit is connected to the power feeding system for the first time, the positive input terminal IN + is connected to the first output terminal OUT1, the negative input terminal IN- is connected to the second output terminal OUT2, and the first output terminal OUT1. The positive electrode 12V of the DC power source is applied with priority.

Claims (6)

直流電源と負荷との間に介在して、負荷に繋がる２本の給電導体へ直流電源を接続するための極性切換回路であって、A polarity switching circuit for interfacing between a DC power source and a load and connecting the DC power source to two power supply conductors connected to the load,
上記直流電源の正極に接続される正入力端子ＩＮ＋と、  A positive input terminal IN + connected to the positive electrode of the DC power source;
上記直流電源の負極に接続される負入力端子ＩＮ−と、  A negative input terminal IN− connected to the negative electrode of the DC power supply;
上記２本の給電導体の一方に接続される第１出力端子ＯＵＴ１と、  A first output terminal OUT1 connected to one of the two feeding conductors;
上記２本の給電導体の他方に接続される第２出力端子ＯＵＴ２と、  A second output terminal OUT2 connected to the other of the two feeding conductors;
上記正入力端子と上記第１出力端子との間に挿入した第１スイッチＳＷ１と、  A first switch SW1 inserted between the positive input terminal and the first output terminal;
上記正入力端子と上記第２出力端子との間に挿入した第２スイッチＳＷ２と、  A second switch SW2 inserted between the positive input terminal and the second output terminal;
上記負入力端子と上記第１出力端子との間に挿入した第３スイッチＳＷ３と  A third switch SW3 inserted between the negative input terminal and the first output terminal;
上記負入力端子と上記第２出力端子との間に挿入した第４スイッチＳＷ４と、  A fourth switch SW4 inserted between the negative input terminal and the second output terminal;
で構成され、Consists of
上記第１スイッチＳＷ１と第４スイッチＳＷ４は、上記第１出力端子ＯＵＴ１に印加される電圧が上記第２出力端子に印加される電圧よりも高い場合に導通して、上記正入力端子ＩＮ＋を上記第１出力端子ＯＵＴ１に接続すると共に、上記負入力端子ＩＮ−を上記第２出力端子ＯＵＴ２に接続するように構成され、  The first switch SW1 and the fourth switch SW4 are turned on when the voltage applied to the first output terminal OUT1 is higher than the voltage applied to the second output terminal, and the positive input terminal IN + is connected to the first input terminal IN +. The negative output terminal IN− is connected to the second output terminal OUT2 and connected to the first output terminal OUT1,
上記第２スイッチＳＷ２と上記第３スイッチＳＷ３は、上記第１出力端子ＯＵＴ１に印加される電圧が上記第２出力端子ＯＵＴ２に印加される電圧よりも小さい場合に導通して、上記正入力端子ＩＮ＋を上記第２出力端子に接続すると共に、上記負入力端子ＩＮ−を上記第１出力端子に接続するように構成され、  The second switch SW2 and the third switch SW3 are turned on when the voltage applied to the first output terminal OUT1 is smaller than the voltage applied to the second output terminal OUT2, and the positive input terminal IN + Is connected to the second output terminal, and the negative input terminal IN− is connected to the first output terminal,
上記第１スイッチは、制御端Ｇを有する第１スイッチング素子を備え、この第１スイッチング素子はこの制御端と上記正入力端子との間に所定値未満の電圧が印加された時に導通し、  The first switch includes a first switching element having a control terminal G, and the first switching element conducts when a voltage less than a predetermined value is applied between the control terminal and the positive input terminal.
上記第２スイッチは、制御端Ｇを有する第２スイッチング素子を備え、この第２スイッチング素子はこの制御端と上記正入力端子との間に所定値未満の電圧が印加された時に導通し、  The second switch includes a second switching element having a control terminal G, and the second switching element conducts when a voltage less than a predetermined value is applied between the control terminal and the positive input terminal,
上記第３スイッチは、制御端Ｇを有する第３スイッチング素子を備え、この第３スイッチング素子はこの制御端と上記正入力端子との間に所定値を超える電圧が印加された時に導通し、  The third switch includes a third switching element having a control terminal G, and the third switching element conducts when a voltage exceeding a predetermined value is applied between the control terminal and the positive input terminal.
上記第４スイッチは、制御端Ｇを有する第４スイッチング素子を備え、この第４スイッチング素子はこの制御端と上記正入力端子との間に所定値を超える電圧が印加された時に導通し、  The fourth switch includes a fourth switching element having a control terminal G, and the fourth switching element is turned on when a voltage exceeding a predetermined value is applied between the control terminal and the positive input terminal.
上記第１スイッチング素子の制御端と上記第３スイッチング素子の制御端が共に上記第２出力端子ＯＵＴ２に接続され、  The control terminal of the first switching element and the control terminal of the third switching element are both connected to the second output terminal OUT2,
上記第２スイッチング素子の制御端と上記第４スイッチング素子の制御端が共に上記第１出力端子ＯＵＴ１に接続され、  The control terminal of the second switching element and the control terminal of the fourth switching element are both connected to the first output terminal OUT1,
上記第１スイッチは、上記の第１スイッチング素子の制御端に上記正極からの上記所定値以上の制御電圧を与えた後に所定時間遅延させて、この制御端に上記所定値未満の電圧を与える第１遅延回路（Ｒ１、Ｃ１）を備え、  The first switch delays a predetermined time after applying a control voltage higher than the predetermined value from the positive electrode to the control terminal of the first switching element, and applies a voltage less than the predetermined value to the control terminal. 1 delay circuit (R1, C1),
上記第２スイッチは、上記の第２スイッチング素子の制御端に上記正極からの上記所定値以上の制御電圧を与えた後に所定時間遅延させて、この制御端に上記所定値未満の電圧を与える第２遅延回路（Ｒ２、Ｃ２）を備え、  The second switch delays a predetermined time after applying a control voltage higher than the predetermined value from the positive electrode to the control terminal of the second switching element, and applies a voltage less than the predetermined value to the control terminal. 2 delay circuits (R2, C2),
上記第１出力端子に印加される電圧が上記第２出力端子に印加される電圧よりも大きい時に、上記第１遅延回路が動作して、上記第２遅延回路は動作せず、  When the voltage applied to the first output terminal is greater than the voltage applied to the second output terminal, the first delay circuit operates and the second delay circuit does not operate;
上記第１出力端子に印加される電圧が上記第２出力端子に印加される電圧よりも小さい時に、上記第２遅延回路が動作して、上記第１遅延回路は動作せず、  When the voltage applied to the first output terminal is smaller than the voltage applied to the second output terminal, the second delay circuit operates, and the first delay circuit does not operate,
上記第１出力端子と上記第２出力端子にそれぞれ印加される電圧が等しい時に、  When the voltages applied to the first output terminal and the second output terminal are equal,
上記第１遅延回路と上記第２遅延回路が共に動作するが、上記第１遅延回路による遅延よりも上記第２遅延回路による遅延時間が長くなるように構成されたことを特徴とする極性切換回路。A polarity switching circuit characterized in that the first delay circuit and the second delay circuit operate together, but the delay time by the second delay circuit is longer than the delay by the first delay circuit. . 上記第１スイッチング素子はゲート・ソース間に寄生容量を有するＦＥＴであり、ソースが上記正入力端子に結合されると共にドレインが第１出力端子に接続され、ソース電圧がゲート電圧よりも所定値以上の時に導通して、上記の正入力端子を上記第１出力端子に接続し、
上記第１遅延回路は、上記寄生容量Ｃ１と、この寄生容量と直列に上記正入力端子と上記第２出力端子との間に挿入された第１抵抗Ｒ１とで構成されて、第１抵抗Ｒ１と寄生容量Ｃ１との間の接続点がゲートＧに接続され、
上記第２スイッチング素子はゲート・ソース間に寄生容量を有するＦＥＴであり、ソースが上記正入力端に結合されると共にトレインが第２出力端子に接続され、ソース電圧がゲート電圧よりも所定値以上の時に導通して、上記の正入力端子ＩＮ＋を上記第２出力端子ＯＵＴ２に接続し、
上記第２遅延回路（Ｒ２、Ｃ２）は、上記寄生容量Ｃ２と、この寄生容量と直列に上記正入力端子ＩＮ＋と上記第１出力端子ＯＵＴ１との間に挿入された第２抵抗Ｒ２とで構成されて、第２抵抗と寄生容量との間の接続点がゲートＧに接続され、
上記第１抵抗Ｒ１の抵抗値が第２抵抗Ｒ２の抵抗値よりも小さくて、第１遅延回路の時定数を第２遅延回路の時定数よりも小さくしたことを特徴とする請求項１に記載の極性切換回路。 The first switching element is an FET having a parasitic capacitance between a gate and a source, the source is coupled to the positive input terminal, the drain is connected to the first output terminal, and the source voltage is a predetermined value or more than the gate voltage. At the time of connecting the positive input terminal to the first output terminal,
The first delay circuit includes the parasitic capacitor C1 and a first resistor R1 inserted between the positive input terminal and the second output terminal in series with the parasitic capacitor, and the first resistor R1. And the parasitic capacitance C1 is connected to the gate G,
The second switching element is an FET having a parasitic capacitance between the gate and the source, the source is coupled to the positive input terminal, the train is connected to the second output terminal, and the source voltage is a predetermined value or more than the gate voltage. And the positive input terminal IN + is connected to the second output terminal OUT2.
The second delay circuit (R2, C2) includes the parasitic capacitor C2 and a second resistor R2 inserted between the positive input terminal IN + and the first output terminal OUT1 in series with the parasitic capacitor. The connection point between the second resistor and the parasitic capacitance is connected to the gate G,
The resistance of the first resistor R1 is smaller than the resistance value of the second resistor R2, wherein the time constant of the first delay circuit in claim 1, characterized in that it has less than the time constant of the second delay circuit polarity switching circuit. 上記正入力端子ＩＮ＋と上記第２出力端子との間で上記第１抵抗Ｒ１と直列に第１分圧抵抗が接続され、第１抵抗Ｒ１と上記第１分圧抵抗Ｒ１１との間の接続点に上記第１スイッチング素子のゲートが接続され、
上記正入力端子ＩＮ＋と上記第１出力端子との間で上記第２抵抗Ｒ２と直列に第２分圧抵抗が接続され、第２抵抗Ｒ２と上記第２分圧抵抗Ｒ２１との間の接続点に上記第２スイッチング素子のゲートが接続されたことを特徴とする請求項２に記載の極性切換回路。 A first voltage dividing resistor is connected in series with the first resistor R1 between the positive input terminal IN + and the second output terminal, and a connection point between the first resistor R1 and the first voltage dividing resistor R11. Is connected to the gate of the first switching element,
A second voltage dividing resistor is connected in series with the second resistor R2 between the positive input terminal IN + and the first output terminal, and a connection point between the second resistor R2 and the second voltage dividing resistor R21. The polarity switching circuit according to claim 2, wherein a gate of the second switching element is connected to the second switching element . 上記第１分圧抵抗Ｒ１１と上記正入力端子ＩＮ＋との間に第１ツェナーダイオードが挿入され、
上記第２分圧抵抗Ｒ２１と上記正入力端子ＩＮ＋との間に第２ツェナーダイオードが挿入されたことを特徴とする請求項３に記載の極性切換回路。 A first Zener diode is inserted between the first voltage dividing resistor R11 and the positive input terminal IN +;
4. The polarity switching circuit according to claim 3, wherein a second Zener diode is inserted between the second voltage dividing resistor R21 and the positive input terminal IN + . 請求項１〜４の何れかに記載の極性切換回路と、上記の直流電源とを備えた直流電圧給電ユニット。A DC voltage power supply unit comprising the polarity switching circuit according to claim 1 and the DC power source. 上記直流電源は、交流電源に接続されて交流電力を直流電力に変換するように構成され、交流電源との接続をオン・オフする電源スイッチが備えられたことを特徴とする請求項５に記載の直流電圧給電ユニット。 The said DC power supply is connected to AC power supply, and is comprised so that AC power may be converted into DC power, The power supply switch which turns on / off a connection with AC power supply was provided. DC voltage supply unit of.
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KR101861728B1 (en) * 2012-02-03 2018-05-30 삼성전자주식회사 DC power supply apparatus
US9300129B2 (en) * 2013-03-12 2016-03-29 Ascensia Diabetes Care Holding Ag Reverse battery protection for battery-powered devices
CN106329963B (en) * 2016-07-05 2019-05-28 濮阳市立圆汽车电器有限公司 A kind of power supply bridge-type switching device
CN109088391B (en) * 2018-09-18 2023-10-17 罗格朗智能电气(惠州)有限公司 Short-circuit protection circuit and nonstandard POE power supply
CN109910650B (en) * 2019-04-03 2021-09-17 上海歌尔泰克机器人有限公司 Contact charging device and unmanned aerial vehicle

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WO2008001644A1 (en) 2008-01-03
CN101479907B (en) 2011-07-13
JPWO2008001644A1 (en) 2009-11-26

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