JP4924007B2 - Power control circuit - Google Patents

Description

  The present invention relates to a power supply control circuit that controls the operation of a switching power supply, and more particularly to an IC (integrated circuit) power supply control circuit.

  A simple switching power source that converts an alternating current input from a commercial alternating current power source into a direct current and outputs it is used in a wide range of applications, and various types of switching power sources have been put into practical use. Some control circuits for controlling the operation of the switching power supply are integrated into ICs, which are packaged products.

  FIG. 4 is a diagram showing a circuit configuration of a general switching power supply controlled by such an IC power supply control circuit. Here, an example configured as a flyback converter is shown.

  In the circuit configuration shown in the figure, the alternating current from the commercial power supply AP1 is full-wave rectified by the diode stack DS1, and the direct current smoothed by the capacitor C1 is supplied to the primary winding N1 of the output transformer T1. A MOS transistor Q1, which is a switching element, is connected in series to the primary winding N1, and the MOS transistor Q1 is turned on (ON) and turned off (OFF) by a drive signal from the control IC 1 constituting the power supply control circuit. As a result, a pulsating flow is generated in the secondary winding N2 of the output transformer T1. This pulsating current is rectified by the diode D1, smoothed by the capacitor C2, and supplied to a load (not shown).

  The output voltage to the load is divided and detected by the resistors R1 and R2, and the detected value is input to the FB terminal of the control IC 1 as a feedback signal via the photocoupler PC1. Further, when a current flows through the primary winding N1 of the output transformer T1, a voltage is also generated in the auxiliary winding N3. This voltage is rectified by the diode D2, smoothed by the capacitor C3, and Vcc which is the power supply terminal of the control IC1. Supplied to the terminal.

  The CS terminal of the control IC 1 is externally provided with a capacitor C4 that determines a soft start time when the switching power supply is activated and a delay time until the switching of the MOS transistor Q1 is stopped when an abnormality occurs. C5 is a capacitor, ZD1 is a shunt regulator, R3 is a limiting resistor that limits current from the high voltage system, R4 is a detection resistor that detects the current of the MOS transistor Q1, R5 is a filter resistor that reduces noise to the IS terminal, and R6 is This is a resistor for adjusting the gate drive current of the power MOS transistor Q1.

  Here, in the case of the AC / DC power supply as described above, the control IC 1 for driving the external MOS transistor Q1 as a power switching element uses a general-purpose IC having a relatively inexpensive external terminal 8-pin configuration. It is common. In this case, in addition to the above three essential terminals of the Vcc terminal for power supply input, the GND terminal for grounding and the OUT terminal for gate drive of the MOS transistor Q1, the IS terminal for detecting the drain current of the MOS transistor Q1 and the feedback When 2 terminals for controlling the FB terminal for signal input are set, the remaining is 3 terminals.

  Among the remaining 3 terminals, the VH terminal has a high voltage switch function that supplies current (starting current and latch holding current) from the high voltage system to the Vcc terminal only when necessary, and reduces power consumption at light loads. If the NC terminal, which is a pin adjacent to the VH terminal, is excluded from the safety standard requirement, only one terminal can be used for other functions.

  Conventionally, using the remaining one terminal (CS terminal), a soft start function and a delay function until switching stop at the time of an abnormality such as an overload and its latch function (a part of the functions of the switching and power supply control circuit is stopped, It has been proposed to add a function that maintains only the minimum function of the power supply control circuit (see, for example, Patent Document 1). FIG. 5 is a diagram showing the configuration of such a conventional power supply control circuit. This power supply control circuit is configured in the control IC 1 and incorporates an activation element 101. The NC terminal is omitted.

  In the circuit of FIG. 5, reference numeral 102 denotes an internal voltage generation circuit that generates a reference voltage of 5 V, 103 denotes a 60 kHz oscillator, 104 denotes a one-shot circuit, 105 denotes a UVLO (Undervoltage Lockout) circuit, and 106 denotes an output buffer circuit. Further, FF101 is a flip-flop, CP101 to CP103 are comparators, CP104 is a PWM (Pulse Width Modulation) comparator, VP101 to VP105 are voltage sources, IP101 and IP102 are current sources, ZD101 to ZD103 are zener diodes, D101 to D103 are diodes, R101 to R105 are resistors, SW101 is a switch, A101 to A103 are AND gates, and B101 is a buffer.

The above circuit has a soft start function, an overload delay timer function, and a release function thereof. Hereinafter, each of these functions will be described.
The soft start function discharges a constant current of 10 μA from the current source IP101 connected to the Vcc terminal from the CS terminal when the voltage at the Vcc terminal exceeds the voltage of the voltage source VP105 and UVLO is released at the time of startup. Charge the external capacitor. When the voltage of the capacitor rises and exceeds the forward voltage 0.7V of the diode D103, the pulse width of the switching pulse output from the OUT terminal gradually increases due to the action of the PWM comparator CP104. At this time, the voltage at the CS terminal is compared by the PWM comparator CP104 in a manner equivalent to the voltage at the FB terminal, and the lower level is compared with the voltage at the IS terminal. For this reason, even if the voltage of the FB terminal rises to the maximum at the start-up, the voltage of the CS terminal is low, so the switching pulse width is limited. When the voltage at the CS terminal rises to about 2.7 V, the switching pulse width can be expanded to the maximum pulse width.

  The overload delay timer function sets an overload detection threshold level for the voltage at the FB terminal, and recognizes an overload condition when the voltage at the FB terminal exceeds that level. At that time, in a normal state where the voltage of the FB terminal is lower than the overload detection threshold level of 3.3 V (voltage of the voltage source VP102), the switch SW101 is closed (on), and the 4V Zener diode ZD102 or an element corresponding thereto A circuit that sucks a constant current of 50 μA from the current source IP102 is operated. At this time, if the voltage at the CS terminal is higher than the Zener voltage 4V of the Zener diode ZD102, the current of 10 μA supplied from the Vcc terminal via the current source IP101 is sucked, so the voltage at the CS terminal is maintained at 4V.

  In the state where the voltage of the FB terminal is higher than the overload detection threshold level, the above-described sink current is turned off, so that a capacitor externally connected to the CS terminal is charged by a current of 10 μA from the current source IP101. When the terminal voltage of the capacitor rises and the voltage at the CS terminal reaches the latch threshold level 8V (voltage of the voltage source VP101), the output of the comparator CP101 is inverted and shifts to the latch state. At this time, since the current from the current source IP101 continues to flow, the current finally rises to 9V clamp voltage by the Zener diode ZD103 and is maintained.

  To release the latch, when the power supply from the Vcc terminal is stopped and the voltage at the Vcc terminal drops to the UVLO off-threshold level (voltage of the voltage source VP105), the voltage at the CS terminal is switched by a switch (not shown). Is discharged. When the voltage at the CS terminal becomes equal to or lower than the latch detection level (7.5 V) of the comparator CP101, it is reset, and when the power supply is resumed, it can be restarted. The latch can also be released by forcibly lowering the voltage at the CS terminal to below the latch detection level by another external circuit.

Further, at the time of latching, the OUT terminal is fixed to L (low) level, the output of the internal control voltage 5V is stopped to reduce the current consumption, the activation element 101 connected to the VH terminal is turned on, and the current from the Vcc terminal To maintain the latched state.
Japanese Patent Laid-Open No. 10-108457 (paragraph number [0002], FIGS. 4 and 5)

  By the way, in the conventional power supply control circuit as described above, a control IC having a soft start function and an overload latch timer function is used to automatically recover the overload protection function from the latch stop (after being stopped for a certain period of time). When changing the specification to the method of automatically restarting, it will be as follows.

  In this case, when the voltage at the FB terminal is higher than the above-described overload detection threshold level, the voltage at the CS terminal rises, and the switching operation is stopped when the voltage exceeds the latch threshold level. At this time, if the starting element connected to the VH terminal is changed so as not to be turned on, the power supply from the auxiliary winding disappears after the switching is stopped, so that the voltage at the Vcc terminal gradually increases due to the current consumption at the time of latching. When the voltage drops to the UVLO off-threshold level, the circuit is reset, and the CS terminal voltage can be discharged to automatically restart the circuit.

  The time until the above restart, that is, the time until the power supply voltage of the Vcc terminal when the latch is stopped is lowered to the UVLO off-threshold level, the current consumption at the time of latching can be reduced. However, there is a problem in that the time to decrease to the UVLO off-threshold level varies depending on the voltage at the Vcc terminal when switching is stopped.

  Further, assuming a case where the DC output is completely short-circuited to GND by the operation of the switching power supply, in this case, the above-described automatic overload return operation is repeated. At this time, if the ratio of the time during which the switching element such as the external power MOSFET is switched is too large, it may overheat and cause thermal destruction. For this reason, it is necessary to control to some extent the ratio between the time when the output of the OUT terminal of the control IC is switched and the time when it is stopped.

  The present invention has been made in view of the above points, and is a control IC having a soft start function of a switching power supply and a delay function at the time of overload, and automatically recovers from stop to release in a protection operation at the time of overload. Even in this case, it is an object to provide a power supply control circuit that can prevent the switching element from being destroyed by overheating without specially controlling the ratio between the switching time and the stopping time.

  In the present invention, in order to solve the above problems, in an integrated circuit power supply control circuit that controls the operation of a switching power supply, a capacitor connected to a predetermined external terminal, a switching means for switching a charging current of the capacitor, A discharging means for discharging the capacitor; and controlling a charging / discharging current of the capacitor, a soft start time when starting the switching power supply, a delay time until the switching operation is stopped when an abnormality occurs, and the stopping There is provided a power supply control circuit characterized in that the release time until release is adjusted at a certain ratio.

  According to such a power supply control circuit, by controlling the charging / discharging current of the capacitor, the soft start time when starting the switching power supply, the delay time until stopping the switching operation in the event of an abnormality, and until the stop is released The release time is adjusted by a certain ratio, so the control IC with the soft start function of the switching power supply and the delay function at the time of overload automatically recovers from stop to release in the overload protection operation. However, it is not necessary to specifically control the ratio between the switching time and the stopping time, and the switching element can be prevented from being destroyed by overheating.

  The power supply control circuit of the present invention controls the charging / discharging current of the capacitor, the soft start time when starting the switching power supply, the delay time until the switching operation is stopped in the event of an abnormality, and the release until the stop is released Since the time is adjusted at a certain ratio, even if the control IC is equipped with a soft start function of the switching power supply and a delay function at the time of overload, even when it automatically recovers from stop to release in the overload protection operation, There is an advantage that the switching element can be prevented from being destroyed by overheating without specially controlling the ratio between the switching time and the stop time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a power supply control circuit according to an embodiment of the present invention. This power supply control circuit is used for a switching power supply as shown in FIG. 4, and is configured in a control IC 1 having an external pin of 8 pins and incorporates an activation element 11 to which power is supplied from a VH terminal. The NC terminal is omitted.

  In the circuit of FIG. 1, 12 is an internal voltage generation circuit that generates a voltage of 5 V, 13 is an oscillator with a frequency of 60 kHz, 14 is a one-shot circuit, 15 is a UVLO circuit having an on / off threshold level of 16 V / 9 V, The voltage of the voltage source VP7 is input. Reference numeral 16 denotes an output buffer circuit.

  FF1 to FF3 are flip-flops, CP1 to CP5 are comparators, and the comparator CP1 is a latch comparator that compares the voltage at the CS terminal (the terminal voltage of the capacitor connected to the CS terminal) with the voltage of 8V from the voltage source VP1. , The comparator CP2 is a reset comparator that compares the voltage of the CS terminal with the voltage of 0.5V of the voltage source VP2, the comparator CP3 is a comparator for switching control that compares the voltage of the CS terminal with the voltage of 3V of the voltage source VP3, The comparator CP4 is an overload detection comparator that compares the voltage of the FB terminal with the voltage of 3.3V of the voltage source VP4, and the comparator CP5 is for output control that compares the voltage of the FB terminal with the voltage of 0.4V of the voltage source VP5. The 5V voltage output from the internal voltage generation circuit 12 is a diode. Input through de D11, resistor R11.

  CP6 is a PWM comparator that compares the detected voltage obtained by dividing the voltage of the FB terminal passing through the diode D12 by 3: 1 with the resistors R12 and R13 with the voltage of the IS terminal. The voltage of the voltage source VP6 (reference voltage) and soft start A voltage is also input. IP1 is a 15 μA discharge current source, IP2 and IP3 are 40 μA and 10 μA charging current sources, IP4 is a 50 μA control current source, ZD11 is a 30V Zener diode, ZD12 is a 4V Zener diode, ZD13 is A 9V Zener diode, D11 to D13 are diodes, R14 and R15 are resistors, SW1 to SW6 are switches, A1 to A3 are AND gates, and B1 is a buffer.

  The power supply control circuit having the above configuration has a capacitor (capacitor C4 shown in FIG. 4) connected to the CS terminal, which is an external terminal, and switches the charging current of the capacitor as means for controlling charging and discharging of the capacitor. The switching means, the stopping means for stopping the charging of the capacitor, and the discharging means for discharging the capacitor are constituted by comparators CP1 to CP5, flip-flops FF1 to FF3, current sources IP1 to IP4, and Zener diodes ZD11 to ZD13. And by controlling the charging / discharging current of the capacitor, the soft start time when starting the switching power supply, the delay time until the switching operation is stopped at the time of abnormality, and the release time until the stop is canceled, Adjust at a certain ratio. In the embodiment, the soft start time, the delay time, and the release time are adjusted by switching the charging current of the capacitor by comparing the voltage of the CS terminal with a preset threshold level.

  Next, a specific operation of the power supply control circuit having the above configuration will be described. It is assumed that a capacitor of 0.5 μF is connected to the CS terminal, and the power supply control circuit of the embodiment uses this capacitor to realize a soft start function, an overload delay timer function, and a release function thereof. FIG. 2 is a timing chart showing the operation of the power supply control circuit according to the embodiment. The output voltage of the switching power supply, the FB terminal voltage, the CS terminal voltage, the Vcc terminal voltage, the ON / OFF of the starting element 11 and the switching by the OUT terminal output. The operation is shown.

  When input power is supplied to the VH terminal, the starting element 11 is turned on to charge the capacitor (capacitor C3 shown in FIG. 4) connected to the Vcc terminal. The voltage at the CS terminal is 0 V until the voltage at the Vcc terminal reaches the UVLO 16V on-threshold level (voltage of the voltage source VP7). This is because the CS terminal is fixed to the ground potential by a discharge switch that operates with a UVLO signal (not shown).

  When the voltage at the Vcc terminal exceeds 16V and the power supply voltage UVLO is released, charging of the capacitor connected to the CS terminal is started. Until the voltage of the capacitor, that is, the voltage of the CS terminal becomes 0.5 V, switching of the switching power supply by the output signal from the OUT terminal is in the off mode by the output of the comparator CP2, and 40 μA + 10 μA = 50 μA by the current sources IP2 and IP3. To charge the capacitor. This is because the flip-flop FF2 is set by the comparator CP2 when the voltage at the CS terminal is at the ground potential, and the Q output of the flip-flop FF2 becomes H (high), thereby closing the switch SW2 (at the same time) The flip-flop FF1 is reset and the switch SW1 is opened (off)). At this time, 5V of the internal voltage generation circuit 12 is still off.

  The soft start mode is until the voltage at the CS terminal changes from 0.5 V to 3 V, and the capacitor is charged at the above 50 μA. The soft start time until reaching 3V is t = (3V−0.5V) × 0.5 μF / 50 μA = 25 ms. At this time, when the voltage at the CS terminal becomes 2.7 V, the ON width of the switching by the signal at the OUT terminal can be expanded up to the maximum duty setting. That is, a voltage (= (CS terminal voltage−0.7 V) × 1/4) input from the CS terminal to the PWM comparator CP6 at 2.7 V is input to the other inverting input terminal of the PWM comparator CP6. It becomes equal to the voltage of 0.5V (voltage defining the maximum pulse width (maximum duty)) of the voltage source VP6. In the above formula, 0.7V is the forward voltage of the diode D13, and ¼ is the voltage divided by the resistors R14 and R15.

  When the voltage at the CS terminal becomes 3 V, the flip-flop FF2 is reset by the comparator CP3, the switch SW2 is opened (off), the 40 μA current source IP2 is cut off, and the charging current of the capacitor at the CS terminal becomes 10 μA. .

  If the voltage at the FB terminal is 3.3V or less, the switch SW4 is closed by the output of the comparator CP4, the current source IP4 of 50 μA is activated through the Zener diode ZD12, the charging current is all sucked, and the voltage at the CS terminal is clamped at 4V. Is done. When the voltage at the FB terminal becomes an overload state of 3.3 V or more, the switch SW4 is opened, and the capacitor at the CS terminal is charged with 10 μA of the current source IP3.

  When the voltage of the CS terminal rises to 8V, the flip-flop FF1 is set by the output of the comparator CP1, and switching of the switching power supply is stopped. The delay time until the switching is stopped is t = (8V-4V) × 0.5 μF / 10 μA = 200 ms.

  Here, the internal power supply output from the internal voltage generation circuit 12 is turned off to shift to a low current consumption state, the activation element 11 is turned on, and the power supply voltage at the Vcc terminal is maintained at the UVLO on-threshold level (16 V) or higher. . When the flip-flop FF1 is set, the switch SW1 is closed, the capacitor discharge current source IP1 is turned on, and a discharge current of 15 μA is sucked. At the CS terminal, the capacitor is discharged at 15 μA−10 μA = 5 μA. At this time, the discharge current by the current source IP1 may be 5 μA, and the 10 μA current source IP3 may be turned off by means not shown to turn on the 5 μA discharge current source IP1.

  When the voltage at the CS terminal decreases to 0.5V, the above stop state is released. This release period is t = (8V−0.5V) × 0.5 μF / 5 μA = 750 ms, which is about 750 ms.

  In the embodiment, the upper and lower threshold levels are set for the voltage at the CS terminal, and the charge / discharge of the capacitor is switched each time the voltage at the CS terminal reaches the threshold level. At that time, the switching operation of the switching power supply is controlled.

  In other words, if it is necessary to further reduce the ratio of the switching period, do not reset immediately after the voltage at the CS terminal has dropped to 0.5V, start charging, raise it to 8V, and discharge again. Next, if the counter is configured by adding one or several stages of toggle flip-flops after the output of the flip-flop FF1 so that the reset is performed when the voltage drops to 0.5 V, the stop period can be extended. . FIG. 3 shows a timing chart when one stage of the toggle flip-flop is added. The CS element voltage is switched from discharging to charging while the activation element 11 is turned on and the switching by the output of the OUT terminal is turned off. Repeat to increase to 8V, and then switch to discharge and decrease to 0.5V.

  If a counter with a larger number of bits is used in the above control, the capacity of the capacitor connected to the CS terminal can be reduced, and even if the soft start time is set shorter, the stop delay time and reset time can be set longer. . In this case as well, the control in A of FIG. 2 is repeated n (positive integer) times as described above.

It is a figure which shows the structure of the power supply control circuit of embodiment of this invention. 3 is a timing chart illustrating an operation of the power supply control circuit according to the embodiment. It is a timing chart at the time of adding a toggle flip-flop to the output of flip-flop (FF1). It is a figure which shows the circuit structure of a general switching power supply. It is a figure which shows the structure of the conventional power supply control circuit.

Explanation of symbols

1 Control IC
DESCRIPTION OF SYMBOLS 11 Starting element 12 Internal voltage generation circuit 13 Oscillator 14 1 shot circuit 15 UVLO circuit 16 Output amplifier A1-A3 AND gate B1 Buffer CP1-CP5 Comparator CP6 PWM comparator D11-D13 Diode FF1-FF3 Flip-flop IP1-IP4 Current source R11- R15 resistor SW1 to SW6 switch VP1 to VP7 voltage source ZD11 to ZD13 Zener diode

Claims (3)

In an integrated circuit power supply control circuit that controls the operation of a switching power supply,
A capacitor connected to a predetermined external terminal;
Switching means for switching the charging current of the capacitor;
Discharging means for discharging the capacitor,
By controlling the charging / discharging current of the capacitor, a soft start time at the start of the switching power supply, a delay time until the switching operation is stopped in the event of an abnormality, and a release time until the stop is canceled are constant. The power supply control circuit is characterized by being adjusted at a ratio of   2. The soft start time, the delay time, and the release time are adjusted by switching a charging current of the capacitor by comparing a voltage of the external terminal with a preset threshold level. Power supply control circuit.   Two upper and lower threshold levels are set for the voltage of the external terminal, and charging and discharging of the capacitor is switched each time the voltage of the external terminal reaches the threshold level, until the switching frequency reaches a predetermined number of times. The power supply control circuit according to claim 1, wherein the release time is set as the release time.

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