JP4918250B2 - Inverter device having inverter circuit protection means and control method thereof - Google Patents

Description

  The present invention relates to an inverter device having an inverter circuit protection means and an inverter control method.

  Conventionally, in an inverter device having a resonance circuit such as an induction heating device as a load, a PLL (Phase Locked Loop) is generally used for controlling the oscillation frequency of the inverter circuit. The PLL is composed of a phase comparison circuit, a low-pass filter, and a VCO (Voltage Controlled Oscillator). In controlling the oscillation frequency of the inverter circuit, for example, in a high frequency induction heating apparatus such as a quenching apparatus used in an automobile parts factory or the like, it is necessary to control an oscillation frequency having a width of about several kHz to about 400 kHz. In addition, when processing and processing parts having different sizes in one line, it is necessary to replace the heating coil of the high-frequency induction heating device, and the resonance frequency of the resonance load changes each time.

  When the resonance frequency changes in this way, in the PLL using the low-pass filter, the low-pass filter requires frequency characteristics corresponding to the resonance frequency of the load, and therefore the existence of the cutoff frequency of the low-pass filter becomes a problem. Further, since the oscillation frequency passes through the phase comparison circuit (Ex-OR type) and the low-pass filter, the oscillation frequency may converge to a value that is n times or 1 / n times the resonance frequency. Therefore, in the PLL using the low-pass filter, the controllable frequency range is limited. Therefore, in the conventional PLL, it is difficult to control the oscillation frequency over a wide band. It is also difficult to cope with the case where the resonance frequency of the load changes due to factors such as temperature characteristics. If the oscillation frequency band that can be controlled is narrow, the frequency range that can be handled by a single control device is narrowed. Therefore, in some cases, a plurality of control devices are required.

  A method for controlling the oscillation frequency of an inverter circuit without using a PLL circuit that performs analog processing as described above is disclosed in Patent Document 1. However, Patent Document 1 relates to an induction heating cooker. Generally, in an induction heating cooker, it is not necessary to control the oscillation frequency over a wide band. In Patent Document 1, it is only necessary to control a frequency with a width of 25 to 27 kHz ± 2 kHz as described in paragraph 0006. Therefore, Patent Document 1 does not plan to widen the oscillation frequency control, and does not disclose a configuration for realizing the wide band.

In addition, when there is an electrical short circuit in the coil, the heating target, and the path to the coil, the quality (such as the pattern of the hardened layer) may be affected in the quenching apparatus, or the coil may melt. In a PLL using a conventional low-pass filter, in order to protect the inverter circuit against such a situation, a signal output from the filter and input to the VCO is provided with an upper and lower limit value and monitored. When this signal deviates from the upper and lower limit values set as the allowable range, the inverter circuit is stopped. However, since the signal after passing through the low-pass filter is detected and monitored, the detection may be delayed and the inverter circuit may be destroyed. Further, the presence of the low-pass filter makes it difficult to adapt to the case where the resonance frequency of the load changes due to factors such as temperature characteristics.
JP 2003-86342 A

  In view of the above problems, for example, in an inverter device that needs to control a broadband oscillation frequency, such as a high-frequency induction heating device such as a quenching device used in an automobile parts factory, etc., the oscillation frequency of the inverter circuit is controlled in a wide band. There is a need to make it possible. Further, in such an inverter device that can be controlled in a wide band, in order to protect the inverter circuit, it is required to detect an abnormality earlier than before and stop the inverter circuit. Such a protective device is particularly required for an industrial induction heating apparatus that needs to control the oscillation frequency of the inverter circuit in a wide band.

  An apparatus according to the present invention includes a load that constitutes a resonance circuit, an inverter circuit that includes a switching element and supplies high frequency power to the load, and a time difference in phase between a voltage applied to the load and a current flowing through the load. A time difference detection means for detecting a value representing the time difference, a phase angle conversion means for converting the value representing the time difference into a phase angle value, and obtaining a difference between the phase angle value and a preset phase angle command value, The difference instruction is used to calculate a cycle instruction value that determines the period of the oscillation frequency of the inverter circuit, and to output the cycle instruction value, to obtain the period instruction value, and to obtain the cycle instruction value of the switching element of the inverter circuit An inverter drive signal for controlling on / off is generated based on the cycle instruction value, and an inverter drive signal generating means for outputting the drive signal to the inverter circuit; When the phase angle value converted by the phase angle converting means is compared with a preset monitoring phase angle value and the phase angle value is outside the range allowed as the monitoring phase angle value, the phase Phase angle monitoring means for outputting an angle abnormality detection signal to the inverter drive signal generation means. Further, the inverter drive signal generation means can be configured to stop the inverter circuit when the phase angle abnormality detection signal is acquired from the phase angle monitoring means.

  Further, the phase angle conversion means is a multiplication that multiplies a reciprocal number calculating means for calculating a reciprocal number of the period based on the cycle indication value, a value representing the time difference detected by the time difference detecting means and the reciprocal number of the period. Means.

  Comparing the cycle indication value calculated by the oscillation cycle calculation means with a preset monitoring cycle indication value, when the cycle indication value is outside the range allowed as the monitoring cycle indication value, Period indication value monitoring means for outputting a period indication value abnormality detection signal to the inverter drive signal generation means can be provided. Further, the inverter drive signal generation means can be configured to stop the inverter circuit when a period instruction value abnormality detection signal is acquired from the period instruction value monitoring means.

  In the device of the present invention, the resonance circuit may be a series resonance circuit. At this time, the voltage type inverter device includes a current detection unit that detects a current flowing through the load and applies a binarized current signal to the time difference detection unit in accordance with the sign of the current waveform. The device of the present invention can be configured.

  In the device of the present invention, the resonance circuit may be a parallel resonance circuit. At this time, a voltage detection unit is provided that detects a voltage applied to the load in the current type inverter device and applies a binarized voltage signal to the time difference detection unit in accordance with the polarity of the waveform of the voltage. Thus, the device of the present invention can be configured.

  Further, according to the present invention, the inverter drive signal generating means can comprise counting means for counting clock signals having a predetermined frequency, and the counting means can achieve the clock count up to a target count number indicated by the cycle indication value. Each time the signal is counted, the count number is reset, and the device of the present invention can be configured to generate the inverter drive signal based on the time obtained by counting to the target count number.

  The present invention also provides an inverter control method having the following characteristics. A method according to the present invention is an inverter control method for controlling an oscillation frequency of the inverter circuit in an inverter device including a load that configures a resonance circuit and an inverter circuit that includes a switching element and supplies high-frequency power to the load. A time difference detecting step of detecting a value representing a time difference in phase between a voltage applied to the load and a current flowing in the load, a phase angle converting step of converting the value representing the time difference into a phase angle value, An oscillation period calculating step for obtaining a difference between a phase angle value and a preset phase angle command value, calculating a period instruction value for determining a period of the oscillation frequency using the difference, and outputting the period instruction value And acquiring the cycle instruction value, an inverter drive signal for controlling on / off of the switching element of the inverter circuit, the cycle instruction value An inverter drive signal generation step for generating the output signal to the inverter circuit, and comparing the phase angle value converted in the phase angle conversion step with a preset monitoring phase angle value, When the angle value is out of the allowable range as the monitoring phase angle value, the phase angle monitoring step for outputting the phase angle abnormality detection signal and the phase angle abnormality detection signal are acquired, and the inverter circuit is stopped. An inverter stop step.

  Further, the phase angle conversion step includes a reciprocal calculation step for calculating a reciprocal of the cycle based on the cycle indication value, and a multiplication for multiplying a value representing the time difference detected by the time difference detection step by the reciprocal of the cycle. Steps.

  Further, the cycle indication value calculated in the oscillation cycle calculation step is compared with a preset monitoring cycle indication value, and this cycle indication value is a value outside the range allowed as the monitoring cycle indication value. In some cases, a cycle indication value monitoring step for outputting a cycle indication value abnormality detection signal can be provided, and the inverter stopping step includes obtaining the cycle indication value abnormality detection signal and stopping the inverter circuit. Can do.

  Further, in the voltage type inverter device in which the resonance circuit is a series resonance circuit, the present method detects a current flowing through the load and binarizes the current according to the sign of the current waveform. Current detection step for generating the current difference, and in the time difference detection step, the current binarization signal may be used to detect a value representing the time difference.

  Further, according to the present method, in the current type inverter device in which the resonance circuit is a parallel resonance circuit, a voltage binarization in which a voltage applied to the load is detected and binarized according to the sign of the voltage waveform A voltage detection step of generating a signal may be included, and in the time difference detection step, the voltage binarized signal may be used to detect a value representing the time difference.

  Further, in the method of the present invention, the inverter driving step includes a step of counting a clock signal having a predetermined frequency by a counting unit, and the counting unit counts the clock signal up to a target count number indicated by the cycle instruction value. Each time, the count number of the counter is reset, and the inverter drive signal is generated based on the time obtained by counting up to the target count number.

  In the device and method of the present invention, the value representing the time difference in phase between the voltage applied to the load and the current flowing through the load directly detects the voltage applied to the load and the current flowing through the load. It may be a value derived from this, or it may not be. When the device of the present invention is configured as a voltage type inverter device, the time when the count reaches the target count number and is reset and the time point of the rising point of the current binarization signal is obtained from the count number If the difference is taken, “a value representing a time difference in phase” is obtained. Therefore, in this case, it is not always necessary to actually measure the voltage in order to know the phase of the voltage applied to the load. Further, when the present invention device is configured as a current type inverter device, the time point when the count reaches the target count number and is reset and the time point of the rising point of the voltage binarization signal are obtained from the count number. If the difference from the one is taken, a “value representing the phase time difference” can be obtained. Therefore, in this case, it is not always necessary to actually measure the current in order to know the phase of the current flowing through the load.

  In the present invention, control of the oscillation frequency of the inverter circuit is realized without using a low-pass filter. Therefore, compared with a PLL using a conventional low-pass filter, it is not influenced by the frequency characteristics of the low-pass filter, and therefore, broadband frequency control is possible. In the present invention, a value representing a time difference in phase between the inverter output voltage (voltage applied to the load) and the inverter output current (current flowing through the load) is obtained, and an operation for converting it into a phase angle is performed. Thus, the obtained phase angle value is compared with a preset phase angle command value. When comparing with the target time difference using the time difference, it is necessary to adjust the preset target time difference every time the frequency changes. However, in the present invention, since the time difference is converted into the phase angle, it is not necessary to adjust the preset phase angle command value for each different frequency, and it is possible to deal with a wideband frequency.

  Further, since the abnormality of the phase angle value is monitored without going through the low-pass filter, it is possible to detect the abnormality earlier than before and stop the inverter circuit. Therefore, the failure of the inverter circuit can be reduced as compared with the conventional case.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. 1 and 2 show an electrical configuration of the inverter device according to the first embodiment of the present invention. FIG. 2 shows details of the inverter drive signal generator 16 in FIG. The inverter device 10 shown in FIG. 1 is configured as a voltage type inverter device, and is used for an induction heating device. The inverter device 10 includes a resonance load (a load constituting a resonance circuit) 11 and an inverter circuit 12. The inverter device 10 includes a time difference detection unit 13, a phase angle conversion unit 14, an oscillation period calculation unit 15, and an inverter drive signal generation unit 16. Further, the inverter device 10 is provided with a phase monitoring unit 60, a frequency upper / lower limit monitoring unit 61, an input side current monitoring unit 17, and an insulation / amplification unit 27.

  In the case of the voltage type inverter device, the resonance circuit of the resonance load 11 is a series resonance circuit, and in this embodiment, includes a heating coil Ls and a resonance capacitor Cs. Moreover, the resistance depending on the to-be-heated object heated by the inverter apparatus 10 is shown by Rs. The inverter circuit 12 includes a bridge circuit including two transistors whose gates are indicated by Ga (here, an insulated gate bipolar transistor can be used) and two transistors whose gates are indicated by Gb. ing. A diode is connected in antiparallel between the source and drain of each transistor. In addition, the inverter circuit 12 includes a DC power supply 26.

The inverter drive signal generation unit 16 includes a counter 20, a clock signal oscillation unit 21, a 50 percent duty ratio generation unit 22, a non-overlapping signal generation unit 50, and an abnormal time cutoff unit 51. Further, in this embodiment, the oscillation cycle calculation unit 15 includes an integrator 30 that performs an integration calculation for stabilizing the feedback control. The phase angle conversion unit 14 includes an inverse number calculation unit 40 and a multiplication unit 41. Moreover, in this embodiment which implement | achieves a voltage type inverter apparatus, the electric current detection part 18 is provided, and the electric current detection part 18 detects the sensor (not shown) which detects the output current (current which flows into load) i _inv of an inverter circuit. I have.

FIG. 3 schematically shows signal waveforms in the inverter device 10. The waveform indicated by Ga is the waveform of the inverter drive signal applied to the gate Ga of the switching element, and the waveform indicated by Gb is the waveform of the inverter drive signal applied to the gate Gb of the switching element. The waveform of v _{inv is} the waveform of the inverter output voltage corresponding to the circuit diagram of FIG. 1, and the waveform of i _{inv is} the waveform of the inverter output current corresponding to the circuit diagram of FIG. The waveform of i _{dc is} the waveform of the inverter input side current corresponding to the circuit diagram of FIG.

Next, the operation of each component will be described. The output current i _inv of the inverter circuit is detected by a sensor of the current detection unit 18. FIG. 4 shows a conceptual diagram of time difference detection in the present embodiment. The detected current has a sinusoidal waveform as shown in FIG. The current detector 18 generates a current binarized signal that is binarized in response to a change from positive to negative and from negative to positive of the sinusoidal waveform. As is clear from FIG. 4, the zero cross point of the output current i _inv of the inverter circuit coincides with the rising point b and the falling point of the current binarized signal. This current binarized signal is given to the time difference detector 13. The time difference detector 13 detects the time difference between the rising zero-cross point a of the inverter output voltage (voltage applied to the load) v _{inv and} the rising point b of the current binarized signal. A detection method and a specific time difference detection method of the inverter output voltage _vinv in this embodiment will be described later.

ここで、ｑは共振の鋭さ（ｑｕａｌｉｔｙ ｆａｃｔｏｒ）を示しており、このｑは、共振回路の定数で決定される、その性質を表すパラメータである。上式は、直列共振回路においても、また並列共振回路においても、成立する。図５に、インバータ回路の発振周波数ｆｓと、共振周波数ｆｒと、位相角φとの関係を示す。図５からも明らかなように、インバータ回路の出力電流と出力電圧の位相差（位相角）がゼロに近づくように制御すれば、発振周波数を共振周波数に近づけることできる。 In the induction heating apparatus, in order to increase the heating efficiency, it is necessary to bring the oscillation frequency of the inverter circuit close to the resonance frequency of the resonance circuit as a load. In this case, since the resonance frequency is determined from the inductance Ls of the heating coil, the capacitance Cs of the resonance capacitor, and the resistance Rs of the object to be heated, the resonance frequency is tracked as the values of these parameters vary. Need to be controlled. In order to track and control the resonance frequency, the characteristics of the resonance circuit are used. If the oscillation frequency of the inverter circuit is fs, the resonance frequency is fr, and the phase angle (phase difference between the output voltage and output current of the inverter circuit) is φ, the phase angle φ can be expressed as follows.

Here, q represents a resonance factor (quality factor), and q is a parameter representing the property, which is determined by a constant of the resonance circuit. The above equation holds true for both series resonant circuits and parallel resonant circuits. FIG. 5 shows the relationship between the oscillation frequency fs of the inverter circuit, the resonance frequency fr, and the phase angle φ. As is apparent from FIG. 5, the oscillation frequency can be brought close to the resonance frequency by controlling the phase difference (phase angle) between the output current and the output voltage of the inverter circuit to approach zero.

FIG. 6 schematically shows a time chart of output waveforms of the inverter output voltage v _inv and the inverter output current i _inv in the present embodiment. When the phase angle φ is obtained from the phase difference, it is the ratio of t _{fbk to} t _{sw in} the figure. Thus, the phase angle in Figure 5, can be calculated as φ = 2πt _fbk / t _sw.

Here, the phase angle conversion unit 14 calculates the phase time value of the phase difference between the inverter output voltage v _inv and the inverter output current i _inv detected by the time difference detection unit 13 by the reciprocal calculation unit 40 and the multiplication unit 41. Convert to The reciprocal calculation unit 40 obtains a cycle value from the cycle indication value output via the oscillation cycle calculation unit 15, performs a reciprocal calculation on this value, and outputs a reciprocal of the cycle. The multiplier 41 multiplies the reciprocal of this period by the time difference output from the time difference detector 13 and multiplies it by 2π to derive a phase angle value, and this phase angle value is derived from the oscillation period calculator 15. Output to.

  The oscillation period calculator 15 calculates and obtains the difference between the phase angle command value and the phase angle value output from the phase angle converter 14. Here, the phase angle command value is not zero and is preferably about 10 to 20 degrees. When the phase difference is negative, that is, when the oscillation frequency of the inverter circuit is lower than the resonance frequency, the phase difference of the series resonance circuit becomes negative, and the resonance circuit becomes a capacitive load. Therefore, an inrush current exceeding the rated value flows through the switching element, and the element may be damaged.

  As described above, in the present embodiment, the phase time difference between the inverter output voltage and the inverter output current is converted into the phase angle, and the phase angle value and the preset phase angle command value are calculated. Are comparing. When the time difference is directly used and compared with the target time difference, it is necessary to adjust the preset target time difference every time the frequency changes. However, in the present invention, since the time difference is converted into the phase angle, it is not necessary to adjust the value of the preset phase angle command value for each frequency, and it is possible to deal with a wideband frequency. .

  In this embodiment, an integral gain is given as a value to be multiplied by the acquired difference. The integral gain is desirably a value obtained by multiplying a reciprocal of the q value (resonance sharpness) of the load by a period value of the resonance frequency given in advance and π in order to appropriately stabilize the feedback control. The integrator 30 performs an integration operation using the difference multiplied by the integration gain. In addition, the cycle indication value is calculated using the difference information after the integration calculation processing and the initial cycle value given in advance. As the initial period value, for example, the period of the maximum frequency may be used in the band of the oscillation frequency assumed as the control target. The cycle indication value is a value that determines the cycle of the oscillation frequency of the inverter circuit so as to eliminate the difference between the phase angle command value and the calculated phase angle value. The cycle instruction value is given to the inverter drive signal generator 16. Further, as described above, the cycle instruction value is also given to the reciprocal calculation unit 40.

The counter 20 provided in the inverter drive signal generation unit 16 counts a clock signal having a predetermined frequency supplied from the clock signal oscillation unit 21. Each time the counter 20 counts the clock signal up to a numerical value (target count number) indicated by the cycle instruction value, the count number of the counter is reset. These operations are shown as timer operations in FIG. This conceptually shows how the count number increases every clock. Here, as schematically shown in FIG. 4, in the voltage type inverter of the present embodiment, when the count reaches the target count number and the counter is reset, the inverter output voltage _vinv rises at the time at the zero cross point a. Are configured to match. Therefore, in the present embodiment, the time difference detection unit 13 obtains the inverter output voltage v _inv and the inverter output current i by obtaining the time point of the rising point b of the given current binarization signal from the count number of the counter. A phase difference N _{fbk in} phase with _inv is detected.

  In order to clearly show the difference between the digital processing in this embodiment shown in FIG. 4 and the conventional PLL that performs analog processing, FIG. 11 shows analog processing by the conventional PLL. Since FIG. 11 is shown as a comparison with the digital processing shown in FIG. 4, the frequency upper and lower limit monitoring unit is not shown.

The inverter drive signal generation unit 16 can obtain the period by obtaining the time until the counter counts the clock signal having a predetermined frequency to the target value (period instruction value N _sw ). Based on the count number indicating the length of the period, the 50% duty ratio generation unit 22 generates a signal with a duty ratio of 50% so that the period of the oscillation frequency of the inverter circuit becomes the period indicated by the period instruction value. Generated. As shown in FIG. 2, a logically inverted signal of this signal is also generated. Then, the duty ratio is adjusted by the non-overlapping signal generation unit 50 so that the non-overlapping time of the two signals is provided. In the voltage type inverter, a non-overlap time is provided in order to prevent a short circuit due to the switching element Ga and the switching element Gb being simultaneously turned on. Further, the two signals are adjusted so that the time of the zero cross point when the inverter output voltage _vinv changes from negative to positive coincides with the time when the count reaches the target count and the counter is reset. .

  The adjusted signals are given to the inverter circuit 12 through the insulation / amplification unit 27 as the inverter drive signal A and the inverter drive signal B. The insulation / amplification unit 27 serves to electrically insulate between the inverter drive signal generation unit 16 and the inverter circuit 12 and to amplify current output from the inverter drive signal generation unit 16. When the switching elements Ga and Gb are turned on / off by the adjusted inverter drive signal A and inverter drive signal B, the cycle of the oscillation frequency of the inverter circuit becomes the cycle indicated by the cycle indication value. Here, when an abnormality in the input-side current is detected by the input-side current monitoring unit 17, an abnormality signal is given to the abnormal-time cutoff unit 51, and the abnormal-time cutoff unit 51 stops the inverter circuit. In the present embodiment, the input side current monitoring unit 17 monitors the instantaneous value of the input side current. In this embodiment of the voltage type inverter, the inverter circuit is stopped by turning off all the switching elements.

  The input side current monitoring unit 17 compares the preset comparison value with the current value detected by the input side current detection unit 24 by the comparator 25, and the detected value is a value outside the range determined by the comparison value. If so, an abnormal signal is output to the abnormal-time cutoff unit 51. The input-side current monitoring unit 17 and the abnormal interruption unit 51 prevent a switching element from being destroyed by a current exceeding the rated value flowing through the switching element.

  Further, the inverter device 10 is equipped with inverter circuit protection means. The phase angle value output from the phase angle converter 14 to the oscillation period calculator 15 is monitored by the phase monitor 60. The phase monitoring unit 60 compares the phase angle calculated by the phase angle conversion unit 14 with a preset monitoring phase angle value, and the calculated phase angle value is out of the allowable range as the monitoring phase angle value. When the value is, the phase angle abnormality detection signal is output to the abnormality cutoff unit 51 of the inverter drive signal generation unit 16. The abnormal-time cutoff unit 51 stops the inverter circuit immediately upon receiving the phase angle abnormality detection signal.

  As described above, when the oscillation frequency of the inverter circuit is lower than the resonance frequency, a current higher than the rated value of the switching element flows and the switching element may be destroyed. In the induction heating device, fusing due to insufficient cooling of the coil, breakage due to electromagnetic force, coil contact of the object to be heated, and the like occur. In such a case, the oscillation frequency> resonance frequency cannot be maintained only by the above oscillation frequency control. Sometimes. In addition, there may be a case where the input-side current monitoring unit 17 destroys the element without stopping the inverter circuit in time. Even in such a case, the phase monitoring unit 60 can protect the inverter circuit.

  Further, since the phase monitoring unit 60 monitors the phase angle value converted by the phase angle conversion unit 14 without using a low-pass filter as in the conventional frequency upper and lower limit monitoring, the phase monitoring unit 60 detects an abnormality earlier than in the past. Can be detected. For reference, conventional frequency upper and lower limit monitoring is schematically shown in a block diagram in FIG. In FIG. 10, a phase comparison unit 213, a filter unit 215, and a frequency variable circuit 216 realize a PLL (Place Locked Loop). The filter unit 215 is configured by a low-pass filter generally used in a PLL, and the frequency variable circuit 216 is configured by a VCO (Voltage Controlled Oscillator). As shown in FIG. 10, in the prior art, the frequency upper and lower limit monitoring unit 261 monitors the signal output from the low-pass filter and input to the VCO. Therefore, in the conventional method, it takes about 1.5 to 3 times the inverter oscillation period to detect the abnormality, and this time depends on the constant of the filter. However, in this embodiment, the oscillation cycle of the inverter is the maximum value of the delay time, and an abnormality can be detected earlier than in the conventional method, so that the inverter circuit can be protected more firmly.

  Further, the frequency upper / lower limit monitoring unit 61 monitors the cycle instruction value given from the oscillation cycle calculation unit 15 to the inverter drive signal generation unit 16. In the present embodiment, the cycle instruction value monitoring unit is realized as the frequency upper and lower limit monitoring unit 61. When the cycle instruction value is outside the range permitted as the monitoring cycle instruction value by comparing the cycle instruction value with a preset monitoring cycle instruction value, the inverter instruction signal generator generates a cycle instruction value abnormality detection signal. 16 is output to the abnormal-time cutoff unit 51. The abnormality cutoff unit 51 stops the inverter circuit immediately upon receiving the periodic instruction value abnormality detection signal. The frequency upper / lower limit monitoring unit 61 is used to further strengthen the protection of the inverter circuit.

  The present invention is implemented as described above as an example, and the oscillation frequency of the inverter circuit can be controlled by digital control. Compared to conventional control using a PLL that performs analog processing, the digital circuit is more resistant to aging and deterioration, and the control value and control operation can be easily switched.

  Next, a second embodiment of the present invention will be described. 7 and 8 show an electrical configuration of the inverter device 100 according to the second embodiment of the present invention. FIG. 8 shows details of the inverter drive signal generator 116 in FIG. The inverter device 100 shown in FIG. 7 is configured as a current-type inverter device and is used as an induction heating device. The apparatus 100 includes a resonant load (a load constituting a resonant circuit) 111 and an inverter circuit 112. The inverter device 100 includes a time difference detection unit 113, a phase angle conversion unit 114, an oscillation cycle calculation unit 115, and an inverter drive signal generation unit 116. In addition, an input side voltage monitoring unit 117 and an insulation / amplification unit 127 are provided.

  In the case of the current type inverter device, the resonance circuit of the resonance load 111 is a parallel resonance circuit, and in this embodiment, includes a heating coil Ls and a resonance capacitor Cs. The resistance of the object to be heated heated by the inverter device 100 is indicated by Rs. The inverter circuit 12 includes a bridge circuit including two transistors whose gates are indicated by Ga (here, insulated gate bipolar transistors) and two transistors whose gates are indicated by Gb. A diode is connected to each transistor in series. Further, the inverter circuit 112 includes a DC power supply 126. In addition, the inductance by wiring is shown as Lc.

The inverter drive signal generation unit 116 includes a counter 120, a clock signal oscillation unit 121, a 50 percent duty ratio generation unit 122, an overlap signal generation unit 150, and an abnormal time cutoff unit 151. Further, in this embodiment, the oscillation period calculation unit 115 includes an integrator 130 that performs an integration calculation for stabilizing the feedback control. The phase angle conversion unit 114 includes an inverse operation unit 140 and a multiplication unit 141. Moreover, in this embodiment which implement | achieves a current type inverter apparatus, the voltage detection part 118 is provided, and the voltage detection part 118 is provided with the sensor which is not shown in figure which detects the output voltage _vinv of an inverter circuit.

Moreover, each signal waveform in the inverter apparatus 100 is typically shown in FIG. The waveform of Ga is the waveform of the inverter drive signal given to the switching element Ga in FIG. 7, and the waveform of Gb is the waveform of the inverter drive signal given to the switching element Gb in FIG. The waveform of i _{inv is} the waveform of the inverter output current (current flowing through the load) corresponding to the circuit diagram of FIG. 7, and the waveform of v _inv is the inverter output voltage (applied to the load) corresponding to the circuit diagram of FIG. Voltage). v _dc is the waveform of the voltage on the input side corresponding to the circuit diagram of FIG.

Next, the operation of each component will be described. The output voltage v _inv of the inverter circuit is detected by a sensor of the voltage detection unit 118. The voltage detection unit generates a binarized voltage signal from the detected voltage, which is binarized corresponding to the positive and negative of the waveform, as in the first embodiment. This voltage binarized signal is given to the time difference detector 113. The time difference detector 113 detects the time difference between the rising point of the inverter output current (current flowing through the load) i _{inv and} the rising point of the voltage binarized signal.

The voltage type inverter has a load connected to a voltage source and a current flows. Therefore, in the first embodiment, the time difference between the inverter output voltage v _inv and the inverter output current i _inv is based on the voltage. Has been detected. On the other hand, in the current type inverter, a load is connected to a current source to generate a voltage. Therefore, in this embodiment, the time difference between the inverter output voltage v _inv and the inverter output current i _inv is the current It is detected on the basis of.

Similarly to the first embodiment, the phase angle conversion unit 114 converts the phase time difference between the inverter output voltage v _inv and the inverter output current i _inv detected by the time difference detection unit 113 into an inverse number calculation unit 140 and a multiplication unit 141. To convert to a phase angle value. The reciprocal calculation unit 140 acquires a cycle value from the cycle indication value output through the oscillation cycle calculation unit 115, performs a reciprocal calculation on this value, and outputs a reciprocal of the cycle. The multiplier 141 multiplies the reciprocal of this period by the time difference output from the time difference detector 113 and multiplies it by 2π to derive a phase angle value, which is then sent to the oscillation period calculator 115. Output.

  The oscillation period calculation unit 115 calculates and obtains the difference between the phase angle command value and the phase angle value output from the phase angle conversion unit 114. Here, the phase angle command value is not zero and is preferably about 10 to 20 degrees. When the phase difference is negative, that is, when the oscillation frequency of the inverter circuit is lower than the resonance frequency, the parallel resonance circuit becomes an inductive load. If the current is switched in such an inductive state, a surge voltage may be generated and the switching element may be destroyed. Therefore, it is desirable to set a positive phase angle command value that is not zero. In the present embodiment, an integral gain is given to the integrator 130 as a value to be multiplied by the acquired difference. As in the first embodiment, the integral gain is desirably a value obtained by multiplying the inverse of the load q value (resonance sharpness) by a period value of resonance frequency given in advance and π. The integrator 130 performs an integration operation using the difference multiplied by the integration gain. In addition, the cycle indication value is calculated using the difference information after the integration calculation processing and the initial cycle value given in advance. As the initial period value, for example, the period of the maximum frequency may be used in the band of the oscillation frequency assumed as the control target. As described above, the oscillation period calculation unit 115 calculates the period instruction value as in the first embodiment. The cycle instruction value is given to the inverter drive signal generation unit 116. The cycle instruction value is also given to the reciprocal calculation unit 140.

A counter 120 provided in the inverter drive signal generation unit 116 counts a clock signal having a predetermined frequency supplied from the clock signal oscillation unit 121. Each time the counter 120 counts the clock signal up to a numerical value (target count number) indicated by the cycle instruction value, the count number of the counter is reset. The current type inverter of the present embodiment is configured such that the time at the rising zero cross point of the inverter output current i _inv coincides with the time when the count reaches the target count and the counter is reset. Therefore, in the present embodiment, the time difference detection unit 113 obtains the inverter output voltage v _inv and the inverter output current i _inv by acquiring the time of the rising point of the given voltage binarized signal from the count number of the counter. The time difference of the phase with respect to is detected.

The inverter drive signal generation unit 116 can obtain the period by obtaining the time until the counter 120 counts the clock signal having a predetermined frequency to the target count. Based on the count number indicating the length of the period, the 50% duty ratio generation unit 122 generates a signal with a duty ratio of 50% so that the period of the oscillation frequency of the inverter circuit becomes the period indicated by the period instruction value. And a signal obtained by logically inverting this signal is also generated. In the present embodiment, which is a current type inverter, the duty ratio is adjusted by the overlap signal generation unit 150 so that an overlap time is provided for these two signals. The overlap time is determined by the current and the inductance Lc. Furthermore, the two signals are adjusted so that the time of the zero cross point when the inverter output current i _inv changes from negative to positive coincides with the time when the count reaches the target count and the counter is reset. .

  The adjusted signals are given to the inverter circuit as the inverter drive signal A and the inverter drive signal B through the insulation / amplification unit 127 as in the first embodiment. Here, the insulation / amplification unit 127 plays the same role as the insulation / amplification unit in the first embodiment. When the switching elements Ga and Gb are turned on / off by the adjusted inverter drive signal A and inverter drive signal B, the cycle of the oscillation frequency of the inverter circuit becomes the cycle indicated by the cycle indication value. Here, when an abnormality of the input side voltage is detected by the input side voltage monitoring unit 117, an abnormal signal is given to the abnormal-time cutoff unit 151, and the abnormal-time cutoff unit 151 stops the inverter circuit. In this embodiment of the current type inverter, the inverter circuit is stopped by turning on all the switching elements.

  In the present embodiment, the input-side voltage monitoring unit 117 monitors the instantaneous value of the input-side voltage, and the input-side voltage detection unit 124 extracts the voltage with an insulation amplifier. The input side voltage monitoring unit 117 compares the preset comparison value with the voltage detected by the input side voltage detection unit 124 by the comparator 125, and the detected value is a value outside the range defined by the comparison value. If there is, an abnormal signal is output to the abnormal interruption unit 151. The input side voltage monitoring unit 117 and the abnormal interruption unit 151 prevent destruction of the switching element due to generation of a surge voltage or the like.

  Further, the inverter device 100 is equipped with inverter circuit protection means. The phase angle value output from the phase angle conversion unit 114 to the oscillation period calculation unit 115 is monitored by the phase monitoring unit 160. The phase monitoring unit 160 compares the phase angle calculated by the phase angle conversion unit 114 with a preset monitoring phase angle value, and the calculated phase angle value is out of the allowable range as the monitoring phase angle value. When the value is, the phase angle abnormality detection signal is output to the abnormality cutoff unit 151 of the inverter drive signal generation unit 116. The abnormal-time cutoff unit 151 stops the inverter circuit immediately upon receiving the phase angle abnormality detection signal.

  As described above, when the oscillation frequency of the inverter circuit is lower than the resonance frequency, a voltage higher than the rated value of the switching element may be applied to destroy the switching element. As described in the first embodiment, in the induction heating apparatus, fusing due to insufficient cooling of the coil, breakage due to electromagnetic force, coil contact of the object to be heated, etc. occur. In such a case, only the above-described oscillation frequency control is performed. Then, the oscillation frequency> resonance frequency may not be maintained. In addition, there may be a case where the input side voltage monitoring unit 117 destroys the element without stopping the inverter circuit in time. Even in such a case, the phase monitoring unit 160 can protect the inverter circuit.

  Further, since the phase monitoring unit 160 monitors the phase angle value converted by the phase angle conversion unit 114 without using a low-pass filter as in the conventional frequency upper and lower limit monitoring, the phase monitoring unit 160 in the first embodiment. As stated, abnormalities can be detected earlier than before. Therefore, it is possible to protect the inverter circuit more firmly.

  Further, the frequency upper / lower limit monitoring unit 161 monitors the cycle instruction value given from the oscillation cycle calculation unit 115 to the inverter drive signal generation unit 116. In the present embodiment, the cycle instruction value monitoring unit is realized as the frequency upper / lower limit monitoring unit 161. When the cycle instruction value is outside the range permitted as the monitoring cycle instruction value by comparing the cycle instruction value with a preset monitoring cycle instruction value, the inverter instruction signal generator generates a cycle instruction value abnormality detection signal. 116 is output to the abnormal-time cutoff unit 151. The abnormal-time cutoff unit 151 stops the inverter circuit immediately upon receiving the periodic instruction value abnormality detection signal. The frequency upper / lower limit monitoring unit 161 is used to further strengthen protection of the inverter circuit.

[Other Embodiments]
The inverter device and the inverter control method according to the present invention are not limited to the above-described embodiments. For example, in another embodiment, a timer of TMS320F2812 manufactured by Texas Instruments may be used for the inverter drive signal generation unit. This timer has various functions. When the cycle indication value N _sw is given to the timer, the timer generates a cycle of (N _sw +1) × P _clk (a clock signal having a predetermined frequency), which is sent to the comparator. When N _sw / 2 is given, a signal with a duty ratio of 50% is generated. Since a non-overlap period can be given, an inverter drive signal can be directly generated. The timer can also be used in the time difference detector, the phase angle converter, and the oscillation period calculator.

  In the above embodiment, the inverter circuit includes a bridge circuit using four switching elements. However, the configuration of the inverter circuit is not limited to the above configuration, and the number of switching elements is not limited to the above embodiment. In addition, since 2π is a fixed value in the calculation in the phase angle conversion unit, the value of 2π may or may not be used. The input side voltage monitoring unit is not limited to the above embodiment, and can be realized by using various means such as a circuit using a breakover diode and a transformer.

  The inverter device and the inverter control method according to the present invention can be applied not only to an induction heating device but also to a device using an inverter circuit having a resonance circuit as a load, such as an ozonizer or a corona discharge device.

It is a schematic diagram which shows the whole electric system of the 1st Embodiment of this invention. It is a schematic diagram which shows the whole electric system of the 1st Embodiment of this invention. It is a schematic diagram of each signal waveform corresponding to the circuit diagram of FIG. It is a conceptual diagram of the time difference detection in 1st Embodiment. It is a characteristic view which shows the characteristic of a resonance circuit. The time chart of output waveforms of the inverter output voltage v _inv and inverter output current i _inv in the first embodiment is a schematic diagram illustrating schematically. It is a schematic diagram which shows the whole electric system of the 2nd Embodiment of this invention. It is a schematic diagram which shows the whole electric system of the 2nd Embodiment of this invention. It is a schematic diagram of each signal waveform corresponding to the circuit diagram of FIG. It is a schematic diagram which shows the conventional inverter circuit protection means. It is a schematic diagram which shows the analog processing by the conventional PLL.

Explanation of symbols

10 Inverter device (voltage type)
DESCRIPTION OF SYMBOLS 11 Resonant load 12 Inverter circuit 13 Time difference detection part 14 Phase angle conversion part 15 Oscillation period calculation part 16 Inverter drive signal generation part 17 Input side current monitoring part 18 Current detection part 20 Counter 21 Clock signal oscillation part 22 50 percent duty ratio generation part 30 integrator 40 reciprocal calculation unit 41 multiplication unit 50 non-overlapping signal generation unit 51 abnormal time cut-off unit 60 phase monitoring unit 61 frequency upper and lower limit monitoring unit 100 inverter device (current type)
111 Resonant load 112 Inverter circuit 113 Time difference detector 114 Phase angle converter 115 Oscillation period calculator 116 Inverter drive signal generator 117 Input voltage monitor 118 Voltage detector 120 Counter 121 Clock signal oscillator 122 50 percent duty ratio generator 130 Integrator 140 Reciprocal Calculation Unit 141 Multiplication Unit 150 Overlap Signal Generation Unit 151 Abnormality Blocking Unit 160 Phase Monitoring Unit 161 Frequency Upper / Lower Limit Monitoring Unit

Claims (16)

A load constituting a resonance circuit;
An inverter circuit comprising a switching element and supplying high frequency power to the load;
A time difference detecting means for detecting a value representing a time difference in phase between a voltage applied to the load and a current flowing in the load;
Phase angle conversion means for performing an operation of converting a value representing the time difference into a phase angle value;
A difference between the phase angle value and a preset phase angle command value is acquired, a period instruction value that determines a period of the oscillation frequency of the inverter circuit is calculated using the difference, and the period instruction value is output. Oscillation period calculation means;
Inverter drive signal generation that acquires the cycle instruction value, generates an inverter drive signal for controlling on / off of the switching element of the inverter circuit based on the cycle instruction value, and outputs the drive signal to the inverter circuit Means,
When the phase angle value converted by the phase angle conversion means is compared with a preset monitoring phase angle value, and the phase angle value is outside the range allowed as the monitoring phase angle value, the phase Phase angle monitoring means for outputting an angle abnormality detection signal to the inverter drive signal generation means, and
The inverter device that stops the inverter circuit when the inverter drive signal generation unit acquires a phase angle abnormality detection signal from the phase angle monitoring unit.   The phase angle conversion means, based on the period indication value, an inverse number calculation means for calculating an inverse number of the period; a multiplication means for multiplying a value representing the time difference detected by the time difference detection means by the inverse number of the period; The inverter device according to claim 1, comprising: Comparing the cycle indication value calculated by the oscillation cycle calculation means with a preset monitoring cycle indication value, when the cycle indication value is outside the range allowed as the monitoring cycle indication value, A cycle command value monitoring means for outputting a cycle command value abnormality detection signal to the inverter drive signal generating unit;
3. The inverter device according to claim 1, wherein the inverter drive signal generation unit is configured to stop the inverter circuit when acquiring a cycle instruction value abnormality detection signal from the cycle instruction value monitoring unit. The inverter drive signal generating means includes counting means for counting clock signals having a predetermined frequency,
The counting means, each for counting said clock signal to the target count number indicated by the period indicated value, resets the count number,
Based on the time obtained by counting up the number of the target count, generating the inverter drive signals, inverter device according to any one of claims 1-3. By detecting the current flowing before Symbol load comprises a current detecting means for providing a binarized current binary signal depending on positive and negative waveform of the current to said time difference detecting means, the inverter device according to claim 4 . Comprising a voltage detecting means for providing a voltage binary signal by binarizing according detects the voltage applied to the prior SL load the sign of the waveform of the voltage to the time difference detecting means, the inverter according to claim 4 apparatus. The time difference detection means detects a value representing the time difference from a difference between a time when the count reaches the target count number and is reset and a time point when the current binarized signal is acquired from the count number. The inverter device according to claim 5. The time difference detection means detects a value representing the time difference from a difference between a time when the count reaches the target count number and is reset, and a time point when the voltage binarized signal is acquired from the count number. The inverter device according to claim 6. An inverter control method for controlling the oscillation frequency of the inverter circuit,
A time difference detection step for detecting a value representing a time difference in phase between a voltage applied to a load and a current flowing in the load;
A phase angle conversion step of performing an operation of converting a value representing the time difference into a phase angle value;
An oscillation period calculation that obtains a difference between the phase angle value and a preset phase angle command value, calculates a period instruction value that determines the period of the oscillation frequency using the difference, and outputs the period instruction value Steps,
Inverter drive signal generation that acquires the cycle instruction value, generates an inverter drive signal for controlling on / off of the switching element of the inverter circuit based on the cycle instruction value, and outputs the drive signal to the inverter circuit Steps,
When the phase angle value converted in the phase angle conversion step is compared with a preset monitoring phase angle value, and the phase angle value is outside the range allowed as the monitoring phase angle value, the phase A phase angle monitoring step for outputting an angle abnormality detection signal;
An inverter control method comprising: an inverter stop step of acquiring the phase angle abnormality detection signal and stopping the inverter circuit. The phase angle conversion step includes a reciprocal calculation step for calculating a reciprocal of the cycle based on the cycle indication value, and a multiplication step of multiplying a value representing the time difference detected by the time difference detection step by the reciprocal of the cycle. The inverter control method according to claim 9 , comprising: Comparing the cycle indication value calculated in the oscillation cycle calculation step with a preset monitoring cycle indication value, when the cycle indication value is outside the range allowed as the monitoring cycle indication value, A cycle command value monitoring step for outputting a cycle command value abnormality detection signal is provided,
The inverter control method according to claim 9 or 10 , wherein the inverter stop step includes acquiring the cycle instruction value abnormality detection signal and stopping the inverter circuit. The inverter drive signal generating step counts the counting means a clock signal of a predetermined frequency, said counting means, each for counting said clock signal to the target count number indicated by the period indicated value, resets the count , based on the time obtained by counting up the number of the target count, a step of generating the inverter drive signals, inverter control method according to any one of claims 9-11. By detecting the current flowing before Symbol load includes a current detection step of generating a binarized current binary signal depending on positive and negative waveform of the current,
The inverter control method according to claim 12 , wherein in the time difference detection step, the current binarized signal is used to detect a value representing the time difference. By detecting a voltage applied to the prior SL load includes a voltage detection step of generating a voltage binary signal binarized according to the positive or negative of the waveform of the voltage,
The inverter control method according to claim 12 , wherein, in the time difference detection step, the voltage binarized signal is used to detect a value representing the time difference. In the time difference detection step, a value representing the time difference is detected from a difference between a time when the count reaches the target count number and is reset and a time point when the current binarized signal is obtained from the count number. The inverter control method according to claim 13. In the time difference detection step, a value representing the time difference is detected from a difference between a time when the count reaches the target count number and is reset and a time point of rising of the voltage binarization signal acquired from the count number. The inverter control method according to claim 14.

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