JP7306315B2 - AC chopper circuit control device and AC chopper circuit control method - Google Patents

Description

The present invention relates to a technique for suppressing current distortion caused by current detection offset in an AC chopper circuit in which one leg of a single-phase inverter is replaced with a diode.

FIG. 1 shows an AC chopper circuit disclosed in Patent Document 1. As shown in FIG. The AC chopper circuit can flow active power in only one direction from the AC power supply 11 side to the DC voltage Vdc.

FIG. 2 shows the current control block of the AC chopper circuit. In this specification, the input current amplitude command value Ichp*>0 for the input current Ichp of the AC chopper circuit because the direction of flow from the DC voltage Vdc to the AC power supply 11 side is negative.

FIG. 3 shows an output voltage command value calculation block and a PWM modulation block. FIG. 3(a) is a block assuming synchronous rectification, and FIG. 3(b) is a block assuming that synchronous rectification is not applied. In either case, when the correction coefficient α=1, the deviation increases when the input current amplitude command value Ichp* is set near zero. This problem is solved by calculating the correction coefficient α and correcting the output voltage command value, and keeping the deviation of the output current small in the discontinuous mode (the current rises from zero in the switching cycle and ends at zero during the fall). can be done.

JP-A-10-337032

When an offset is superimposed on the input current detection value obtained by detecting the input current Ichp of the AC chopper circuit (hereinafter, both the input current and the input current detection value of the AC chopper circuit are denoted by Ichp), the input of the AC chopper circuit Distortion of the current Ichp may be exacerbated. FIG. 8 shows the waveform at that time.

The topmost waveform is the input current Ichp of the AC chopper circuit. When the input current Ichp of the AC chopper circuit is positive, the lower peak of the current ripple is always zero, indicating operation in discontinuous mode. However, when the current ripple is negative, there is a period in which the upper side of the current ripple is away from zero, temporarily leaving the discontinuous mode. The current waveform is vertically asymmetrical.

It was confirmed that not only the DC component but also even-order harmonics were superimposed on the current at this time. The DC component of the input current Ichp of the AC chopper circuit causes biased magnetism in the transformer connected to the system, which tends to cause magnetic flux saturation and an inrush current. Harmonics of the input current Ichp of the AC chopper circuit may cause abnormal noise, heat generation, and burnout of filter reactors and capacitors, and malfunction of devices connected to the surroundings, and must be reduced as much as possible.

As a countermeasure, it is necessary to remove the offset from the input current detection value Ichp. However, in principle, when a Hall element is used for current detection, an offset is likely to be superimposed, and even if the offset is removed at the time of shipment, the offset changes due to temperature and aging.

A method of detecting the asymmetry by checking the magnitude of the ripples superimposed on the positive side and the negative side of the input current detection value Ichp is also conceivable. However, it is necessary to accurately detect the ripple of the input current Ichp of the AC chopper circuit, and the frequency band and sampling frequency of the Hall element must be set sufficiently high. cost will increase. If the frequency band is high, malfunction due to noise is likely to become a problem, making noise countermeasures difficult.

If the current is detected by connecting a resistor to the main circuit side and measuring the voltage drop, no offset is superimposed on the input current detection value Ichp. However, it is not possible to eliminate the possibility that the loss will increase and that an offset will be superimposed on the printed circuit board such as the A/D converter and the operational amplifier.

As described above, in the AC chopper circuit, the problem is how to suppress the current distortion caused by the offset superimposed on the input current detection value.

The present invention has been devised in view of the conventional problems described above, and one aspect of the present invention comprises a capacitor, a set of semiconductor switching elements connected in series as an upper arm and a lower arm, and a set of semiconductor switching elements connected in series. are connected in parallel, and a single-phase AC power supply is connected between the connection point of the set of semiconductor switching elements and the connection point of the set of diodes, wherein , a current control block for controlling the input current detection value obtained by detecting the input current of the AC chopper circuit to be the input current amplitude command value; a PLL block for calculating a phase signal synchronized with the voltage of the single-phase AC power supply; and based on the phase signal, the output voltage command value, and the carrier signal. a PWM modulation block for generating a gate signal for the set of semiconductor switching elements; and an offset correction value based on even-order harmonics superimposed on the input current detection value; and an offset removal block that corrects the input current detection value by subtracting a correction value.

In one aspect, the offset removal block interrupts the adjustment of the offset correction value when the absolute value of the even-order harmonic is greater than a first threshold.

Also, as one aspect thereof, the offset removal block is characterized by limiting the offset correction value within a preset range.

Further, as one aspect thereof, the adjustment of the offset correction value is interrupted when the input current amplitude command value is larger than a second threshold value.

Further, as one aspect thereof, when the adjustment of the offset correction value is interrupted, the offset correction value calculated immediately before the interruption is used.

According to the present invention, in an AC chopper circuit, it is possible to suppress current distortion caused by an offset being superimposed on an input current detection value.

The block diagram which shows an example of an alternating current chopper circuit. The figure which shows the current control block of an alternating current chopper circuit. The figure which shows the output voltage command value calculation block and PWM modulation block of an alternating current chopper circuit. FIG. 4 is a diagram showing an offset removal block according to the first embodiment; FIG. FIG. 4 is a diagram showing waveforms when the offset of the input current detection value is removed; FIG. 12 is a diagram showing an offset removal block in the second embodiment; FIG. FIG. 10 is a diagram showing an offset removal block in Embodiment 3; FIG. 10 is a diagram showing a waveform when an offset is superimposed on the input current detection value;

Embodiments 1 to 3 of a control device for an AC chopper circuit according to the present invention will be described in detail below with reference to FIGS. 1 to 7. FIG.

[Embodiment 1]
First, the main circuit configuration of the representative AC chopper circuit of FIG. 1 will be described. In FIG. 1, one end of a single-phase AC power supply 11 is connected to a connection point of a pair of semiconductor switching elements Sa and Sb connected in series as upper and lower arms via reactors 12a and 12b that constitute an LC filter. It is The semiconductor switching elements Sa and Sb are composed of, for example, MOSFETs and IGBTs shown in the figure.

The other end of the AC power supply 11 is connected to a connection point of a pair of diodes 13a and 13b connected in series. 14 is a capacitor on the DC output side of the AC chopper circuit. The capacitor 14, a series circuit of diodes 13a and 13b, and a series circuit of semiconductor switching elements Sa and Sb (hereinafter also referred to as legs) are connected in parallel.

A capacitor 15 forming an LC filter is connected between the connection point of the reactors 12 a and 12 b and the other end of the AC power supply 11 . A potential transformer 16 is connected across the AC power supply 11, and a power supply voltage detection value V1 is obtained on the secondary side thereof.

Resistors 17 and 18 acting as a semiconductor switching element voltage detection circuit are connected in series between both ends (between drain and source) of the semiconductor switching element Sb of the lower arm. A voltage divided by these resistors 17 and 18 is output as a semiconductor switching element voltage detection value Vds.

In FIG. 1, Iout indicates the output current of the AC power supply 11, Ichp indicates the input current of the AC chopper circuit, and Vdc indicates the DC voltage across the capacitor 14, respectively.

In the above configuration, the semiconductor switching elements Sa and Sb are controlled to be turned on and off by the controller, so that the active power can flow only in one direction from the AC power supply 11 side to the DC voltage Vdc side.

FIG. 2 shows a current control block in the controller for the AC chopper circuit. In FIG. 2, an LPF (low-pass filter) 21 receives an input current detection value Ichp obtained by detecting the input current of the AC chopper circuit of FIG. Eliminate switching ripple, etc.

The multiplier 22 multiplies the set input current amplitude command value Ichp* by the cosine value cos θ corresponding to the phase signal θ synchronized with the voltage of the single-phase AC power supply 11, calculated by the PLL block 23, which will be described later. , to output an instantaneous input current amplitude command value Ichp*cos θ. However, the cosine value cos θ is obtained by referring to the cosine value table 24 prepared in advance.

A subtractor 25 subtracts the output of the LPF 21 from the input current amplitude command value Ichp*cos θ, which is the output of the multiplier 22 .

A P amplifier (current control amplifier) 26 receives the output of the subtractor 25, multiplies it by a gain, and outputs a proportional value. Note that the P amplifier 26 may also use a resonance amplifier that has an infinite gain with respect to the fundamental frequency.

The LPF 21, the multiplier 22, the subtractor 25, and the P amplifier 26 constitute a current control block that controls the input current detection value Ichp to become the input current amplitude command value Ichp*cos θ. The output V* of the current control block is obtained by.

A divider 27 obtains the reciprocal 1/Vdc from the DC voltage detection value Vdc which is the DC voltage detected across the capacitor 14 in FIG. A multiplier 28 multiplies the reciprocal 1/Vdc and the cosine value cos θ to obtain the reference sine wave cos θ/Vdc.

The adder 29 subtracts the output V* of the current control block, which is the output of the amplifier 26, from the reference sine wave cos θ/Vdc, which is the output of the multiplier . A buffer 30 temporarily stores the output of the adder 29 and outputs the output V*' of the current control block one calculation cycle before.

In the PLL block 23, the voltage of the single-phase AC power supply is adjusted based on either the power supply voltage detection value V1, the semiconductor switching element voltage detection value Vds, or the output V*' of the current control block one operation cycle before. output a phase signal θ synchronized with

In the PLL block 23, for example, when the device is stopped, the semiconductor switching element voltage detection value Vds is multiplied by 2. Multiply by a sine wave sin θ delayed by 90 degrees, extract the DC component with the LPF, apply the deviation between the phase command value and the output of the LPF to the PI amplifier to calculate the angular frequency ω, integrate the angular frequency ω, and obtain the phase signal θ demand.

Alternatively, the power supply voltage detection value V1 is multiplied by a sine wave sinθ delayed by 90 degrees with respect to the AC power supply voltage, the DC component is extracted by the LPF, and the deviation between the phase command value and the output of the LPF is applied to the PI amplifier and the angular frequency ω is calculated, and the phase signal θ is obtained by integrating the angular frequency ω.

The phase command value is normally zero. However, for example, a value obtained by multiplying the input current detection value Ichp by a sine wave sin θ may be used to extract a DC component with an LPF, and the output of the LPF may be amplified by a proportional integral operation in a PI amplifier to obtain a value. Alternatively, the phase command value for test operation may be stored, and the stored phase command value for test operation may be output during normal operation. Alternatively, the phase command value may be corrected by adding a value obtained by multiplying the input current amplitude command value Ichp* by the gain G (AC side inductance value).

FIG. 3(a) shows an output voltage command value calculation block and a PWM modulation block of the control device assuming synchronous rectification. The multiplier 31 in FIG. 3A doubles the current control block output V* output from the P amplifier 26 . A multiplier 32 doubles the reference sine wave cos θ/Vdc output from the multiplier 28 .

The adder 33 adds 2 to the output 2cos θ/Vdc of the multiplier 32 . A subtractor 34 subtracts 2 from the output 2cos θ/Vdc of the multiplier 32 .

A multiplier 35 multiplies the output of the adder 33 by a correction coefficient α for correcting the duty ratio. A multiplier 36 multiplies the output of the subtractor 34 by a correction coefficient α for correcting the duty ratio.

The correction coefficient α is a set fixed correction coefficient, or, for example, the absolute value of the instantaneous input current amplitude command value Ichp*cos θ is smaller than half the peak-to-peak value Irpl/2 of the ripple current, and , is a correction coefficient that is 0 to 1 when the input current amplitude command value Ichp* is equal to or less than the threshold, and is 1 otherwise. Note that the multipliers 35 and 36 are excluded when the correction coefficient α is not used.

Subtractor 37 subtracts 1 from the output of multiplier 35 or the output of adder 33 . Adder 38 adds 1 to the output of multiplier 36 or the output of subtractor 34 . Subtractor 37 and adder 38 output switching duty ratios (duty ratios calculated from reference sine wave cos θ/Vdc) of semiconductor switching elements Sa and Sb in FIG. 1, respectively.

A subtractor 39 subtracts the output of the multiplier 31 from the output of the subtractor 37 (superimposes the double component of the output V* of the current control block on the duty ratio) to obtain an output voltage command value α (2cos θ/Vdc+2 )-1-2V*.

A subtractor 40 subtracts the output of the multiplier 31 from the output of the adder 38 (superimposes the double component of the output V* of the current control block on the duty ratio) to obtain an output voltage command value α (2cos θ/Vdc -2) Output +1-2V*.

The switch 41 selects the output voltage command value α(2 cos θ/Vdc+2)−1−2V* output from the subtractor 39 if the cosine value cos θ is negative, and the output voltage output from the subtractor 40 if positive. Select the command value α(2cosθ/Vdc-2)+1-2V*.

The multipliers 31, 32, 35, 36, adders 33, 38, subtractors 34, 37, 39, 40 and switch 41 constitute an output voltage command value calculation block.

A carrier generator 42 outputs a carrier signal that varies between -1 and 1. A subtractor 43 subtracts the carrier signal from the output voltage command value selected by the switch 41 .

Comparator 44 determines whether the output of subtractor 43 is greater than zero. Dead time adding section 45 adds dead time to the output of comparator 44 . Gate signals for the semiconductor switching elements Sa and Sb shown in FIG.

The carrier generator 42, subtractor 43, comparator 44, and dead time adder 45 constitute a PWM modulation block.

In the control block of FIG. 3(a), it is assumed that synchronous rectification is applied. When the semiconductor switching elements Sa and Sb in FIG. 1 are MOSFETs, when the MOSFETs are turned on while the current is flowing through the antiparallel diodes, the current flows through the MOSFETs. At this time, the conduction loss can be reduced because the MOSFET itself has better characteristics than the MOSFET parasitic antiparallel diode. When the input current detection value Ichp>0, only the semiconductor switching element Sb of the lower arm should be switched. Performs synchronous rectification.

When the power supply voltage detection value V1≈0, if V1>0, then Ichp>0, and the diode 13b on the lower arm side becomes conductive in the diode series circuit. The ON time of the semiconductor switching element Sb is lengthened by setting the output voltage command value to around -1. Similarly, if V1<0, the output voltage command value is set to around 1 to lengthen the ON time of the semiconductor switching element Sa. This operation is performed by the output voltage command value calculation block of FIG. 3(a).

Then, in the PWM modulation block of FIG. 3(a), the gate signal obtained by comparing the output voltage command value with the carrier signal and adding dead time is input to the corresponding semiconductor switching elements Sa and Sb of FIG.

FIG. 3B shows an output voltage command value calculation block and a PWM modulation block of the control device assuming that synchronous rectification is not applied.

The absolute value calculator ABS obtains the absolute value of the reference sine wave cos θ/Vdc. A subtractor 46 subtracts from 1 the output of the absolute value calculator ABS. A multiplier 47 obtains the product of the output of the subtractor 46 and the correction coefficient α. Subtractor 48 subtracts the output of multiplier 47 from one.

The sign detector 49 outputs 1 if the reference sine wave cos θ/Vdc is plus, and outputs -1 if it is minus. When the reference sine wave cos θ/Vdc is 0, either 1 or −1 may be output. Multiplier 50 multiplies the output of sign detector 49 and the output of subtractor 48 . The multiplier 50 outputs the switching duty ratio of the semiconductor switching elements Sa and Sb (duty ratio calculated from the reference sine wave cos θ/Vdc). A subtractor 51 subtracts the current control block output V* from the output of the multiplier 50 (superimposes the current control block output V* on the duty ratio) and outputs an output voltage command value.

The absolute value calculator ABS, subtractors 46, 48, 51, multipliers 47, 50, and sign detector 49 constitute an output voltage command value calculation block.

A carrier generator 52 outputs a first carrier signal that varies between 0 and 1. FIG. A carrier generator 53 outputs a second carrier signal that varies between 0 and -1. A subtractor 54 obtains the difference between the output of the subtractor 51 and the first carrier signal. A subtractor 55 obtains the difference between the output of the subtractor 51 and the second carrier signal.

Comparator 56 outputs 1 if the output of subtractor 54 is positive (that is, if the output of subtractor 51 is greater than the first carrier signal), and if the output of subtractor 54 is negative (that is, subtract 0 is output if the output of unit 51 is less than or equal to the first carrier signal. Comparator 57 outputs 1 if the output of subtractor 55 is positive (that is, if the output of subtractor 51 is greater than the second carrier signal), and if the output of subtractor 55 is negative (that is, subtraction 0 is output if the output of the unit 51 is less than or equal to the second carrier signal.

The comparator 58 outputs 1 if the cosine value cos θ is positive. In FIG. 3(b), it is compared with a value slightly larger than 0 (0.001) for the purpose of adding dead time. The comparator 59 outputs 1 if the cosine value cos θ is negative. In FIG. 3(b), it is compared with a value slightly smaller than 0 (-0.001) for the purpose of adding dead time.

AND element 60 ANDs the outputs of comparators 56 and 58 . The output of the AND element 60 becomes 1 when the cosine value cos θ is positive and the output of the subtractor 51 is smaller than the first carrier signal. A gate signal output from the AND element 60 is input to the lower arm semiconductor switching element Sb.

AND element 61 obtains the logical product of the outputs of comparators 57 and 59 . The output of the AND element 61 becomes 1 when the cosine value cos θ is negative and the output of the subtractor 51 is greater than the second carrier signal. A gate signal output from the AND element 61 is input to the upper arm semiconductor switching element Sa.

The carrier generators 52, 53, subtractors 54, 55, comparators 56, 57, 58, 59 and AND elements 60, 61 constitute a PWM modulation block.

FIG. 4 shows an offset removal block in the first embodiment.

A subtractor 62 subtracts an offset correction value, which will be described later, from the input current detection value Ichp. The output of the subtractor 62 becomes the input current detection value Ichp' after offset removal, and is input to Ichp of the control block in FIG.

The phase signal .theta. is the value obtained from the PLL block 23 in FIG. Multiplier 63 doubles the phase signal θ obtained from PLL block 23 . A cosine unit 64 outputs a cosine wave cos2θ corresponding to the output of the multiplier 63 . A multiplier 65 obtains the product of the cosine wave cos2[theta] and the input current detection value Ichp' after offset removal.

A filter (eg, low-pass filter) 66 extracts the DC component from the product, which is the output of multiplier 65 . A PI amplifier 67 amplifies the output of the filter 66 . The output of the PI amplifier 67 becomes the offset correction value. A DC component is superimposed on the current distortion caused by the detection offset. Apart from this, even harmonics are also superimposed as a feature different from general current distortion. In the first embodiment, the second harmonic of the lowest order among the even harmonics is detected, and the offset correction value is adjusted so that this becomes zero. In addition, although the second harmonic among the even harmonics is detected in the first embodiment, other even harmonics may be applied.

By obtaining the product of the input current detection value Ichp and cos2θ and averaging one period of the fundamental wave, it is possible to extract the cos2θ component (second harmonic component) superimposed on the input current detection value Ichp. This is amplified by the PI amplifier 67 and subtracted from the input current detection value Ichp as an offset correction value to obtain the input current detection value Ichp' after offset removal. By using this as a signal obtained by removing the offset from the input current detection value Ichp for current control, a current waveform with a small DC component and even harmonics can be obtained.

FIG. 5 shows waveforms when control is performed using the input current detection value Ichp' after offset removal with respect to FIG. As in FIG. 8, the topmost waveform is the input current Ichp of the AC chopper circuit. It can be confirmed that the current waveform is vertically symmetrical, and that the DC component and distortion are reduced.

If an offset is superimposed on the input current detection value when the current is small in an AC chopper circuit, even-order harmonics are superimposed on the current in addition to the DC component, and the waveform may be distorted. According to the first embodiment, the distortion of the DC component and even-order harmonics can be removed by detecting the second-order component of the even-order harmonics and correcting the offset. It can be used even when a Hall element is used for current detection, where offset is likely to be superimposed. Since the offset can be removed during operation, there is no need to adjust the offset in advance, and there is no need to increase the sampling frequency, thereby reducing costs.

[Embodiment 2]
FIG. 6 shows an offset removal block in the second embodiment. In the second embodiment, the following limiter 68 and limiter 69 are added to the offset removal block of the first embodiment.

The limiting unit 68 is provided after the filter 66, and outputs the same value as the input when the absolute value of the input is less than or equal to the first threshold, and outputs zero when the absolute value of the input is greater than the first threshold. The limiter 69 is provided in the subsequent stage of the PI amplifier 67 and sets the upper and lower limits of the output value of the PI amplifier 67 . In the second embodiment, the output of the limiter 69 becomes the offset correction value.

Embodiment 1 removes the offset by focusing on the even-order harmonics of the inflow current. Even-order harmonics are rarely generated normally. However, when magnetic flux saturation occurs in the transformer and an inrush current flows, very large even-order harmonics may be superimposed. When this inrush current is input to the block in FIG. 4, the PI amplifier 67 amplifies the even-order harmonics contained in the inrush current, and a very large value is set as the offset correction value, which may interfere with the operation. There is

In the second embodiment, first, when the absolute value of the even-order harmonic is larger than the first threshold value, the limiting unit 68 determines that an inrush current has occurred, and inputs 0 to the PI amplifier 67 to Stop (interrupt) the operation. At this time, the PI amplifier 67 outputs the value of the integration buffer. Therefore, the input current detection value Ichp' after the offset is removed can be obtained using the offset correction value immediately before the output of the filter 66 becomes larger than the first threshold value. When the absolute value of the even-order harmonic becomes smaller than the first threshold value again, the PI amplifier 67 resumes its operation and adjusts the offset correction value, so it is possible to follow changes in temperature and aging. This allows the PI amplifier 67 to ignore the rush current. The first threshold is set to a value of about several percent of the rated current.

Next, the limiter 69 limits the offset correction value within a predetermined range. This fixed range is set by referring to the data sheet of the current detector, and is usually about 1% of the current detector's rating.

As described above, according to the second embodiment, it is possible to prevent the offset removal block from malfunctioning when even-order harmonics flow due to factors other than the offset, such as inrush current due to magnetic flux saturation of the transformer. Become.

In addition, it is possible to prevent a situation in which the offset correction value becomes an abnormal value and, conversely, the DC component and even-order harmonics superimposed on the current increase.

[Embodiment 3]
FIG. 7 shows an offset removal block in the third embodiment. The third embodiment adds a subtractor 70 and a switch 71 to the offset removing block of the second embodiment.

The subtractor 70 subtracts the input current amplitude command value Ichp* from the second threshold Ith. The switch 71 is provided after the filter 66 and selects and outputs one of the two inputs. One of the inputs is the output of filter 66 . Another of the inputs is a fixed value of zero. If the input current amplitude command value Ichp* is smaller than the second threshold value Ith, the switch 71 inputs the output of the filter 66 to the limiter 68 . If the input current amplitude command value Ichp* is greater than the second threshold value Ith, the switch 71 inputs the fixed value 0 to the limiter 68 .

When the input current amplitude command value Ichp* is sufficiently large, a current waveform with less distortion can be obtained by fixing the correction coefficient α to 1. Under this condition, the input current amplitude command value Ichp* becomes sufficiently larger than the current ripple, and the input current Ichp of the AC chopper circuit reliably exits the discontinuous mode on both the positive side and the negative side, and the input current Ichp of the AC chopper circuit The waveform becomes almost symmetrical and the superimposed even-order harmonics are also very small.

At this time, the current ripple near the sampling frequency, which is erroneously detected as the second harmonic, becomes larger than the second harmonic actually superimposed on the current due to the offset, and as a result, the PI amplifier 67 runs out of control, causing the offset. This may hinder the operation of adjusting the correction value.

In the third embodiment, it is detected that the input current amplitude command value Ichp* is sufficiently large, and zero is input to the PI amplifier 67 to stop (interrupt) the operation of the PI amplifier 67 . At this time, the PI amplifier 67 outputs the value of the integration buffer. Therefore, the input current detection value Ichp' after offset removal can be obtained using the offset correction value immediately before the input current amplitude command value Ichp* increases.

When the input current amplitude command value Ichp* becomes smaller again, the PI amplifier 67 resumes its operation and adjusts the offset correction value, so it is possible to follow changes in temperature and aging. The second threshold Ith to be compared with the input current amplitude command value Ichp* is determined in advance by simulation or the like. Then, a method of searching for an input current amplitude command value Ichp* that can reduce THD by enabling correction can be considered.

Alternatively, the second threshold Ith may be switched based on the result of estimating the value of the system inductance. The system inductance value is estimated by detecting, for example, the third harmonic superimposed on the waveform of the input current detection value Ichp. If the tertiary harmonic is large, the system inductance is small, and the secondary harmonic is likely to flow, so the second threshold Ith is increased. Conversely, if the tertiary harmonic is small, the second threshold Ith is also decreased. may As a result, even if the system is connected to a different system or if the system inductance changes due to load fluctuations during operation, it can be followed.

As described above, according to the third embodiment, it is possible to prevent malfunction under the condition that the current amplitude is sufficiently large and the second harmonic is hardly superimposed even if the offset is superimposed on the current detection signal.

In addition, it is possible to prevent a situation in which the offset correction value becomes an abnormal value and, conversely, the DC component and even-order harmonics superimposed on the current increase.

Although the present invention has been described in detail only with respect to the specific examples described above, it is obvious to those skilled in the art that various modifications and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are, of course, covered by the claims.

62, 70 Subtractor 63, 65 Multiplier 64 Cos unit 66 Filter 67 PI amplifier 68 Limiter 69 Limiter 71 Switch

Claims (6)

A capacitor, a set of semiconductor switching elements connected in series as an upper arm and a lower arm, and a set of diodes connected in series are connected in parallel. A control device for an AC chopper circuit in which a single-phase AC power supply is connected between a pair of diode connection points,
a current control block for controlling the input current detection value obtained by detecting the input current of the AC chopper circuit to be the input current amplitude command value;
an output voltage command value calculation block that calculates an output voltage command value by superimposing the output of the current control block on the duty ratio calculated from the reference sine wave;
a PLL block that calculates a phase signal synchronized with the voltage of the single-phase AC power supply;
a PWM modulation block that generates a gate signal for the set of semiconductor switching elements based on the phase signal, the output voltage command value, and the carrier signal;
an offset removal block that calculates an offset correction value based on even-order harmonics superimposed on the input current detection value, subtracts the offset correction value from the input current detection value, and corrects the input current detection value;
A control device for an AC chopper circuit, comprising: The offset removal block includes:
2. The controller for an AC chopper circuit according to claim 1, wherein the adjustment of the offset correction value is interrupted when the absolute value of the even-order harmonic is greater than a first threshold. The offset removal block includes:
3. A controller for an AC chopper circuit according to claim 1, wherein said offset correction value is limited within a preset range. 4. The controller for an AC chopper circuit according to claim 1, wherein the adjustment of the offset correction value is interrupted when the input current amplitude command value is greater than a second threshold value. 5. A controller for an AC chopper circuit according to claim 2, wherein, when the adjustment of said offset correction value is interrupted, said offset correction value calculated immediately before interruption is used. A capacitor, a set of semiconductor switching elements connected in series as an upper arm and a lower arm, and a set of diodes connected in series are connected in parallel. A control method for an AC chopper circuit in which a single-phase AC power supply is connected between a pair of diode connection points,
In the current control block, controlling the input current detection value obtained by detecting the input current of the AC chopper circuit to be the input current amplitude command value,
In an output voltage command value calculation block, the output voltage command value is calculated by superimposing the output of the current control block on the duty ratio calculated from the reference sine wave,
In the PLL block, a phase signal synchronized with the voltage of the single-phase AC power supply is calculated,
generating a gate signal for the set of semiconductor switching elements based on the phase signal, the output voltage command value, and the carrier signal in the PWM modulation block;
In the offset removal block, an offset correction value is calculated based on even-order harmonics superimposed on the input current detection value, and the input current detection value is corrected by subtracting the offset correction value from the input current detection value. A control method for an AC chopper circuit, characterized by:

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