JP4912333B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a heat treatment technique and other wafer processing techniques in a method for manufacturing a semiconductor device (or a semiconductor integrated circuit device), and particularly to a technique that is effective when applied to its transfer technique.

  Japanese Patent Application Laid-Open No. 7-142553 (Patent Document 1) discloses a technique for detecting a wafer position shift on a boat using a sensor on a wafer transfer device in relation to wafer transfer in a vertical heat treatment furnace.

  In Japanese Patent Laid-Open No. 2005-142244 (Patent Document 2), regarding wafer transfer in a vertical heat treatment furnace, after a wafer is placed on a boat, the transfer arm is moved, thereby shifting the wafer position on the boat. A technique for detecting by a sensor on a wafer transfer machine is disclosed.

  Japanese Patent Application Laid-Open No. 2005-142245 (Patent Document 3) discloses a technique for monitoring the state of accommodation of wafers on a boat by detecting light transmitted horizontally through the boat with respect to wafer transfer in a vertical heat treatment furnace. Is disclosed.

  Japanese Patent Application Laid-Open No. 6-20981 (Patent Document 4) discloses a technique for detecting a wafer storage state on a boat by a sensor installed near the exit of a processing chamber, regarding wafer conveyance in a vertical heat treatment furnace. Yes.

  Japanese Patent Application Laid-Open No. 2007-227781 (Patent Document 5) describes a wafer held in a transfer arm in order to avoid a transfer mistake or the like when an LCD substrate or the like is processed by a multi-chamber processing apparatus. A technique for detecting whether or not the horizontal position on the transfer arm is correct is disclosed.

JP-A-7-142553 JP 2005-142244 A JP 2005-142245 A JP-A-6-20981 JP 2007-227781 A

  In batch processing vertical furnaces (oxidation, diffusion, CVD, etching), one or more wafers are transferred to a vertical boat (wafer storage jig) by a transfer robot arm, and then the boat is used as the furnace body. Insert and process. After the processing is completed, the wafer is unloaded by the reverse operation. In such a vertical furnace, once manual adjustment (initial adjustment) has been performed on the wafer transfer position to the boat and the wafer unloading position from the boat, quantitative state monitoring and position correction are performed. Was not done.

  The reason for this is that the vertical furnace has an appropriate monitoring and correction function for changes in the wafer storage position due to deterioration of the boat that stores the wafers (chemical solution etching cleaning, thermal deformation) and changes over time in the wafer transfer position of the transfer mechanism. Because there is no. For this reason, when wafer transfer is performed by the wafer transfer robot, collision (contact) occurs between the wafer and the boat (wafer storage unit) or between the wafer transfer arm and the wafer in the boat, and the wafer is fatal such as scratches and particle adhesion. Was causing flaws. Further, the fatal defects are not limited to the wafers that collide (contact), but have spread to a plurality of wafers (about 150 at the maximum) in the boat due to the scattering and dropping of dust.

  In order to solve such a problem, the inventors of the present application have examined that a collision occurs between a wafer transfer arm and a wafer in a boat or between a wafer and a boat (a wafer storage unit such as a wafer folder). The reference position (reference coordinate) is changed by the time-dependent change of the wafer transfer arm and transfer system (including the control system) or the time-dependent change of the heat treatment furnace, particularly the wafer boat (heat treatment wafer folder). It became clear that it was to shift.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the present invention relates to a semiconductor manufacturing method in which a plurality of wafers are processed at once by a batch type vertical wafer processing furnace, in the case of loading a wafer into a wafer processing boat or unloading a wafer from a wafer processing boat. In addition, with the wafer held in the transfer mechanism, the relationship between the reference height on the wafer processing boat and the height of the wafer holding the wafer in the transfer mechanism is monitored, and based on the result, the wafer, boat, and transfer mechanism are monitored. The possibility of causing an undesired collision or contact between any two of these is automatically detected in advance.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, when a wafer is loaded into the wafer processing boat or unloaded from the wafer processing boat, the reference height on the wafer processing boat and the wafer held in the transfer mechanism are held in the transfer mechanism. The height relationship between the two is monitored automatically and the possibility of undesired collision or contact between any two of the wafer, boat, and transfer mechanism is automatically detected in advance. Troubles due to changes with time of each part such as a robot or a wafer processing apparatus (including a control apparatus) or accumulation of offset deviation can be avoided, and a highly reliable processing process can be provided.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) In a batch type vertical wafer processing apparatus that batch-processes a large number of wafers to be processed, a plurality of wafers to be processed among the wafers to be processed have a plurality of wafer tweezers. Held by a robot or other wafer transfer robot having a plurality of wafer tweezers (including the case where the apparatus to be used has only a single wafer transfer robot), on the wafer processing boat, along the main axis, By repeating a plurality of wafer loading operation cycles in which each main surface of a large number of wafers to be processed is loaded so as to be substantially orthogonal to the main axis of the wafer processing boat, the large number of wafers to be processed are used for the wafer processing. Transfer to the boat;
(B) inserting the wafer processing boat containing the wafers to be processed into a wafer processing chamber;
(C) performing wafer processing on the multiple processing wafers in the wafer processing chamber in a state where the main shaft of the wafer processing boat is substantially vertical;
(D) discharging the wafer processing boat containing the wafers to be processed that have undergone the wafer processing from the wafer processing chamber;
(E) A plurality of wafers to be processed among the plurality of wafers to be processed on the wafer processing boat discharged from the wafer processing chamber are held by the wafer transfer robot or the other wafer transfer robots, and the wafers A step of carrying out the plurality of wafers to be processed on the wafer processing boat out of the wafer processing boat by repeating a plurality of wafer unloading operation cycles to be carried out of the processing boat;
Here, at least one of the plurality of wafer unload operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e) includes the following sub-steps: :
(X1) a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and a reference plane orthogonal to the main axis on the wafer processing boat in a state where a plurality of wafers to be processed are held Detecting a relative distance from at least one of a plurality of wafers to be processed.

2. 2. The method of manufacturing a semiconductor device according to 1 above, wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in (e). Further includes the following substeps:
(X2) Based on the result of the sub-process (x1), when necessary, the wafer processing boat, a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and the multiple objects A step of automatically performing avoidance processing so as to avoid occurrence of undesired contact between any two of the processing wafers.

3. 3. The method of manufacturing a semiconductor device according to 1 or 2, wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e). One further includes the following substeps:
(X2) A step of automatically stopping the wafer transfer robot or the other wafer transfer robot when necessary based on the result of the substep (x1).

4). 4. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein at least one of the plurality of wafer loading operation cycles in the step (a) or the plurality of wafer unloading in the step (e). At least one of the operation cycles further includes the following sub-steps:
(X2) A step of generating an alarm when necessary based on the result of the substep (x1).

5. 5. The method of manufacturing a semiconductor device according to any one of 1 to 4, wherein at least one of the plurality of wafer loading operation cycles in the step (a) or the plurality of wafer unloading in the step (e). At least one of the operation cycles further includes the following sub-steps:
(X2) Based on the result of the sub-process (x1), when necessary, the wafer processing boat, a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and the multiple objects Automatically correcting the operating conditions of the wafer transfer robot or the other wafer transfer robot so as to avoid the occurrence of undesired contact between any two of the processed wafers.

  6). 6. In the method of manufacturing a semiconductor device according to any one of items 1 to 5, the reference plane is set on a dummy wafer on the wafer processing boat.

  7). 7. In the method of manufacturing a semiconductor device according to any one of 1 to 6, the detection of the relative distance is performed in a first cycle of the plurality of wafer load operation cycles.

  8). 8. The method for manufacturing a semiconductor device according to any one of 1 to 7, wherein the semiconductor device is executed in a first cycle among the plurality of wafer unload operation cycles.

  9. 9. In the method for manufacturing a semiconductor device according to any one of 1 to 8, the relative distance is detected optically.

  10. 10. In the method for manufacturing a semiconductor device according to any one of 1 to 9, the relative distance is detected for at least two of a plurality of wafers to be processed that are held.

  11. 11. The method of manufacturing a semiconductor device according to any one of 1 to 10, wherein the relative distance is detected by two different points on the wafer in an extending direction of a wafer tweezer holding the wafer to be detected or Run for more.

  12 12. In the method of manufacturing a semiconductor device according to any one of 1 to 11, the relative distance is detected by detecting at least one of the plurality of wafer load operation cycles and the plurality of wafer unload operation cycles. In at least one of the following.

  13. 13. In the method for manufacturing a semiconductor device according to any one of items 1 to 12, the relative distance is detected in a cycle other than the first cycle among the plurality of wafer load operation cycles.

  14 14. The method of manufacturing a semiconductor device according to any one of 1 to 5 and 7 to 13, wherein the reference surface is set on one of the wafers to be processed on the wafer processing boat. The

  15. 15. The method for manufacturing a semiconductor device according to any one of 1 to 14, wherein the semiconductor device is executed in a cycle other than a first cycle among the plurality of wafer unload operation cycles.

  16. 16. In the method for manufacturing a semiconductor device according to any one of 1 to 15, the relative distance is detected in two or more cycles among the plurality of wafer load operation cycles.

  17. 17. The method for manufacturing a semiconductor device according to any one of 1 to 16, wherein the semiconductor device is executed in two or more cycles among the plurality of wafer unload operation cycles.

  18. 18. In the method for manufacturing a semiconductor device as described above in any one of 1 to 17, in the substep (x1), a pitch between the plurality of wafers to be processed that are held is further detected.

  19. 19. In the method of manufacturing a semiconductor device according to any one of items 1 to 18, further, in the sub-step (x1), an inclination between the plurality of wafers to be processed being held is detected.

  20. 20. In the method of manufacturing a semiconductor device as described above in any one of 1 to 19, in the lower step (x1), the plurality of wafers to be processed that are held are all in contact with the wafer processing boat. Done.

21. A semiconductor device manufacturing method including the following steps:
(A) In a batch processing type vertical wafer processing apparatus that batch-processes a large number of wafers to be processed, a plurality of wafers to be processed among the wafers to be processed are transferred to a wafer transfer robot or another wafer transfer robot. (Including the case where the apparatus to be used has only a single wafer transfer robot), and each main surface of the multiple wafers to be processed along the main axis is on the wafer processing boat. Transferring a plurality of wafers to be processed onto the wafer processing boat by repeating a plurality of wafer loading operation cycles in which the wafer is loaded so as to be substantially orthogonal to the main axis of the boat;
(B) inserting the wafer processing boat containing the wafers to be processed into a wafer processing chamber;
(C) performing a wafer process on the multiple wafers to be processed in the wafer processing chamber;
(D) discharging the wafer processing boat containing the wafers to be processed that have undergone the wafer processing from the wafer processing chamber;
(E) A plurality of wafers to be processed among the plurality of wafers to be processed on the wafer processing boat discharged from the wafer processing chamber are held by the wafer transfer robot or the other wafer transfer robots, and the wafers A step of carrying out the plurality of wafers to be processed on the wafer processing boat out of the wafer processing boat by repeating a plurality of wafer unloading operation cycles to be carried out of the processing boat;
Here, at least one of the plurality of wafer unload operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e) includes the following sub-steps: :
(X1) In a state where a plurality of wafers to be processed are held by the wafer transfer robot or the other wafer transfer robot, a reference position on the wafer processing boat and a plurality of wafers to be processed are held. Detecting a relative distance to at least one wafer;

22. 24. In the method of manufacturing a semiconductor device according to item 21, at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in (e). Further includes the following substeps:
(X2) Based on the result of the sub-process (x1), if necessary, any of the wafer processing boat, the wafer transfer robot or the other wafer transfer robot, and the multiple wafers to be processed A step of automatically performing avoidance processing so as to avoid occurrence of undesired contact between the two.

23. 23. In the method of manufacturing a semiconductor device according to item 21 or 22, at least one of the plurality of wafer load operation cycles in step (a) or at least one of the plurality of wafer unload operation cycles in (e). One further includes the following substeps:
(X2) A step of automatically stopping the wafer transfer robot or the other wafer transfer robot when necessary based on the result of the substep (x1).

24. 24. In the method of manufacturing a semiconductor device as described above in any one of 21 to 23, at least one of the plurality of wafer loading operation cycles in the step (a) or the plurality of wafer unloading in the step (e). At least one of the operation cycles further includes the following sub-steps:
(X2) A step of generating an alarm when necessary based on the result of the substep (x1).

25. 25. In the method of manufacturing a semiconductor device according to any one of 21 to 24, at least one of the plurality of wafer loading operation cycles in the step (a), or the plurality of wafer unloading in (e). At least one of the operation cycles further includes the following sub-steps:
(X2) Based on the result of the sub-process (x1), if necessary, any of the wafer processing boat, the wafer transfer robot or the other wafer transfer robot, and the multiple wafers to be processed Automatically correcting the operating conditions of the wafer transfer robot or the other wafer transfer robot so as to avoid the occurrence of undesired contact between the two.

  26. 26. In the method for manufacturing a semiconductor device as described above in any one of 21 to 25, the reference plane is set on a dummy wafer on the wafer processing boat.

  27. 27. In the method for manufacturing a semiconductor device as described above in any one of 21 to 26, the detection of the relative distance is executed in a first cycle of the plurality of wafer load operation cycles.

  28. 28. In the method for manufacturing a semiconductor device as described above in any one of 21 to 27, the semiconductor device is executed in a first cycle of the plurality of wafer unload operation cycles.

  29. 29. In the method of manufacturing a semiconductor device according to any one of 21 to 28, the relative distance is detected optically.

  30. 30. In the method for manufacturing a semiconductor device as described above in any one of 21 to 29, the relative distance is detected for at least two of a plurality of wafers to be processed that are held.

  31. 31. In the method of manufacturing a semiconductor device as described above in any one of 21 to 30, the relative distance is detected by a wafer tweezer of the wafer transfer robot or the other wafer transfer robot holding the wafer to be detected. Run on two or more different points on the wafer in the extending direction.

  32. 32. In the method of manufacturing a semiconductor device as described above in any one of 21 to 31, the relative distance is detected by detecting at least one of the plurality of wafer load operation cycles and the plurality of wafer unload operation cycles. In at least one of the following.

  33. 33. In the method for manufacturing a semiconductor device as described above in any one of 21 to 32, the detection of the relative distance is executed in a cycle other than the first cycle among the plurality of wafer load operation cycles.

  34. 34. In the method for manufacturing a semiconductor device according to any one of 21 to 25 and 27 to 33, the reference plane is set on one of the multiple wafers to be processed on the wafer processing boat. The

  35. 35. In the method of manufacturing a semiconductor device as described above in any one of 21 to 34, the semiconductor device is executed in a cycle other than the first cycle among the plurality of wafer unload operation cycles.

  36. 36. In the method of manufacturing a semiconductor device as described above in any one of 21 to 35, the detection of the relative distance is performed in two or more cycles among the plurality of wafer load operation cycles.

  37. 37. In the method for manufacturing a semiconductor device according to any one of 21 to 36, the semiconductor device is executed in two or more cycles among the plurality of wafer unload operation cycles.

  38. 38. In the method for manufacturing a semiconductor device as described above in any one of 21 to 37, in the substep (x1), a pitch between the plurality of wafers to be processed that are held is further detected.

  39. 39. In the method for manufacturing a semiconductor device as described above in any one of 21 to 38, in the substep (x1), an inclination between the plurality of wafers to be processed that are held is further detected.

  40. 40. In the method of manufacturing a semiconductor device as described above in any one of 21 to 39, in the lower step (x1), all of the plurality of wafers to be processed held are in a non-contact state with the wafer processing boat. Done.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, the term “silicon oxide film” refers not only to relatively pure undoped silicon oxide, but also to FSG (Fluorosilicate Glass), TEOS-based silicon oxide, and SiOC ( Silicon Oxicarbide) or Carbon-doped Silicon oxide (OSG) (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass) and other thermal oxide films, CVD oxide films, SOG (Spin ON Glass) , Nano-clustering silica (NSC) -coated silicon oxide, silica-based low-k insulating film (porous insulating film) with pores introduced in the same material, and these Needless to say, it includes a composite film with another silicon-based insulating film as an essential component.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer or an SOI wafer, and a semiconductor layer or the like. Needless to say, composite wafers are also included.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Outline of semiconductor manufacturing method in the present embodiment (mainly FIG. 1)
FIG. 1 is a block diagram illustrating an outline of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Based on FIG. 1, the outline of the semiconductor manufacturing method in the present embodiment will be described.

  As shown in FIG. 1, in a vertical batch type wafer processing furnace 51 such as a heat treatment furnace, a wafer is transferred from a wafer transfer container 52 such as a hoop (normally, a plurality of wafer transfer containers are set in a load port). The transfer tool of the transfer mechanism 64 in the section 53 unloads the wafers 1 (one at a time, but usually carries about 5 at a time for shortening the transfer time), and a wafer processing wafer holder 54 ( The wafer is loaded into a wafer processing wafer boat. For example, immediately before this loading, the wafer 1 is held on the transfer tool and is in the vicinity 55 of the wafer processing wafer holder 54, and the wafer 1 and the wafer processing wafer holder 54 are not in contact with each other. The relative position of the wafer 1 on the tool and a predetermined reference surface on the wafer processing wafer holder 54 (usually, the reference height of the wafer processing wafer holder 54 is always almost vertical) is detected ( Wafer position inspection during loading). Thereafter, if there is no problem, the wafer 1 is placed on the wafer holder 54 for wafer processing. With the wafer 1 placed on the wafer processing wafer holder 54, the wafer processing wafer holder 54 is raised by the boat elevator and is subjected to wafer processing in the wafer processing chamber 56. When the processing is completed, the wafer processing wafer holder 54 is lowered by the boat elevator and goes out of the wafer processing chamber 56. Then, the transfer tool lifts the processed wafer 1 and carries it out of the wafer processing wafer holder 54. Here, when the processed wafer 1 is lifted by the transfer tool and is not in contact with the wafer processing wafer holder 54 and in the vicinity 55 of the wafer processing wafer holder 54, The relative position between a predetermined reference plane on the wafer 1 and the wafer processing wafer holder 54 is detected (wafer position inspection during unloading). Thereafter, if there is no particular problem, the wafer 1 is returned to the original slot of the original wafer transfer container 52 (which may be another wafer transfer container) (or may be another slot).

  Here, the wafer position inspection such as the wafer position inspection at the time of loading or the wafer position inspection at the time of unloading may be performed at least one of the time of loading or unloading. Further, when a large number of wafers are transferred by a repetitive operation, it may be performed at least once. Further, when the apparatus is stable, it may be carried out once for several wafer processes.

  In addition, when an abnormality is found by the wafer position inspection, a process for avoiding an undesired contact between any two of the transfer tool, the wafer 1 and the wafer processing wafer holder 54 (avoidance process). (Or avoidance operation) is automatically performed. This avoidance process is a conveyance stop (usually accompanied by an alarm display. Generally, a conveyance stop is a measure taken when a danger such as a collision cannot be avoided by a normal response), and a reference position of the conveyance mechanism 64 Correction and change of settings such as wafer pitch, etc. (This is a case where self can be avoided by relatively minor transfer condition correction), alarm display (without stop of transfer) (deviation from reference value) Is relatively small, so there is little possibility of a serious collision for the time being, but a relatively minor correction of the transport conditions does not solve the problem).

  Here, the wafer 1 is in contact with the wafer processing wafer holder 54 in a non-contact state because the undesired contact such as a collision occurs when the wafer 1 is not in contact with the wafer processing wafer holder 54. This is because (or the position of the wafer transfer tool) is in a positional relationship where it should collide as it proceeds. Therefore, even if the positional relationship between the wafer 1 placed on the wafer processing wafer holder 54 and the reference plane is inspected, it can be considered that there is little substantial significance. It merely looks at the variation of how the individual wafers 1 are warped and loaded, and does not evaluate the overall position offset between the transfer mechanism 64 and the wafer processing wafer holder 54. .

  The predetermined reference surface on the wafer processing wafer holder 54 is usually the upper surface of the dummy wafer that is always placed at both ends of the wafer processing wafer holder 54 and that is closest to the product wafer. Is selected.

  In this way, the regular inspection (separate from the mass production process) is generally performed by monitoring the wafer position periodically (inspection process embedded in the mass production process) during normal mass production wafer processing. Since the correction can be made while the difference from the reference position relationship is small compared to the case of (Process) etc., inevitable variations or sudden displacements of individual wafers act synergistically Aside from rare events, factors that lower the device availability such as collisions can be greatly reduced.

2. Description of semiconductor manufacturing apparatus used in this embodiment (mainly FIGS. 2 to 7)
FIG. 2 is a front view of the wafer processing apparatus (non-wafer processing period) showing the structure of the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 3 is a front view of the wafer processing apparatus (wafer processing period) showing the structure of the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 4 is a perspective view of the periphery of the wafer boat showing the arrangement (apparatus process a) of the optical displacement sensor in the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 4 is an enlarged perspective view of the periphery of the boat 54 of FIG. FIG. 5 is an internal structure explanatory view showing the internal configuration of the optical displacement detector in the wafer processing apparatus used in the method of manufacturing a semiconductor device in one embodiment of the present invention. FIG. 6 is a front view of the apparatus showing the structure of the transfer mechanism of the wafer transfer unit in the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention and the details of the main part of the boat (FIG. 6A). And FIG. 6B is a bottom view of the device (FIG. 6B). FIG. 7 is a front view of the apparatus showing the structure of the entire transfer mechanism of the wafer transfer unit in the wafer processing apparatus used in the method of manufacturing a semiconductor device according to one embodiment of the present invention. Based on these, the semiconductor manufacturing apparatus used in the present embodiment will be described.

  As shown in FIG. 2, FIG. 4, and FIG. 7, a batch type wafer processing apparatus 51 (thermal treatment between 350 ° C. and 1200 ° C. such as a thermal oxidation apparatus, thermal nitridation apparatus, annealing apparatus, CVD apparatus, A load port of a vapor phase surface processing apparatus such as an etching apparatus or the like contains a plurality of hoops (typically, in the case of a 300φ wafer, 12 wafers are accommodated per hoop. The wafer pitch is about 12.5 mm. On the other hand, a wafer cassette of 68 wafers is usually set in a wafer cassette of 200φ wafers. Normally, 300-phi wafers have a charge of about 25 to 100 sheets (considering 200φ and other wafer conditions, a normal batch process is considered to be in the range of about 25 to 250 sheets). If the number of lots is 25, the number of hoops to be set is 4 and 1 to 12 is 9 to 10. The transport unit 53 is normally maintained in a clean environment (dry air or nitrogen gas atmosphere) by downflow, and a transport robot 65 is provided inside. The transfer robot 65 is controlled by a transfer control system 67, and together with this, a wafer transfer mechanism 64 is configured. Usually, a single transfer robot 65 is provided in the wafer transfer mechanism 64. However, if a plurality of transfer robots 65 are prepared and operated simultaneously, transfer efficiency can be improved. it can. Of course, a single transfer robot has an advantage that the space of the apparatus can be reduced. Note that the transfer robot may hold and hold the back surface of the wafer without being sucked. Here, the description will be made on what is adsorbed. The transfer robot 65 is usually provided with five tweezers 66 (wafer holding arms) for directly holding the back surface of the wafer 1 by vacuum suction. The tweezers 66 are held by the transfer robot 65 one by one by a tweezer holder 91 (FIG. 7). The wafers 1 to be processed are held by five tweezers 66 by five, and loading to the boat 54 and unloading from the boat 54 are performed. However, the number of wafers 1 that the transfer robot 65 carries at one time is the same as or less than the number of tweezers 66. For example, only one sheet may be conveyed at a break of a conveyance lot. Wafer position detection is performed from a position detection optical system 61 (consisting of a light projecting part 61a and a light receiving part 61b as shown in FIG. 4 with a belt-like light beam 71 interposed between the two parts). The output detection signal is analyzed by the position detection analysis / control unit 62, necessary processing is determined, and an instruction is issued to the transport control system 67 as necessary. A boat 54 (usually mainly made of quartz or SiC) is installed on a boat / elevator base 121, a boat lower substrate 103, a boat upper substrate, and three or four pillars 101a (see FIG. 4) etc. The boat 54 is normally held so that the main shaft 185 in the longitudinal direction is substantially vertical. The wafer processing unit 57 includes a heater 59, a reaction tube 58 (usually a quartz tube or a SiC tube) therein, a wafer processing chamber 56 and the like therein. Similarly, the reaction tube 58 is installed almost vertically. The wafers 1 to be processed are close to each other between the wafers 1 along the main axis thereof so that the main surfaces 1a of the many wafers 1 are almost horizontal in the boat 54 (the wafers are spaced from each other). This is called the wafer pitch. Here, “vertical” or “horizontal” is not completely “vertical” or “horizontal”, but may be tilted by several degrees (the slot itself may be tilted slightly from the horizontal). In addition, the wafer is often held at an angle of about several degrees so as not to drop by vibration. Similarly, the main axis of the boat 54 and the reaction tube 58 may be slightly inclined. Further, it may be inclined by about 30 degrees from the vertical as it is literally (basically a substantially vertical range).

  Further, the posture of the boat at the time of wafer processing may or may not be substantially vertical when the wafer is loaded or unloaded. For example, there are cases where loading or unloading is easier to perform if tilted by several tens of degrees (sometimes close to horizontal, but there is a problem that the position of the wafer cannot be determined when completely horizontal). However, since the slots of the hoop are arranged substantially vertically (the slot surface is substantially horizontal), it is advantageous from the aspect of controlling the tweezers 66 that the posture of the boat is also substantially vertical.

  As shown in FIG. 3, during wafer processing, the boat 54 is housed in a wafer processing chamber 56 by a boat elevator. At this time, various gases are supplied to the wafer processing chamber 56 as necessary. Further, the wafer processing chamber 56 can be decompressed, pressurized, or vacuumed as necessary. There may also be a plasma excitation system.

  Next, the internal configuration of the position detection optical system 61 and the position detection analysis / control unit 62 will be briefly described. As shown in FIG. 5, the position detection optical system 61 includes a light projecting unit 61a that emits a thin and wide position detection light beam 71 (visible light) and a light receiving unit 61b that receives the light projecting unit 61b. An object to be observed 76 (wafer) is placed between them. The light emitted from the light source 73 passes through the diffusion plate 74 and is converted into a parallel beam by the lens 75 to become a light beam 71. The light beam 71 that was originally a single band is intercepted by the object to be observed 76 on the way, branches into a large number of bands, is condensed by the lens 77 in the light receiving unit 61b, and is divided into two by the beam splitter. , Some are sent to the monitor system and some are sent to the observation system. In the observation system, it is collimated again by the lens 81, detected by the sensor 81 on the line, and sent to the position detection analysis / control unit 62 (observation system detection light signal). On the other hand, the monitor system detection light signal partially sent to the monitor system is similarly collimated by the lens, detected by the sensor 79 on the line, and sent to the position detection analysis / control unit 62. In the position detection analysis / control unit 62, the monitor detection light signal is first A / D converted by the A / D conversion circuit 83 a, sent to the frame memory 84, and displayed on the monitor display screen 85. On the other hand, the observation system detection light signal is similarly A / D converted by the A / D conversion circuit 83b, and the digital signal processor (DSP) 86 and the central processing unit (CPU) 87 refer to the monitor system image data. Are analyzed, a necessary collision avoidance process is determined, and an instruction is issued to the transport control system 67.

  Next, details of the holding state of the wafer 1 by the tweezer 66 and the relationship between the boat 54 and the wafer 1 will be described. As shown in FIGS. 6A and 6B, the tweezer 66 is provided with a vacuum supply passage 92, and a vacuum suction opening 93 is opened at the tip. The tweezers 66 with the wafer 1 and its main surface 1a facing up and vacuum-sucked on its back surface are upper and lower wafer hangers 107a and 107b provided on the pair of side pillars 101a and center pillars 101b of the boat 54, respectively. , That is, the slot 106 is entered in a non-contact state (region near the boat 54). In this state, the wafer 1 is observed with a single or a plurality of strip-shaped observation beams 71.

  In the subsequent drawings, the shape of the center pillar 101b is simplified for convenience of illustration. Accordingly, the relationship between the center pillar 101b and its wafer hanger 107b is similar to that shown in FIG. In the four-pillar system, the center pillars are divided and two are arranged at intervals. The pillar is usually made of quartz, and a groove is cut and formed in a columnar or other columnar member to integrally form the wafer / hanger portion and the pillar main body portion.

3. Description of apparatus processing flow a of the semiconductor manufacturing method in the present embodiment (mainly FIG. 8 to FIG. 27 and FIG. 50)
FIG. 8 is a schematic diagram showing a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters a transfer wafer storage container in order to unload a wafer from the transfer wafer storage container). It is a top view (FIG. 8A) and a schematic front view (FIG. 8B). FIG. 8A shows the direction of the dotted arrow from the broken line part of FIG. 8B. FIG. 9 shows a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters a transfer wafer storage container and lifts off a target wafer to unload the wafer from the transfer wafer storage container). Is a schematic front view. FIG. 10 is a schematic front view of a processing sequence (a step in which a tweezer carries out a target wafer from a transfer wafer storage container) of a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 11 is a schematic front view of a processing sequence (step of reducing the interval between tweezers) of the method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 12 is a schematic front view of a processing sequence (a step in which a tweezer holds a wafer and approaches a boat) of a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 13 is a processing sequence of a method of manufacturing a semiconductor device according to an embodiment of the present invention (the tweezer holds a wafer and approaches the wafer mounting position of the boat, and the held wafer and the boat are in a non-contact state. FIG. 6 is a schematic front view of a step of monitoring a relationship between a held wafer and a reference position. FIG. 14 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to one embodiment of the present invention (step where the tweezer holds and lowers the wafer and places the wafer on the finger of the slot 106 corresponding to the boat). It is. FIG. 15 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to one embodiment of the present invention (step where the tweezers land on the fingers and then move down further away from the back surface of the wafers). FIG. 16 is a schematic front view of a processing sequence (a step where the tweezer retracts from the boat) of the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 17 is a schematic front view of a processing sequence (step in which a boat filled with wafers rises toward the wafer processing chamber) of the semiconductor device manufacturing method according to one embodiment of the present invention. FIG. 18 is a schematic front view of a processing sequence (wafer processing step) of a semiconductor device manufacturing method according to an embodiment of the present invention. FIG. 19 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a boat on which a wafer has been processed descends). FIG. 20 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer approaches a boat to carry out a wafer after the completion of wafer processing). FIG. 21 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters the boat in a non-contact manner to carry out a wafer after completion of wafer processing). FIG. 22 shows a processing sequence of a method of manufacturing a semiconductor device according to an embodiment of the present invention (wafers that have been processed by the wafer are held by the tweezers and the wafers are lifted off from the boat, and the held wafers and reference positions) FIG. FIG. 23 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer carries out a wafer after completion of wafer processing from a boat). FIG. 24 is a schematic front view of a processing sequence (step of enlarging the interval between tweezers) of the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 25 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (step of approaching the original slot of the wafer hoop even if the wafer is held by the tweezers). FIG. FIG. 26 shows a processing sequence of a method for manufacturing a semiconductor device according to an embodiment of the present invention (a wafer that has been subjected to wafer processing is held by a tweezer and enters the original slot of the original wafer hoop in a non-contact state. It is a schematic front view of (step). FIG. 27 shows a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a wafer that has been processed by a wafer is held by a tweezer and lowered and placed on the original shelf of the original wafer hoop. FIG. 6 is a schematic front view of the step of further descending. FIG. 50 is a block flow diagram showing an overall apparatus processing flow of the semiconductor manufacturing method according to the present embodiment. Based on these, the apparatus processing flow a of the semiconductor manufacturing method in the present embodiment will be described.

  In the following, description will be made sequentially from the step 151 of entering the tweezers into the wafer hoop 95 in the wafer load operation cycle 181 of FIG. As shown in FIG. 8, the hoop 95 (or a wafer transfer container such as a wafer cassette) is provided with a wafer slot 96 delimited by a wafer support plate 97, and generally has about 25 wafers 1 (1a). , 1b, 1c, 1d, 1e, etc.). In order to transfer the wafer 1 (specifically, a wafer group, the same applies hereinafter) to the boat 54 (heat-resistant wafer container or heat treatment wafer jig), first, a tweezer 66 (specifically, a tweezer group) of the wafer transfer robot 65. , The same applies hereinafter) enters a target slot 96 (specifically, a group of slots, the same applies hereinafter) in the target hoop 95 without contact between the hoop 95 and the tweezer 66 and between the wafer 1 and the tweezer 66. To do.

  Thereafter, as shown in FIG. 9, the tweezer 66 rises to take off the wafer 1 from the wafer support plate 97 (wafer lift step 152 in FIG. 50). Next, as shown in FIG. 10, the tweezer 66 moves backward in a non-contact state with the hoop 95, the wafer 1, and the tweezer 66, and the wafer 1 is unloaded (wafer unloading step 153 from the hoop of FIG. 50). Subsequently, as shown in FIG. 11, the pitch between the tweezers 66 is adjusted as necessary. In general, in the case of a 300φ wafer, the wafer is often reduced, but may not be changed or may be enlarged (twiser pitch changing step 154 in FIG. 50). Therefore, as shown in FIG. 50, this step is skipped if the pitch is not changed. Thereafter, the tweezer 66 approaches the boat 54 while holding the wafer 1, and the boat 54, the tweezer 66, and the wafer 1 enter the vicinity region 55 in a non-contact state (approach / entry to the boat in FIG. 50). Step 155).

  Next, as shown in FIG. 13, the position of the wafer 1 on the horizontal plane is almost in the vicinity of the mounting position on the boat 54, and the boat 54, the tweezer 66, and the wafer 1 are not in contact with each other. Stop (may be a substantial stop, or may be moving at a low speed or normal speed. While moving, the vibration associated with the stop can be avoided and time can be saved. Then, it is not necessary to move the measurement system, so there are advantages such as easy measurement, etc. Measuring at the stop position before the mounting operation is advantageous from the viewpoint of measurement accuracy and time.) The height H1 of the wafer 1 (1a, 1b, 1c, 1d, 1e) held by the tweezers 66 with the upper surface of the dummy wafer 1r placed on the boat 54 by the measurement light beam 71 as the reference plane Hr. H2, H3, H4 5 (for example, the height or position of the center), and then the reference surface height and pitch information of the wafer transfer mechanism 64 and the actual reference surface height and slot pitch (boat pitch on the boat) on the boat 54 are measured. The difference is calculated (wafer position inspection step 156 in FIG. 50). This inspection is normally performed in the first cycle of the wafer loading operation cycle 181 (FIG. 50), but is skipped in the cycle in which the inspection is not performed as shown in FIG. The merit of carrying out in the wafer loading operation cycle 181 (FIG. 50) is that, by performing batch processing using wafers or boats in which problems have occurred due to transfer errors, contamination or the like is not diffused throughout the batch or the entire apparatus. It is in. Further, the merit of performing in the first cycle of the wafer load operation cycle 181 (FIG. 50) is that when the transfer deviation is approaching the allowable limit, the load operation is repeated without first inspecting. There is a high possibility that a collision will occur due to variations inherent in the wafer. In addition, if a transfer deviation is found after many wafers are loaded, there is a high possibility that the already loaded wafer is affected by a transfer error. Also, as will be explained later, this test can be performed in the first cycle and performed in another cycle. It is also possible to perform this inspection in another cycle without performing this inspection in the first cycle. Further, in the wafer load operation cycle 181 (FIG. 50), this inspection is not performed, and the wafer unload operation cycle 191 (FIG. 50) and other portions can be performed. Similarly, this inspection can be performed in the wafer loading operation cycle 181 (FIG. 50), and can be performed in the wafer unloading operation cycle 191 (FIG. 50) and other portions. When this inspection is performed in the wafer unload operation cycle 191 (FIG. 50), it is normally performed in the first cycle of the wafer unload operation cycle 191 (FIG. 50). Skip as shown. The merit of carrying out this inspection in the wafer unload operation cycle 191 (FIG. 50) is that there is a possibility that the wafer is subjected to fluctuations such as warpage due to wafer processing, resulting in a positional relationship different from the positional relationship at the time of loading. is there. Further, the merit performed in the first cycle of the wafer unload operation cycle 191 (FIG. 50) is almost the same as that performed in the first cycle of the previous wafer load operation cycle 181 (FIG. 50). Also, as will be explained later, this test can be performed in the first cycle and performed in another cycle. The merit of implementing in another cycle is that statistical processing can be performed as a result of obtaining a plurality of reference positions (dummy wafers, one or more product wafers) with respect to deviation from the reference position. It is in a place where it can be eliminated. It is also possible to perform this inspection in another cycle without performing this inspection in the first cycle. The advantage of not performing this inspection in the first cycle and in another cycle is based on the actual product wafer (same as other wafers to be measured), not the dummy wafer that has been processed many times. The error due to the difference in the attributes of the wafer can be eliminated.

  Based on the inspection result, when necessary, the reference surface height and pitch information of the wafer transfer mechanism 64 are corrected (transfer mechanism setting correction step 157 in FIG. 50). At the same time, an alarm may be displayed (for example, an indication that the deviation has been corrected). Also, based on this, when necessary, the height of the tweezer 66 is adjusted in real time (approximately at the same time or at some time interval). The merit of executing the correction operation simultaneously with the inspection is not only that the result can be reflected immediately, but also that the tweezer 66 can be adjusted with high accuracy while simultaneously feeding back the inspection result. On the other hand, the advantage of executing the correction operation when the wafer is held in the tweezers 66 and out of the vicinity region 55 of the boat 54 is that it can move while moving (pitch change steps 154 and 169 in FIG. 50). Can be saved, and there is no unexpected contact due to vibration during adjustment. If a problem occurs when the step is advanced, or if it is unclear how to correct the setting, the wafer transfer robot 65 is stopped and an alarm (for example, an indication that there is a danger of imminent collision) ) Is displayed. If the problem does not occur immediately but it is unclear how to correct the setting, only the alarm (the content of the deviation and the predicted risk) is displayed.

  After that, as shown in FIG. 14, the tweezer 66 is lowered, and the wafer 1 is lowered from a predetermined stop position (position in the horizontal plane) before the mounting operation and is placed on the corresponding wafer hangers 107a and 107b. It is mounted (loading step 158 to the boat of FIG. 50). Subsequently, as shown in FIG. 15, the tweezer 66 is separated from the wafer 1 and further lowered to be in a non-contact state with the wafer 1 and the boat 54 (the tweezer lowering step 159 in FIG. 50). In this state, as shown in FIG. 16, the boat 54 is evacuated (evacuation step 160 from the boat of FIG. 50). At this time, as shown in FIG. 50, when there remains a wafer 1 to be loaded, the process returns to the entry step 151 into the hoop. When all necessary wafers 1 to be processed have been loaded, the process proceeds to the next process chamber. The wafer loading operation cycle 181 is from the entry step 151 to the hoop to the retreat step 160 from the boat.

  Thereafter, as shown in FIG. 17, the boat 54 filled with the wafers 1 is lifted by the boat elevator toward the wafer processing chamber 56 (see FIGS. 2 and 3) (loading step 161 into the processing chamber of FIG. 50). . Further, as shown in FIG. 18, heat treatment and other wafer processing 162 (FIG. 50) are performed in the wafer processing chamber 56. After the wafer processing, as shown in FIG. 19, the boat 54 filled with the wafer 1 is lowered from the wafer processing chamber 56 by a boat elevator and discharged (unloading step 163 from the processing chamber in FIG. 50).

  When the processed wafer 1 is carried out of the wafer processing chamber 56, the tweezer 66 approaches the boat 54 as shown in FIG. 20 (accessing step 164 to the boat in FIG. 50). Further, as shown in FIG. 21, the tweezer 66 enters the boat 54 in a non-contact state as before (step 165 for re-entering the boat in FIG. 50).

  Here, as shown in FIG. 22, as in the case of FIG. 13, the tweezer 66 is lifted in a state where the wafer 1 is vacuum-sucked (held), and the wafer 1 and the boat 54 are not in contact with each other. , Stop (it may be a substantial stop, or it may be moving at a low speed or at a normal speed. While moving, the vibration associated with the stop can be avoided and time can be saved. Since it is not necessary to move the measurement system when stopped, there are advantages such as easy measurement, etc. In addition, when measuring at a position almost ascended from the mounting position on the boat 54, the measurement accuracy and time are also considered. The wafer 1 (1a, 1b, 1c, 1d, 1e) held by the tweezer 66 is defined with the upper surface of the dummy wafer 1r placed on the boat 54 by the measurement light beam 71 as the reference plane Hr. ) Height 1, H 2, H 3, H 4, H 5 (for example, the height or position of the center), and then the reference surface height and pitch information of the wafer transfer mechanism 64, the actual reference surface height on the boat 54 and the slot pitch ( The difference from the wafer pitch on the boat is calculated (wafer position inspection step 166 in FIG. 50). This inspection step can also be skipped as described above (see FIG. 50).

  Based on the inspection result, when necessary, the reference surface height and pitch information of the wafer transfer mechanism 64 are corrected (transfer mechanism setting correction step 167 in FIG. 50). At the same time, an alarm may be displayed (for example, an indication that the deviation has been corrected). Also, based on this, when necessary, the height of the tweezer 66 is adjusted in real time (approximately at the same time or at some time interval). If a problem occurs when the step is advanced, or if it is unclear how to correct the setting, the wafer transfer robot 65 is stopped and an alarm (for example, an indication that there is a danger of imminent collision) ) Is displayed. If the problem does not occur immediately but it is unclear how to correct the setting, only the alarm (the content of the deviation and the predicted risk) is displayed. As described above, this correction step can be skipped when it is not necessary (see FIG. 50).

  Next, as shown in FIG. 23, the wafer 1 and the tweezer 66 are not in contact with the boat 54 while the wafer 1 and the tweezer 66 are not in contact with the boat 1 while the wafer 1 is sucked (held). It carries out outside (unloading step 168 from the boat of FIG. 50). Next, as shown in FIG. 24, the pitch between the tweezers 66 is adjusted as necessary. In general, the image is often enlarged, but may not be changed or may be reduced (Tweezer Pitch Change Step 169 in FIG. 50). Therefore, as shown in FIG. 50, this step is skipped if the pitch is not changed. Subsequently, as shown in FIG. 25, the tweezer 66 approaches the hoop 95 while holding the wafer 1. Further, as shown in FIG. 26, in that state, the tweezer 66 enters the slot 96 of the corresponding hoop 95 without contact (entry step 170 to the hoop in FIG. 50). Subsequently, as shown in FIG. 27, the tweezer 66 is lowered, the wafer 1 is landed on the wafer support plate 97, and further lowered to leave the wafer 1, so that the hoops are not contacted with the wafer and the hoop 95. Retreat to the outside (evacuation step 172 from the hoop in FIG. 50). At this time, as shown in FIG. 50, when the wafer 1 to be unloaded remains in the boat 54, the process returns to the boat approaching step 164. When unloading of all necessary processed wafers 1 is completed, the process proceeds to the next step. From the boat approaching step 164 to the evacuation step 172 from the hoop is a wafer unload operation cycle 191.

4). Detailed description of the optical monitoring method in the apparatus processing flow a of the semiconductor manufacturing method in the present embodiment (mainly FIGS. 47 to 49)
FIG. 47 is a front view (FIG. 47 (a)) and a bottom view (FIG. 47 (b)) of the main part of the light detection portion for explaining the details of the optical monitoring method in the apparatus processing flow of the semiconductor manufacturing method in the present embodiment. It is. FIG. 48 is an explanatory diagram of light intensity distribution illustrating the detected light intensity distribution in the optical monitoring method in the apparatus processing flow of the semiconductor manufacturing method according to the present embodiment. 47 schematically shows the tilt of the wafer as viewed from the direction of arrow X in FIG. 47 (including wafer warpage, curvature and sagging including the wafer tweezer and the wafer) and the tilt of the wafer as viewed from the direction of arrow Y. Has been. The high intensity (a) relates to the beam 71a (a point close to the center of the wafer, hereinafter referred to as “center part”), and the high intensity (b) relates to the beam 71b (a point close to the tip of the wafer, hereinafter referred to as “tip part”). It is about. FIG. 49 is a conceptual diagram showing a basic concept of position or pitch deviation sampling in the apparatus processing flow of the semiconductor manufacturing method according to the present embodiment. Based on these, the details of the optical monitoring method in the apparatus processing flow of the semiconductor manufacturing method in the present embodiment will be described.

  As shown in FIG. 6 or FIG. 13, the wafer position can be inspected with a single beam. However, in order to increase the accuracy, detection is performed with a plurality of beams 71a and 71b as shown in FIG. It is desirable to carry out at two or more different points (a plurality of points) on the wafer 1 in the extending direction of the wafer tweezers 66 holding the wafer to be processed. This is because the wafer tweezer 66 is as thin as about 1 mm and hangs down due to the weight of the wafer 1, so it is important to predict the position of the tip of the wafer 1 from a plurality of points. That is, the reason for the high possibility of a collision is that the outer periphery of the lower end of the front end portion of the wafer 1 and the lower end of the front half. Of course, the upper end of the outer periphery of the rear half of the wafer 1 (the base side of the wafer tweezer 66) becomes a problem in terms of upper contact and collision. Moreover, although it is relatively rare, when the outer periphery of the wafer 1 is warped upward, the upper end portion of the entire outer periphery may cause a problem. The portions where the contact of the wafer 1 or the wafer tweezer 66 is a problem are collectively referred to as the outermost points (including the uppermost point, the lowermost point, the most advanced point, the last point, etc.).

  The actual light receiving pattern is as shown in FIG. As shown in FIG. 48, if there is no inclination, the thickness of the dark portion is substantially the same as the thickness of the wafer in both the central portion thickness Taa and the tip portion thickness Tab as in the dummy wafer 1r and the product wafer 1. Since the wafer 1b is inclined only in the direction perpendicular to the axis of the wafer tweezer 66, that is, the width direction of the wafer tweezer 66 (hereinafter referred to as "orthogonal direction"), Tba is considerably thick, but Tbb is slightly thick. Only. In this respect, the wafer 1c is substantially the same. That is, Tca is considerably thicker and Tcb is only slightly thicker. On the other hand, since the wafer 1d is inclined only in the axial direction of the wafer tweezer 66 (hereinafter referred to as “axial direction”), the thicknesses of Tda and Tdb are substantially the same as those of the wafer. Although it is, it can be seen that the center position is shifted. On the contrary, it is detected that the wafer hangs down in the axial direction. Since both the orthogonal direction and the axial direction of the wafer 1e are inclined, both Tea and Teb are thick, and the center position is shifted. On the contrary, it is detected that the wafer hangs down in the axial direction and is also inclined in the orthogonal direction. Predicting the position of the outermost point in consideration of the inclination information enables precise control.

  In section 3 and the like, the dummy wafer (or product wafer) on the boat 54 is used as a reference height, and the positions of a plurality of wafers held on the wafer tweezer 66 are detected, and the actual reference position and wafer pitch are detected. Although an example in which is calculated is shown, there are various methods for processing these data. As shown in FIG. 49, regarding the position control, the physical allowable range is, for example, that the slot pitch of the boat 54 (corresponding to the wafer pitch) is generally about 8 mm for a 300φ wafer (on the other hand, in the hoop). Is about 12.5 mm). Here, the control accuracy (conveyance error) of the wafer tweezer 66 is generally considered to be about 0.3 mm. Further, the thickness of the wafer is about 0.75 mm, and in addition, the thickness of the wafer tweezer 66 is about 1 mm. Since the inherent variation (sled, tilt, etc.) of each wafer is added to this, the statistically safe range is usually about several millimeters above and below the ideal center value. Therefore, statistically processing the detected relative positions with respect to multiple wafers, that is, calculating the deviation from the reference position and the pitch by eliminating the wafer variation by averaging, pitch estimation by linear regression, etc. Then, more accurate control is possible.

  It is also effective to correct the difference from the sequentially detected reference value by calculating a true deviation amount by statistically eliminating an error in consideration of a moving average or the like.

5. Description of apparatus processing flow b of the semiconductor manufacturing method in the present embodiment (mainly FIGS. 28 and 29)
The following is also a modification regarding the arrangement of the detection system in the apparatus processing flow a.

  FIG. 28 is a perspective view of the periphery of the wafer boat showing the arrangement of the optical displacement sensor (apparatus process b) in the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention. FIG. 28 corresponds to FIG. 4 in the apparatus processing flow a of the semiconductor manufacturing method according to the present embodiment. FIG. 29 shows a processing sequence of a semiconductor device manufacturing method (apparatus process b) according to an embodiment of the present invention (the tweezer holds a wafer and approaches the wafer mounting position of the boat, and the held wafer and the boat are not FIG. 6 is a schematic front view of a step of monitoring a relationship between a held wafer and a reference position in a contact state. Based on these, the apparatus processing flow b of the semiconductor manufacturing method in the present embodiment will be described. Except for the parts described below, it is the same as the description of sections 1 to 4 except where it is clearly not, and the description thereof will not be repeated.

  As shown in FIG. 28, the feature of this batch furnace is that the light projecting unit 61a and the light receiving unit 61b of the position detection optical system 61 (see FIG. 2) are interlocked with the wafer transfer robot 65 by an integral support arm 111. (Up-and-down movement and plane movement in conjunction). The advantage of this structure is that the wafer position inspections 156 and 166 (FIG. 50) can be performed relatively easily regardless of where the wafer 1 is located (may be anywhere in the vicinity region 55 of the boat 54 or outside the vicinity region 55 of the boat 54). can do. Needless to say, the position detection optical system 61 is moved backward so as not to interfere with the transfer between the wafer transfer robot 65 and the hoop 95.

  When such a configuration is used, wafer position inspections 156 and 166 are performed in the middle of the wafer load and unload operation cycle (wafer load operation cycle 181 or wafer load and unload operation cycle 191) described in section 3. (FIG. 50) can be implemented efficiently. That is, as shown in FIG. 29, for example, the upper surface of the wafer 1e loaded in the previous cycle is set to the product wafer reference surface height Hs, and the height of the wafers 1f, 1g, 1h, 1i, and 1j with the beam 71 as before. H6, H7, H8, H9, and H10 are measured. Here, if the dummy wafer reference height Hr is measured in advance, the measurement is substantially based on the dummy wafer reference height Hr. Further, the product wafer reference surface height Hs may be processed as the reference height. In any case, the merit of using the product wafer 1 as a reference wafer is that it is an actual wafer and has the same conditions as other product wafers. The dummy wafer may be deformed by repeated heat treatments. In addition, it is considered that a point relatively close to the measurement target wafer also contributes to an increase in measurement accuracy. Furthermore, there is an advantage that measurement can be performed simultaneously with a relatively narrow beam 71 at any position in the batch.

  Therefore, it is relatively easy to perform wafer position inspection in a plurality of wafer load & unload operation cycles or in all cycles.

6). Description of apparatus processing flow c of the semiconductor manufacturing method in the present embodiment (mainly FIG. 30)
The following is another modification regarding the arrangement of the detection system in the apparatus processing flow a.

  FIG. 30 is a perspective view of the periphery of the wafer boat showing the arrangement of the optical displacement sensor (apparatus process c) in the wafer processing apparatus used in the method of manufacturing a semiconductor device in one embodiment of the present invention. FIG. 30 corresponds to FIG. 4 in the apparatus processing flow a of the semiconductor manufacturing method in the present embodiment. Based on FIG. 30, the apparatus processing flow c of the semiconductor manufacturing method in the present embodiment will be described. Except for the parts described below, the description is the same as the description of sections 1 to 4 and section 5 except where it is not clearly described, and the description thereof will not be repeated.

  As shown in FIG. 30, the feature of this batch furnace is that the light projecting unit 61a and the light receiving unit 61b of the position detection optical system 61 (see FIG. 2) are arranged such that when the boat 54 is at the wafer loading / unloading position, It is near the upper end. This is advantageous when applied to an apparatus of the type that loads the wafers 1 in order from the top of the boat 54 (the apparatus of FIG. 4 assumes that the wafers 1 are loaded in order from the bottom of the boat 54). . That is, the wafer position inspection can be executed in the first cycle of the wafer load & unload operation cycle with a relatively simple apparatus configuration.

7). Description of apparatus processing flow d of the semiconductor manufacturing method in the present embodiment (mainly FIG. 31)
The following are other modified examples regarding the arrangement of the detection system in the apparatus processing flow a.

  FIG. 31 is a perspective view of the periphery of the wafer boat showing the arrangement of the optical displacement sensor (apparatus process d) in the wafer processing apparatus used in the method of manufacturing a semiconductor device in one embodiment of the present invention. FIG. 30 corresponds to FIG. 4 in the apparatus processing flow a of the semiconductor manufacturing method in the present embodiment. Based on FIG. 31, an apparatus processing flow d of the semiconductor manufacturing method in the present embodiment will be described. Except for the parts described below, it is the same as the description of sections 1 to 4 and sections 5 to 6 except where it is not clearly described, and the description thereof will not be repeated.

  As shown in FIG. 31, the feature of this batch furnace is that the light projecting unit 61a and the light receiving unit 61b of the position detecting optical system 61 (see FIG. 2) are arranged such that when the boat 54 is at the wafer loading / unloading position, It is near both the upper end and the lower end. This is advantageous both when applied to an apparatus that loads the wafers 1 in order from the top of the boat 54 and to an apparatus that loads the wafers 1 from the bottom (see FIG. 4). The apparatus assumes that the wafers 1 are loaded in order from the bottom of the boat 54). That is, the wafer position inspection can be executed in the first cycle of the wafer load & unload operation cycle with a relatively simple apparatus configuration.

8). Description of device process flow of semiconductor manufacturing method in the present embodiment (mainly FIGS. 32 to 46)
FIG. 32 is a device cross-sectional view showing a device process flow (STI silicon nitride CVD step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 33 is a device sectional view showing a device process flow (silicon nitride patterning step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 34 is a device sectional view showing a device process flow (STI trench formation step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 35 is a device sectional view showing a device process flow (STI trench embedding step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 36 is a device sectional view showing a device process flow (STI-CMP step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 37 is a device sectional view showing a device process flow (n-well ion implantation step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 38 is a device cross-sectional view showing a device process flow (p-well ion implantation step) of the method for manufacturing a semiconductor device in one embodiment of the present invention. FIG. 39 is a cross-sectional view of the semiconductor device in one embodiment of the present invention. It is device sectional drawing which shows the device process flow (well diffusion step) of a manufacturing method. FIG. 40 is a device sectional view showing a device process flow (cleaning step before gate oxidation) of the method for manufacturing a semiconductor device in one embodiment of the present invention. FIG. 41 is a device sectional view showing a device process flow (gate oxidation step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 42 is a device sectional view showing a device process flow (gate electrode patterning step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 43 is a device cross-sectional view showing a device process flow (source / drain formation step) of the method for manufacturing a semiconductor device in one embodiment of the present invention. FIG. 44 is a device cross-sectional view showing a device process flow (side wall forming step) of the method for manufacturing a semiconductor device in one embodiment of the present invention. FIG. 45 is a device sectional view showing a device process flow (silicidation step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 46 is a device sectional view showing a device process flow (back end step) in the method for manufacturing a semiconductor device according to one embodiment of the present invention. Based on these, the device process flow of the semiconductor manufacturing method in the present embodiment will be described.

  As shown in FIG. 32, for example, a 300φ wafer 1 made of P-type (may be N-type if necessary) single crystal silicon (may be an epitaxial wafer or SOI wafer) having a specific resistance of about 10 Ωcm (other sizes) The thin silicon oxide film 2 (pad oxide film) having a film thickness of about 10 nm is formed on the main surface (wafer processing step A). Subsequently, a silicon nitride film 3 having a thickness of about 100 nm is deposited on the silicon oxide film 2 by a CVD method (wafer processing step B). Next, as shown in FIG. 33, a photoresist film 4 having an element isolation region opened is formed on the silicon nitride film 3, and the silicon nitride film 3 is patterned using the photoresist film 4 as a mask.

  Next, after removing the photoresist film 4, as shown in FIG. 34, the silicon oxide film 2 and the semiconductor substrate 1 are sequentially etched using the silicon nitride film 3 as a mask, so that the semiconductor substrate 1 has a depth of about 350 nm. Element isolation trenches 5a are formed. Subsequently, for example, a thermal oxidation process is performed at a temperature of about 800 to 1150 degrees Celsius to form a silicon oxide film 6 (liner oxide film) on the surface of the element isolation trench 5a and the like (wafer processing step C).

  Next, as shown in FIG. 35, for example, a film is formed on the semiconductor substrate 1 by a CVD method using ozone and tetraethoxysilane as a reaction gas (in a fine product, the high-density plasma CVD method may be used). A silicon oxide film 7 having a thickness of about 800 nm is deposited. Further, as shown in FIG. 36, the silicon oxide film 7 is polished by the CMP method or the like, and the silicon oxide film 7 is left only in the element isolation trench 5a using the silicon nitride film 3 as a polishing stopper. 5 is formed. Subsequently, for example, a wafer process of about 1000 degrees Celsius is performed to densify the silicon oxide film 7 in the element isolation region 5 (wafer processing step D).

Next, the silicon nitride film 3 is removed by wet etching using hot phosphoric acid (at this time, the liner oxide film is once removed on the surface portion of the semiconductor substrate 1 and a thin sacrificial oxide film is formed by thermal oxidation ( Wafer processing step E) is generally performed). Subsequently, as shown in FIG. 37, an impurity for forming an n-type well is ion-implanted in the semiconductor substrate 1 using the photoresist film 8 having an opening in the formation region of the P-channel MOSFET as a mask. Further, impurities for adjusting the threshold voltage of the P-channel MOSFET are ion-implanted. As the impurity for forming the n-type well, for example, phosphorus is used, the implantation energy is 360 keV, and the dose is about 1.5 × 10 ¹³ / cm ² . Further, for example, phosphorus is used as the threshold voltage adjusting impurity, the implantation energy is 40 keV, and the dose amount is about ² × 10 ¹² / cm ² .

Next, after removing the photoresist film 8, as shown in FIG. 38, an impurity for forming a p-type well in the semiconductor substrate 1 using the photoresist film 9 having an opening in the formation region of the N-channel MOSFET as a mask. Ion implantation. Further, an impurity for adjusting the threshold voltage of the N-channel MOSFET is ion-implanted. For example, boron is used as an impurity for forming the p-type well, and the entrapment energy is about 200 keV and the dose amount is about 1.1 × 10 ¹³ / cm ² . Further, for example, boron fluoride (BF ₂ ) is used as the threshold voltage adjusting impurity, the implantation energy is 40 keV, and the dose amount is about ² × 10 ¹² / cm ² .

  Next, after removing the photoresist film 9, as shown in FIG. 39, the semiconductor substrate 1 (the main surface of the wafer) is stretched and diffused by n-type impurities and p-type impurities (wafer processing) at a temperature of about 900 degrees Celsius, for example. By performing step F), the n-type well 10 is formed in the semiconductor substrate 1 in the formation region of the P-channel MOSFET, and the p-type channel region 12 is formed in the vicinity of the surface thereof. At the same time, a p-type well 11 is formed in the semiconductor substrate 1 in the formation region of the N-channel MOSFET, and an n-type channel region 13 is formed in the vicinity of the surface.

  Next, as shown in FIG. 40, the thin oxide film (liner film or sacrificial oxide film) is removed by wet cleaning before gate oxidation. Thereafter, as shown in FIG. 41, a gate oxide film 14 having a thickness of, for example, about 4 nm is formed by thermal oxidation (wafer processing step G).

  Further, as shown in FIG. 42, a gate electrode 15 is formed on the gate oxide film 14. The gate electrode 15 is formed by depositing, for example, an n-type polycrystalline silicon film, a non-doped polycrystalline silicon film, or an amorphous silicon film on the semiconductor substrate 1 by a CVD method (wafer processing step H), and then masking the photoresist film. It is formed by patterning by dry etching. As the gate electrode, a polysilicon single layer, polycide, polymetal, silicide, refractory metal metal, or the like is generally used. After the formation of the gate electrode 15, thermal oxidation (generally referred to as “re-oxidation process”) may be performed for the purpose of adjusting the shape around the gate electrode (wafer processing process I).

Next, as shown in FIG. 43, a p-type impurity, for example, boron is ion-implanted into the formation region of the P-channel MOSFET from the direction orthogonal to the main surface of the wafer 1 and from the oblique direction. A p ⁻ type semiconductor region 16 and a p type semiconductor region 17 are formed in the n type well 10. Further, an n-type impurity, for example, phosphorus is ion-implanted in a direction perpendicular to the main surface of the wafer 1 and an oblique direction into the formation region of the N-channel MOSFET, and the n ⁻ -type is implanted into the p-type well 11 on both sides of the gate electrode 15. A semiconductor region 18 and an n-type semiconductor region 19 are formed.

  Next, as shown in FIG. 44, the silicon oxide film deposited on the semiconductor substrate 1 by the CVD method (wafer processing step J) is anisotropically dry etched to form side wall spacers on the side walls of the gate electrode 15. 20 is formed. At this time, the gate oxide film 14 above the p-type semiconductor region 17 and the gate oxide film 14 above the n-type semiconductor region 19 are removed. Subsequently, a p-type impurity, for example, boron is ion-implanted in the formation region of the P-channel MOSFET to form the p + -type semiconductor region 21 in the n-type well 10 on both sides of the gate electrode 15. In addition, an n-type impurity, for example, phosphorus is ion-implanted in the formation region of the N-channel MOSFET to form an n + -type semiconductor region 22 in the p-type well 11 on both sides of the gate electrode 15.

  Next, as shown in FIG. 45, a cobalt silicide layer 23 (if necessary, a titanium silicide layer) is formed on each surface of the gate electrode 15 of the P-channel MOSFET and the p + type semiconductor region 21 (source / drain region). Or a nickel silicide layer or the like). The cobalt silicide layer 23 is obtained by performing wafer processing on a cobalt film deposited on the semiconductor substrate 1 by sputtering and reacting it with the surfaces of the semiconductor substrate 1 and the gate electrode 15, and then wet-etching the unreacted cobalt film. It is formed by removing. Through the above steps, a P-channel MOSFET (Qp) and an N-channel MOSFET (Qn) are completed.

  Thereafter, as shown in FIG. 46, contact holes 25 are formed in the silicon oxide film 24 deposited on the semiconductor substrate 1 by plasma CVD. Subsequently, an aluminum alloy film deposited by a sputtering method is patterned on the silicon oxide film 24 through a barrier metal or the like by dry etching to form wirings 29 to 31 (back end process). This is mostly related to the CMOS wafer process. The back-end process may be a damascene process using copper or silver wiring.

  The semiconductor device manufacturing method according to the embodiment of the present invention described above can be suitably applied to, for example, the wafer processing steps A to J described here. It goes without saying that even in other processes, batch processing is applicable under appropriate conditions.

9. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the manufacturing method of the CMOS semiconductor integrated circuit device has been specifically described by way of example. However, the present invention is not limited thereto, and other semiconductor integrated circuit device manufacturing methods, Needless to say, the present invention can also be applied to a device manufacturing method.

  In the above embodiment, the vertical batch type wafer processing apparatus has been specifically described as an example. However, the present invention is not limited to this, and other batch type wafer processing apparatuses (including small batch type) are used. It goes without saying that is also applicable.

It is a block diagram explaining the outline of the manufacturing method of the semiconductor device in one embodiment of this invention. 1 is a front view of a wafer processing apparatus (non-wafer processing period) showing a structure of a wafer processing apparatus used in a semiconductor device manufacturing method according to an embodiment of the present invention; It is a front view of the wafer processing apparatus (wafer processing period) which shows the structure of the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. It is a perspective view of the wafer boat periphery which shows arrangement | positioning (apparatus process a) of the optical displacement sensor in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. It is internal structure explanatory drawing which shows the internal structure of the optical displacement detection part in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. FIG. 6A is a front view showing the structure of the transfer mechanism of the wafer transfer unit in the wafer processing apparatus used in the semiconductor device manufacturing method according to the embodiment of the present invention, and details of the main part of the boat. It is a figure (FIG.6 (b)). It is an apparatus front view which shows the structure of the whole conveyance mechanism of the wafer conveyance part in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. FIG. 6 is a schematic top view showing a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters a transfer wafer storage container to unload a wafer from the transfer wafer storage container); FIG. 8A) and a schematic front view (FIG. 8B). Schematic of a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters a transfer wafer storage container and lifts off a target wafer to unload the wafer from the transfer wafer storage container) It is a front view. FIG. 6 is a schematic front view of a processing sequence (a step in which a tweezer carries out a target wafer from a transfer wafer storage container) of a semiconductor device manufacturing method according to an embodiment of the present invention. It is a model front view of the processing sequence (step which reduces the space | interval of tweezers) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is a model front view of the processing sequence (the step where a tweezer holds a wafer and approaches a boat) of a manufacturing method of a semiconductor device in an embodiment of the invention of this application. Processing sequence of semiconductor device manufacturing method according to one embodiment of the present invention (Tweezer holds a wafer and approaches the wafer mounting position of the boat, and the held wafer and the boat are held in a non-contact state. FIG. 6 is a schematic front view of a step of monitoring a relationship between a wafer and a reference position. It is a schematic front view of the processing sequence (the step where the tweezer holds and lowers the wafer and landes the wafer on the finger of the corresponding slot of the boat) of the manufacturing method of the semiconductor device in one embodiment of the present invention. FIG. 5 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer moves down from the back surface of the wafer after landing the wafer on the finger). It is a model front view of the processing sequence (the step where a tweezer retreats out of a boat) of the manufacturing method of the semiconductor device in one embodiment of the invention of this application. FIG. 6 is a schematic front view of a processing sequence (step in which a boat filled with wafers rises toward a wafer processing chamber) of a semiconductor device manufacturing method according to an embodiment of the present invention. It is a model front view of the process sequence (wafer process step) of the manufacturing method of the semiconductor device in one embodiment of this invention. FIG. 6 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a boat on which a wafer having been subjected to wafer processing is placed descends outside the boat). FIG. 6 is a schematic front view of a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer approaches a boat to carry out a wafer for which wafer processing has been completed). FIG. 6 is a schematic front view of a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer enters a boat in a non-contact manner to carry out a wafer after completion of wafer processing). Processing sequence of semiconductor device manufacturing method according to an embodiment of the present invention (a relationship between a wafer held by a tweezer and a wafer being lifted off from a boat while the wafer processing is completed and the reference position) FIG. FIG. 6 is a schematic front view of a processing sequence of the semiconductor device manufacturing method according to an embodiment of the present invention (a step in which a tweezer carries out a wafer after completion of wafer processing from a boat). It is a model front view of the processing sequence (step which expands the space | interval of tweezers) of the manufacturing method of the semiconductor device in one embodiment of this invention. FIG. 6 is a schematic front view of a processing sequence of a semiconductor device manufacturing method according to an embodiment of the present invention (step of approaching an original slot of a wafer hoop even when a wafer is held by a tweezer). . Processing sequence of semiconductor device manufacturing method according to an embodiment of the present invention (step in which a tweezer holds a wafer after completion of wafer processing and enters the original slot of the original wafer hoop in a non-contact state) It is a model front view. Processing sequence of manufacturing method of semiconductor device according to one embodiment of the present invention (After the wafer processing is completed, the tweezer holds the wafer down and places it on the original shelf of the original wafer hoop. It is a model front view of a step to descend. It is a perspective view of the wafer boat periphery which shows arrangement | positioning (apparatus process b) of the optical displacement sensor in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. Processing sequence of semiconductor device manufacturing method (apparatus process b) according to an embodiment of the present invention (with tweezers holding wafers and approaching the wafer mounting position of the boat, the wafer being held and the boat are in non-contact state FIG. 9 is a schematic front view of a step of monitoring a relationship between a held wafer and a reference position. It is a perspective view of the wafer boat periphery which shows arrangement | positioning (apparatus process c) of the optical displacement sensor in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. It is a perspective view of the wafer boat periphery which shows arrangement | positioning (apparatus process d) of the optical displacement sensor in the wafer processing apparatus used for the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (STI silicon nitride CVD step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (silicon nitride patterning step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (STI trench formation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (STI trench embedding step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (STI-CMP step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (n well ion implantation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (p well ion implantation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (well diffusion step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (cleaning step before gate oxidation) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (gate oxidation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (gate electrode patterning step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (source / drain formation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (side wall formation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (silicidation step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is device sectional drawing which shows the device process flow (back end step) of the manufacturing method of the semiconductor device in one embodiment of this invention. It is the front view (FIG. 47 (a)) and bottom view (FIG. 47 (b)) of the principal part of the optical detection part explaining the detail of the optical monitoring method in the apparatus processing flow of the manufacturing method of the semiconductor in this Embodiment. It is light intensity distribution explanatory drawing which illustrates the detection light intensity distribution in the optical monitor method in the apparatus processing flow of the manufacturing method of the semiconductor in this Embodiment. It is a conceptual diagram which shows the fundamental view of the position or pitch shift | offset | difference sampling in the apparatus processing flow of the manufacturing method of the semiconductor in this Embodiment. It is a block flowchart which shows the whole flow of the apparatus processing flow of the semiconductor manufacturing method in this Embodiment.

Explanation of symbols

1 Wafer (semiconductor substrate)
1a Main surface of wafer (front surface or device surface)
51 Vertical wafer processing equipment (Vertical batch type wafer processing furnace)
54 Wafer processing boat (wafer holder for wafer processing)
56 Wafer Processing Chamber 65 Wafer Transfer Robot 66 Wafer Tweezer (Wafer Adsorption Arm)
162 Wafer processing 181 Wafer loading operation cycle 185 Main axis (in the longitudinal direction of the wafer transfer robot) 191 Wafer unloading operation cycle Hr Reference surface (on the wafer processing boat) Reference surface (upper surface of dummy wafer)

Claims (16)

A semiconductor device manufacturing method including the following steps:
(A) In a batch type vertical wafer processing apparatus that batch-processes a large number of wafers to be processed, a plurality of wafers to be processed among the wafers to be processed have a plurality of wafer tweezers. Each main surface of the multiple wafers to be processed along the main axis is held on a wafer processing boat held by a robot or another wafer transfer robot having a plurality of wafer tweezers, and the main axis of the wafer processing boat Transferring a large number of wafers to be processed onto the wafer processing boat by repeating a plurality of wafer loading operation cycles in which the wafers are loaded so as to be substantially orthogonal to each other;
(B) inserting the wafer processing boat containing the wafers to be processed into a wafer processing chamber;
(C) performing wafer processing on the multiple processing wafers in the wafer processing chamber in a state where the main shaft of the wafer processing boat is substantially vertical;
(D) discharging the wafer processing boat containing the wafers to be processed that have undergone the wafer processing from the wafer processing chamber;
(E) A plurality of wafers to be processed among the plurality of wafers to be processed on the wafer processing boat discharged from the wafer processing chamber are held by the wafer transfer robot or the other wafer transfer robots, and the wafers A step of carrying out the plurality of wafers to be processed on the wafer processing boat out of the wafer processing boat by repeating a plurality of wafer unloading operation cycles to be carried out of the processing boat;
Here, at least one of the plurality of wafer unload operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e) includes the following sub-steps: :
(X1) a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and a reference plane orthogonal to the main axis on the wafer processing boat in a state where a plurality of wafers to be processed are held Detecting a relative distance from at least one of a plurality of wafers to be processed. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e). One further includes the following substeps:
(X2) Based on the result of the sub-process (x1), when necessary, the wafer processing boat, a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and the multiple objects A step of automatically performing avoidance processing so as to avoid occurrence of undesired contact between any two of the processing wafers. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e). One further includes the following substeps:
(X2) A step of automatically stopping the wafer transfer robot or the other wafer transfer robot when necessary based on the result of the substep (x1). 2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e). One further includes the following substeps:
(X2) A step of generating an alarm when necessary based on the result of the substep (x1). 2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of the plurality of wafer load operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e). One further includes the following substeps:
(X2) Based on the result of the sub-process (x1), when necessary, the wafer processing boat, a plurality of wafer tweezers of the wafer transfer robot or the other wafer transfer robot, and the multiple objects Automatically correcting the operating conditions of the wafer transfer robot or the other wafer transfer robot so as to avoid the occurrence of undesired contact between any two of the processed wafers. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the reference plane is set on a dummy wafer on the wafer processing boat. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the detection of the relative distance is executed in a first cycle of the plurality of wafer load operation cycles. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the relative distance is detected optically. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the relative distance is detected for at least two or more of a plurality of wafers to be processed that are held. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the relative distance is detected at two or more different points on the wafer in the extending direction of a wafer tweezer holding the wafer to be detected. Execute. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the relative distance is detected by at least one of the plurality of wafer load operation cycles and at least one of the plurality of wafer unload operation cycles. Done in 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the detection of the relative distance is executed in a cycle other than a first cycle among the plurality of wafer load operation cycles. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the reference plane is set on one of the plurality of wafers to be processed on the wafer processing boat. 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the detection of the relative distance is executed in two or more cycles among the plurality of wafer loading operation cycles. 2. The method of manufacturing a semiconductor device according to claim 1 , further comprising detecting a pitch between the plurality of wafers to be processed being held in the sub-process (x1).   A semiconductor device manufacturing method including the following steps:
(A) In a batch processing type vertical wafer processing apparatus that batch-processes a large number of wafers to be processed, a plurality of wafers to be processed among the wafers to be processed are transferred to a wafer transfer robot or another wafer transfer robot. A plurality of times of wafer loading on the wafer processing boat so that the main surfaces of the wafers to be processed are substantially perpendicular to the main shaft of the wafer processing boat along the main axis of the wafer processing boat. Transferring the plurality of wafers to be processed onto the wafer processing boat by repeating an operation cycle;
(B) inserting the wafer processing boat containing the wafers to be processed into a wafer processing chamber;
(C) performing a wafer process on the multiple wafers to be processed in the wafer processing chamber;
(D) discharging the wafer processing boat containing the wafers to be processed that have undergone the wafer processing from the wafer processing chamber;
(E) A plurality of wafers to be processed among the plurality of wafers to be processed on the wafer processing boat discharged from the wafer processing chamber are held by the wafer transfer robot or the other wafer transfer robots, and the wafers A step of carrying out the plurality of wafers to be processed on the wafer processing boat out of the wafer processing boat by repeating a plurality of wafer unloading operation cycles to be carried out of the processing boat;
  Here, at least one of the plurality of wafer unload operation cycles in the step (a) or at least one of the plurality of wafer unload operation cycles in the step (e) includes the following sub-steps: :
(X1) In a state where a plurality of wafers to be processed are held by the wafer transfer robot or the other wafer transfer robot, a reference position on the wafer processing boat and a plurality of wafers to be processed are held. Detecting a relative distance to at least one wafer;

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