JP4904922B2 - Semiconductor substrate manufacturing method and semiconductor substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate.

In recent years, semiconductor devices have been required to be thin in order to reduce loss. In order to reduce the thickness of the semiconductor element, it is necessary to reduce the thickness of the semiconductor substrate. However, when the semiconductor substrate is made thinner, the mechanical strength is lowered, and there is a problem that it is easily broken during handling.
As a technique for solving this problem, the technique of Patent Document 1 has been proposed. In the technique of Patent Document 1, a semiconductor substrate that is thicker than a semiconductor element to be manufactured is used, and a part of the semiconductor substrate (a portion where a semiconductor element is formed) is thinned by etching or polishing. According to the semiconductor substrate manufactured as described above, the semiconductor element is formed in the thinned portion, so that the thinned semiconductor element can be manufactured. On the other hand, the strength of the semiconductor substrate is ensured by the thick portion, so that it is difficult to break.

JP 2002-299196 A

In the technique of Patent Document 1, the semiconductor substrate is thinned by etching (that is, wet etching or dry etching) or mechanical polishing.
When thinning by wet etching is generally isotropic etching, it is difficult to accurately form the boundary between the thinned portion and the thickened portion (that is, the shape of the thinned portion). . Even in anisotropic etching, since the etching direction is determined by the crystal direction, it is difficult to accurately control the etching direction. For this reason, when thinning by wet etching, it is difficult to accurately form the shape of the thinned portion. If the shape of the thinned portion cannot be formed with high accuracy, many semiconductor elements cannot be manufactured from one semiconductor substrate, and there is a problem that productivity is lowered.
On the other hand, when attempting to thin by dry etching, unlike wet etching, the shape of the thinned portion can be formed with high accuracy, but there is a problem that the etching rate is slow. In particular, when many semiconductor elements are manufactured from a semiconductor substrate, many regions of the semiconductor substrate must be thinned. For this reason, there is a problem that etching takes a very long time and productivity is lowered.
Further, when thinning by mechanical polishing, polishing is performed by bringing a rotating polishing plate into contact with the substrate body. For this reason, if an attempt is made to process the shape of the thinned portion with high accuracy, a polishing plate having a small head area must be used, which requires a long time for polishing and reduces productivity. On the other hand, when a polishing plate having a large head area is used to shorten the polishing time, the shape of the thinned portion cannot be formed with high precision, and it is difficult to increase productivity.
As described above, according to the conventional technique, it has been impossible to manufacture a semiconductor substrate which has good productivity and has both mechanical strength and thickness reduction.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor substrate which has good productivity and has both mechanical strength and thickness reduction.

The first semiconductor substrate manufacturing method of the present invention includes a step of forming a trench on the back surface of the substrate body, and a reinforcing material having a higher elastic coefficient and / or higher internal stress than the substrate body only in the formed trench. Arranging.
According to such a semiconductor substrate manufacturing method, a semiconductor substrate in which a reinforcing material is disposed in a trench formed on the back surface of the substrate body can be manufactured. The reinforcing material in the trench has a higher elastic modulus and / or higher internal stress than the substrate body, and has high mechanical strength. Since the substrate body is supported by the reinforcing material, the mechanical strength of the semiconductor substrate is also increased. Therefore, according to this semiconductor substrate manufacturing method, a semiconductor substrate having a small thickness and a high mechanical strength can be manufactured. Further, in this semiconductor substrate manufacturing method, it is not necessary to scrape a large amount of the substrate body by etching or the like, and it is only necessary to form a trench on the back surface of the substrate body, so that productivity can be increased.

In the semiconductor substrate manufacturing method described above, the trench is preferably formed in a region of the substrate body where the semiconductor element is not formed.
When the trench is formed in this way, since the reinforcing material is not included in the semiconductor element, the quality of the semiconductor element manufactured from the semiconductor substrate is stabilized.

In the semiconductor substrate manufacturing method described above, the trench is preferably formed by dry etching.
According to such a method, the trench can be formed with high accuracy. Therefore, the reinforcing material can be arranged with high accuracy, and a large number of semiconductor elements can be manufactured from one semiconductor substrate.

In addition, the present invention provides a second method for manufacturing a semiconductor substrate that has good productivity and has both mechanical strength and thickness reduction. In this semiconductor substrate manufacturing method, a step of forming a trench in a region of the back surface of the substrate body where no semiconductor element is formed, a step of disposing a reinforcing material only in the formed trench, and a disposing material in the trench After that, at least a region where the semiconductor element is formed on the back surface of the substrate body is wet-etched. In the wet etching step, an etching solution that hardly dissolves the reinforcing material is used.
According to this method for manufacturing a semiconductor substrate, a region for forming a semiconductor element on the back surface of the substrate body is wet-etched, so that a thinner semiconductor element can be manufactured. In addition, since wet etching is used, a wide region of the substrate body can be etched in a short time. Therefore, it is also suppressed that productivity is lowered. Furthermore, since an etching solution that hardly dissolves the reinforcing material is used, only a portion other than the reinforcing material (that is, a region where a semiconductor element is formed) can be etched. Thereby, after the wet etching process, the reinforcing material protrudes from the back surface of the semiconductor substrate. Since the substrate body is supported by the reinforcing material, the mechanical strength of the semiconductor substrate can be increased.

The present invention also provides a new semiconductor substrate that can solve the above-described problems.
This semiconductor substrate has a substrate body in which a trench is formed on the back surface, and a reinforcing material disposed in the trench. The reinforcing material has a higher elastic coefficient and / or higher internal stress than the substrate body, and no reinforcing material is disposed in a region of the back surface of the substrate body where no trench is formed.
This semiconductor substrate also has high mechanical strength even when the thickness of the substrate body is thin because the substrate body is supported by the reinforcing material disposed along the trench.

Furthermore, this invention provides the semiconductor substrate of the other form which can solve the above-mentioned subject.
The semiconductor substrate has a substrate body and a beam portion that is erected on the back surface of the substrate body and is formed of a material different from that of the substrate body.
This semiconductor substrate has a high mechanical strength even when the thickness of the substrate body is thin because the substrate body is supported by a beam portion erected on the back surface of the substrate body. Moreover, this semiconductor substrate can be suitably manufactured by the above-described second semiconductor substrate manufacturing method.

The main features of the embodiments described in detail below are listed first.
First, the features of the semiconductor substrate manufacturing method of the first embodiment will be listed.
(Mode 1) The semiconductor substrate manufacturing method includes a step of forming a trench on the back surface of the silicon wafer body, and a step of placing (filling) the reinforcing material only in the formed trench.
(Embodiment 2) As a reinforcing material, a material such as SiO ₂ , SiO _x C _y , SiC, Si ₃ N ₄ or the like having high adhesion to the silicon wafer body and high selectivity with the silicon wafer body during wet etching is used. .
(Mode 3) The trench is formed in a region of the silicon wafer body where no semiconductor element is formed.
(Mode 4) The trench is formed by performing dry etching on the back surface of the silicon wafer by RIE (reactive ion etching).
(Mode 5) The reinforcing material is filled (applied) into the trench by a spin coating method, a scan coating method, a printing method, or the like.
(Mode 6) After filling the trench with a reinforcing material, at least a region of the back surface of the silicon wafer body where the semiconductor element is to be formed is wet-etched.
(Mode 7) For wet etching, an etching solution that hardly dissolves a reinforcing material such as an alkaline aqueous solution of KOH or TMAH is used.
(Mode 8) In wet etching, a region where a semiconductor element is to be formed in the back surface of the silicon wafer body is etched to a position shallower than the depth of the trench.

Next, features of the semiconductor substrate manufacturing method of the second embodiment will be listed.
(Mode 9) As a reinforcing material, a material having a higher Young's modulus and / or a higher internal stress than a silicon wafer body such as high-concentration B-doped polysilicon, SiC, Al ₂ O ₃ , AlN, or CVD diamond is used.
(Mode 10) The reinforcing material is filled (applied) to a position shallower than the depth of the trench, and the filling material is further filled on the filled reinforcing material.
(Embodiment 11) As the filler, a material having high adhesion to the silicon wafer body such as SiO ₂ , SiO _x C _y , SiC, Si ₃ N ₄ is used.

  Preferred embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a semiconductor substrate 40 of the first embodiment of the present invention. As shown in the figure, the semiconductor substrate 40 is a substantially circular substrate, and is composed of a silicon wafer body 10 and a lattice-shaped reinforcing material 34.

  The silicon wafer body 10 is a wafer made of a single crystal of silicon. The upper surface 10a of the silicon wafer body 10 is formed in a planar shape. A plurality of circuit portions 20 are formed in a matrix at predetermined intervals on the upper surface 10a. On the lower surface 10b of the silicon wafer body 10, a region E on the lower surface side of each circuit portion 20 is formed in a concave shape. For example, the thickness of the silicon wafer body 10 can be about 150 μm in the concave portion E, and can be about 700 μm in the portion other than the concave portion E (region D). As a result, a portion corresponding to each circuit portion 20 of the silicon wafer body 10 is a semiconductor element 38 having a thickness of the concave portion E (for example, about 150 μm). A region A around each semiconductor element 38 is a dicing region. The semiconductor element 38 is cut out from the semiconductor substrate 40 by later cutting the region A by dicing. In the concave portion E, the trenches 30 are formed in a lattice shape along the center line of the region A. The width of the trench 30 can be about 100 μm, for example. A reinforcing material 34 is disposed in the trench 30.

The material of the reinforcing member 34 is SiO _2. The reinforcing material 34 is formed in a lattice shape so as to correspond to the trench 30. Therefore, the width of the reinforcing member 34 is substantially the same as that of the trench 30 (for example, about 100 μm). The base end portion of the reinforcing member 34 is coupled to the silicon wafer main body 10 in the trench 30.

  Next, a method for manufacturing the semiconductor substrate 40 will be described with reference to the flowchart shown in FIG. In this semiconductor substrate manufacturing method, the semiconductor substrate 40 is manufactured from the substantially circular silicon wafer main body 10 having a uniform thickness (for example, about 700 μm) shown in FIG.

  In step S2, a plurality of circuit portions 20 are formed on the upper surface 10a of the silicon wafer body 10 using techniques such as photolithography, etching, diffusion / ion implantation, and film growth. As shown in FIGS. 5 and 6, the circuit unit 20 is formed in a matrix form arranged at predetermined intervals. 5 and 6, the region C of the silicon wafer main body 10 is a region corresponding to the circuit unit 20, and is a region that will later become the semiconductor element 38. Further, the area A of the silicon wafer body 10 is an area provided around each area C. As described above, the region A is a region that is scraped when the semiconductor element 38 is cut out and does not become a semiconductor element. Since the circuit unit 20 is formed in a matrix, the region A is a lattice-like region. Center line B is the center line of region A. A region D outside the outermost peripheral portion of the region A is a region that is discarded after the semiconductor element 38 is cut out. Since the manufacturing method of the circuit unit 20 is a conventionally known technique, a detailed description thereof is omitted.

  After each circuit unit 20 is formed on the silicon wafer body 10, a resist 22 is formed on the lower surface 10b of the silicon wafer body 10 (step S4). That is, first, a photoresist solution is applied to the lower surface 10b of the silicon wafer body 10 by spin coating. As a result, as shown in FIG. 7, a resist 22 is formed on the entire lower surface 10b. After the resist 22 is formed on the entire lower surface 10b, the resist 22 near the center line B is irradiated with ultraviolet rays by mask exposure. As a result, the chemical composition of the resist 22 in the vicinity of the center line B changes. Thereafter, a developing solution is sprayed on the entire resist 22 to remove the resist 22 near the center line B. As a result, as shown in FIG. 8, openings 24 formed in a lattice shape along the center line B are obtained. The opening 24 is formed so that the width is the same as the width of the trench 30 (for example, around 100 μm).

  After the resist 22 and the opening 24 are formed, the trench 30 is formed in the lower surface 10b of the silicon wafer body 10 (step S6). The trench 30 is formed by dry etching the silicon wafer body 10 from the lower surface 10b side by a reactive ion etching method (RIE method). When dry etching is performed from the lower surface 10 b side, radicals and ions collide with the lower surface 10 b of the silicon wafer body 10 in the opening 24. Thereby, the silicon wafer main body 10 is etched from the lower surface 10b side. The radicals and ions also collide with the resist 22, but the resist 22 hardly reacts with the radicals and ions, so that it is hardly etched. Therefore, only the silicon wafer body 10 in the opening 24 is etched. Thus, a trench 30 having a predetermined depth (for example, a little over 550 μm) is formed in the lower surface 10b of the silicon wafer body 10 (see FIG. 9). In dry etching by the RIE method, etching proceeds in a direction substantially perpendicular to the etching surface. Accordingly, a trench 30 having a substantially vertical wall surface is formed on the lower surface 10b. Further, since the openings 24 are formed in a lattice shape along the center line B, the trenches 30 are also formed in a lattice shape along the center line B. Further, since the trench 30 has a wall surface substantially perpendicular to the lower surface 10b, the width of the trench 30 is the same as the width of the opening 24 of the resist 22 (for example, about 100 μm).

  After the trench 30 is formed on the lower surface 10b, the resist 22 is removed by oxygen plasma treatment as shown in FIG. 10 (step S8).

When the resist 22 is removed, as shown in FIG. 11, a reinforcing material 34 of SiO ₂ is disposed in the trench 30 (step S10). That is, silsesquioxane is filled in the trench 30 with a dispenser, and then the silicon wafer body 10 is heat treated together. As a result, the reinforcing material 34 is disposed throughout the trench 30. Since the trenches 30 are formed in a lattice shape, the reinforcing material 34 is also arranged in a lattice shape. The width of the reinforcing material 34 is substantially the same width (for example, about 100 μm) as that of the trench 30, and the height of the reinforcing material 34 is substantially the same as that of the trench 30 (for example, a little over 550 μm). Moreover, since the wall surface of the trench 30 is substantially perpendicular to the silicon wafer body 10, the wall surface of the reinforcing member 34 is also substantially perpendicular.

  When the reinforcing material 34 is formed in the trench 30, a polyimide material etching protection tape 36 is attached to the surface of the silicon wafer body 10 (step S 12). As shown in FIG. 12, the etching protection tape 36 is affixed to the region D and the end surface of the outermost reinforcing member 34 in the lower surface 10b of the silicon wafer body 10 without any gap. Further, the silicon wafer body 10 is also affixed to the upper surface 10a and the side surface 10c without any gap.

After the etching protection tape 36 is attached, the silicon wafer body 10 is immersed in an etching solution together with the etching protection tape 36 and the reinforcing material 34, and the silicon wafer body 10 is etched (step S14). As the etching solution, an alkaline aqueous solution such as KOH or TMAH is used. These etching solutions dissolve the silicon wafer body 10 (ie, silicon) well, but hardly dissolve the reinforcing material 34 (ie, SiO ₂ ).
When the silicon wafer main body 10 is immersed in the etching solution, the lower surface 10b of the silicon wafer main body 10 and the reinforcing material 34 in a region where the etching protection tape 36 is not attached come into contact with the etching solution. Since the silicon wafer main body 10 dissolves well in the etching solution, it is etched from the lower surface 10b side. On the other hand, since the reinforcing material 34 is hardly dissolved in the etching solution, it is hardly etched. In normal wet etching, etching proceeds isotropically. However, in step S14, as described above, the reinforcing material 34 is not etched, and thus etching does not proceed in the surface direction of the silicon wafer body 10. Therefore, the etching of the silicon wafer body 10 proceeds in the thickness direction. By immersing the silicon wafer body 10 in an etching solution for a predetermined time, the silicon wafer body 10 is etched by a depth slightly shallower than the trench 30 (for example, about 550 μm) from the lower surface 10b side. As a result, as shown in FIG. 13, the thickness of the silicon wafer body 10 in the region C is reduced to a predetermined thickness (for example, about 150 μm). As a result, the silicon wafer main body 10 in the region C becomes a semiconductor element 38 having a predetermined thickness (for example, 150 μm). Further, since the height of the reinforcing material 34 is substantially the same depth as the trench 30 (for example, a little over 550 μm), after the wet etching, the reinforcing material 34 is bonded to the silicon wafer body 10 only at the base end portion, It will be in the state which protruded from the lower surface 10b of the silicon wafer main body 10. FIG.

  After the silicon wafer body 10 is wet etched, the etching protection tape 36 is peeled off from the silicon wafer body 10 (step S16). Thereby, the semiconductor substrate 40 shown in FIGS. 1 and 2 is completed.

In the semiconductor substrate 40 manufactured by such a semiconductor substrate manufacturing method, the reinforcing material 34 is erected in a beam shape on the back surface of the silicon wafer body 10. The reinforcing material 34 has good adhesion to the silicon wafer body 10 (that is, silicon). Accordingly, the silicon wafer body 10 is supported by the reinforcing material 34, and the mechanical strength of the semiconductor substrate 40 is increased. As a result, even if the region E of the silicon wafer body 10 is very thin, the semiconductor substrate 40 is difficult to break, and handling during manufacture becomes easy.
In this semiconductor substrate manufacturing method, the trench 30 is formed by dry etching. However, since the area for forming the trench 30 is very small in the lower surface 10b, the etching does not require a long time. Moreover, since it is dry etching, the trench 30 can be formed precisely. In this semiconductor substrate manufacturing method, the lower surface 10b of the silicon wafer body 10 is wet-etched, but the etching proceeds in the thickness direction of the silicon wafer body 10 because the reinforcing material 34 is formed. Therefore, the lower surface 10b of the silicon wafer body 10 can be precisely etched. Moreover, since it is wet etching, even if an etching area is large, etching does not require a long time. That is, this semiconductor substrate manufacturing method can manufacture the semiconductor substrate 40 precisely with high productivity.
Further, as described above, in this semiconductor substrate manufacturing method, the trench 30 is formed by dry etching. Since dry etching can be performed with precision, a very narrow trench 30 can be formed. That is, the very narrow reinforcing material 34 can be formed.
Further, in this semiconductor substrate manufacturing method, the trench 30 and the reinforcing material 34 are disposed in the region A of the silicon wafer body 10 where the semiconductor element 38 is not formed. Since the trench 30 and the reinforcing material 34 are thus arranged, the reinforcing material 34 is not included in the semiconductor element 38, and the quality of the semiconductor element 38 is stabilized. Further, as described above, the width of the trench 30 and the reinforcing material 34 is very narrow, and the width of the region A can be very thin. Therefore, a large number of semiconductor elements 38 can be formed on the semiconductor substrate 40. it can.
Further, since the SiO ₂ that is the reinforcing material 34 has good adhesion to the silicon wafer body 10, the silicon wafer body 10 is more preferably reinforced.

Next, a semiconductor substrate according to a second embodiment of the present invention will be described. As shown in FIG. 15, the semiconductor substrate 140 of the second embodiment is composed of a silicon wafer main body 110, a reinforcing material 134, and a filler 142. Unlike the semiconductor substrate 40 of the first embodiment, the semiconductor substrate 140 of the second embodiment has a lower surface 110b formed in a planar shape.
The silicon wafer body 110 is a wafer made of silicon single crystal. The upper surface 110a of the silicon wafer body 110 is formed in a planar shape. A plurality of circuit portions 20 are formed on the upper surface 110a, similarly to the silicon wafer body 10 of the first embodiment. The lower surface 110b of the silicon wafer body 110 is formed in a planar shape. The thickness of the silicon wafer body 110 can be about 150 μm, for example. That is, the silicon wafer body 110 corresponding to each circuit unit 20 is a semiconductor element 38 having a predetermined thickness (for example, about 150 μm). A region A around each semiconductor element 38 is a dicing region. A trench 130 is formed along the center line of the region A on the lower surface 110 b of the silicon wafer main body 110. A SiO ₂ barrier film 144 is formed on the bottom and wall surfaces of the trench 130. A reinforcing material 134 is disposed on the bottom side in the trench 130. A filler 142 is disposed on the reinforcing material 134 in the trench 130.
The material of the reinforcing material 134 is high-concentration B-doped polysilicon. High-concentration B-doped polysilicon has higher internal stress than the silicon wafer main body 110 and SiO ₂ and has high mechanical strength. The reinforcing material 134 is disposed on the bottom side of the trench 130.
The material of the filler 142 is SiO _2. The filler 142 is formed on the reinforcing material 134 in the trench 130. The end surface of the filler 142 is formed so as to have substantially the same height as the lower surface 110 b of the silicon wafer main body 110.

  Next, a method for manufacturing the semiconductor substrate 140 will be described with reference to the flowchart shown in FIG. In the semiconductor substrate manufacturing method of this embodiment, the semiconductor substrate 140 is manufactured from a substantially circular silicon wafer body 110 having a uniform thickness (for example, about 150 μm) shown in FIG. In the silicon wafer main body 110 of FIG. 16, the region C is a region that will later become the semiconductor element 38, and the region A is a dicing region that is scraped off when the semiconductor element 38 is cut out.

  In steps S24 to S28, the trench 130 is formed along the center line of the region A on the lower surface 110b of the silicon wafer body 110 by the same method as the steps S4 to S8 of the manufacturing method of the first embodiment. FIG. 17 shows the silicon wafer main body 110 in which the trench 130 is formed.

After the trench 130 is formed in the silicon wafer main body 110, the silicon wafer main body 110 is thermally oxidized. As a result, as shown in FIG. 18, the surface of the silicon wafer body 110 is oxidized, and a barrier film 144 of SiO ₂ is formed (step S30).

  After the barrier film 144 is formed on the surface of the silicon wafer main body 110, a high concentration B-doped polysilicon layer 146 is grown on the lower surface 110b and the bottom surface of the trench 130 by CVD as shown in FIG. At this time, since the barrier film 144 is formed on the surface of the silicon wafer body 110, the high-concentration B-doped polysilicon component does not diffuse into the silicon wafer body 110. After the high-concentration B-doped polysilicon layer 146 is grown to a predetermined thickness, the grown high-concentration B-doped polysilicon layer 146 is subjected to chemical dry etching. Since chemical dry etching is isotropic etching, the high-concentration B-doped polysilicon layer 146 on the lower surface 110 b is etched at a higher speed than the high-concentration B-doped polysilicon layer 146 in the trench 130. The etching time of the chemical dry etching is adjusted so that the high-concentration B-doped polysilicon layer 146 on the lower surface 110 b is removed and the high-concentration B-doped polysilicon layer 146 having a predetermined thickness remains in the trench 130. The Thereby, as shown in FIG. 20, the reinforcing material 134 of high-concentration B-doped polysilicon is disposed in the trench 130 (step S34).

  When the reinforcing material 134 is arranged, as shown in FIG. 21, a filler 142 is formed on the reinforcing material 134 in the trench 130 (step S36). The filler 142 is disposed by heat-treating the silsesquioxane into the trench 130 with a dispenser. After the filler 142 is disposed, the lower surface 110b of the silicon wafer main body 110 is polished or the like, so that the end surface of the filler 142 becomes substantially the same height as the lower surface 110b of the silicon wafer main body 110.

  When the filler 142 is formed, as shown in FIG. 22, the barrier film 144 is removed by etching (step S38).

  After removing the barrier film 144, a plurality of circuit portions 20 are formed on the upper surface 110a of the silicon wafer main body 110 using techniques such as photolithography, etching, diffusion / ion implantation, and film growth (step S40). The circuit unit 20 is formed in the region C as shown in FIG. As a result, the silicon wafer body 110 in the region C becomes the semiconductor element 38.

In the semiconductor substrate 140 manufactured by such a semiconductor substrate manufacturing method, the reinforcing material 134 is disposed in the trench 130 formed on the back surface of the silicon wafer body 110. The reinforcing material 134 has high internal stress and has higher mechanical strength than silicon and SiO ₂ . In addition, a SiO ₂ filler 142 is formed on the reinforcing material 134. Since the filler 142 has good adhesion to the silicon wafer main body 110 (that is, silicon), the reinforcing material 134 is suitably fixed in the trench 130 by the filler 142. As described above, the silicon wafer main body 110 is supported by the reinforcing material 134 and the filling material 142 formed in the trench 130. This increases the mechanical strength of the semiconductor substrate 140 and facilitates handling during manufacture.

As described above, according to the manufacturing method of the second embodiment, the semiconductor substrate 140 capable of manufacturing a large number of thin semiconductor elements 38 can be manufactured.
Further, the semiconductor substrate 140 manufactured in this way has an upper surface 110a and a lower surface 110b formed in a planar shape. Therefore, it is not necessary to use a special apparatus for transporting the semiconductor substrate 140, and the semiconductor substrate 140 can be manufactured by a general semiconductor substrate manufacturing apparatus. Thereby, it is possible to manufacture the semiconductor substrate 140 with high productivity.
Moreover, according to this manufacturing method, it is not necessary to thin the silicon wafer main body 110. Accordingly, the time required for manufacturing the semiconductor substrate 140 is shortened, the material utilization efficiency is increased, and the manufacturing cost can be reduced.
Further, according to the manufacturing method of the second embodiment, the barrier film 144 is formed on the surface of the silicon wafer main body 110 in the trench 130 in step S30. Therefore, when the reinforcing material 134 is disposed in the trench 130 in step S34, a part of the components of the reinforcing material 134 is prevented from diffusing into the silicon wafer main body 110 and the characteristics of the silicon wafer main body 110 are prevented from changing. The

FIG. 23 shows the result of simulating the mechanical strength of the semiconductor substrate 40 of the first example and the semiconductor substrate 140 of the second example. More specifically, a simulation result when a predetermined acceleration is applied to the semiconductor substrate in a state where both ends of the semiconductor substrate are supported is shown. In FIG. 23, the horizontal axis indicates the position of the semiconductor substrate in the axial direction supporting the semiconductor substrate, and the vertical axis indicates the amount of displacement of the semiconductor substrate at that position (the amount of displacement in the direction perpendicular to the axial direction). Is shown.
Reference numeral 40a in the figure is a simulation result of the semiconductor substrate 40. The thickness of the semiconductor element 38 (ie, the thickness of the region E of the silicon wafer body 10) is 160 μm, and the thickness of the semiconductor substrate 40 (ie, the silicon wafer body). 10) (thickness from the upper surface 10a to the lower end surface of the reinforcing member 34) was set to 775 μm and the width of the reinforcing member 34 was set to 120 μm. Reference numeral 140a denotes a simulation result of the semiconductor substrate 140. The thickness of the semiconductor substrate 140 is 160 μm, the height of the reinforcing material 134 and the filler 142 (that is, the depth of the trench 130) is 80 μm, and the width of the reinforcing material 134. Was set to 120 μm. Further, for comparison with the semiconductor substrates 40 and 140, simulation results of a silicon wafer (for example, a silicon wafer as shown in FIG. 16) in which no reinforcing material is disposed and no trench is formed are shown. 240a). In the silicon wafer simulation, the thickness of the silicon wafer was set to 160 μm.
As shown in FIG. 23, in the silicon wafer of the comparative example, when acceleration was applied, the silicon wafer was greatly warped, and the central portion of the silicon wafer was displaced by 17.0 mm. On the other hand, in the semiconductor substrate 140, the displacement at the center is 11.7 mm, and it can be seen that the mechanical strength of the semiconductor substrate 140 is improved by the reinforcing material 134 and the filler 142. Further, in the semiconductor substrate 40, almost no warp occurred, and the displacement at the center was 0.44 mm. From this, it was found that the mechanical strength of the semiconductor substrate 40 was greatly improved by being reinforced by the reinforcing material 34.

In the first and second embodiments described above, the trench is formed by dry etching using the RIE method, but etching may be performed by other methods. For example, the trench can be suitably formed also by wet etching using the anisotropy of the silicon wafer body.
In the second embodiment described above, the reinforcing material is formed of high-concentration B-doped polysilicon, but other materials can be used as the reinforcing material. For example, a material having a higher Young's modulus and / or higher internal stress than the silicon wafer body such as SiC, Al ₂ O ₃ , AlN, and CVD diamond can be used as the reinforcing material.
In the second embodiment described above, the SiO ₂ barrier film is formed in the trench by thermal oxidation, and then the reinforcing material is disposed in the trench. However, the barrier film may be formed by a method such as CVD. . The barrier film is not limited to SiO ₂ and can be formed of various substances having high barrier properties such as Si ₃ N ₄ . Further, when the reinforcing material is formed of a material whose components do not diffuse into the silicon wafer body, the barrier film may not be formed.
Further, in the manufacturing methods of the first and second embodiments described above, a photoresist solution is applied by spin coating, then irradiated with ultraviolet rays, and a developer is applied to form a resist having a predetermined shape in silicon. Although formed on the wafer body, various methods can be used according to the position and purpose of forming the resist. For example, the resist may be formed by inkjet printing, screen printing, scan coating, or the like.
Moreover, in the manufacturing method of the first embodiment and the second embodiment described above, an aqueous solution was applied in the trench by a dispenser, and then heat treatment was performed, and then the SiO ₂ reinforcing material and filler were disposed in the trench. Various methods can be used depending on the position and purpose of arranging the reinforcing material or filler. For example, the reinforcing material or the filler may be formed by applying an aqueous solution by inkjet printing, screen printing, scan coating, or the like and then performing a heat treatment.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

FIG. 3 is a plan view of the semiconductor substrate 40 as viewed from the lower surface side. II-II sectional view taken on the line of the semiconductor substrate 40 of FIG. 4 is a flowchart showing manufacturing steps of the semiconductor substrate 40. 2 is a cross-sectional view of the silicon wafer body 10. FIG. The top view seen from the lower surface 10b side of the silicon wafer main body 10. FIG. FIG. 6 is a cross-sectional view taken along line VI-VI of the silicon wafer body 10 of FIG. 5. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 2 is a cross-sectional view of the silicon wafer body 10. FIG. 5 is a flowchart showing manufacturing steps of the semiconductor substrate 140. FIG. 6 is a cross-sectional view of a semiconductor substrate 140. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. 2 is a cross-sectional view of a silicon wafer body 110. FIG. The graph which shows the simulation result of the mechanical strength of a semiconductor substrate.

Explanation of symbols

10: Silicon wafer body 10a: Upper surface 10b: Lower surface 10c: Side surface 20: Circuit portion 22: Resist 24: Opening 30: Trench 34: Reinforcement material 36: Etching protection tape 38: Semiconductor element 40: Semiconductor substrate 110: Silicon wafer body 110a: upper surface 110b: lower surface 130: trench 134: reinforcing material 140: semiconductor substrate 142: filler 144: barrier film 146: high-concentration B-doped polysilicon layer

Claims (5)

A method for manufacturing a semiconductor substrate, comprising:
Forming a trench on the back surface of the substrate body;
Placing a reinforcing material having a higher elastic modulus and / or higher internal stress than the substrate body only in the formed trench.   2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the trench is formed in a region of the substrate body where the semiconductor element is not formed.   The semiconductor substrate manufacturing method according to claim 1, wherein the trench is formed by dry etching. A method for manufacturing a semiconductor substrate, comprising:
Forming a trench in a region of the back surface of the substrate body where the semiconductor element is not formed;
Arranging the reinforcing material only in the formed trench;
A step of wet-etching at least a region for forming a semiconductor element on the back surface of the substrate body after disposing the reinforcing material in the trench, and
In the wet etching process, an etching solution that hardly dissolves the reinforcing material is used. A substrate body having a trench formed on the back surface;
A reinforcing member disposed in the trench,
The reinforcing material has a higher elastic modulus and / or higher internal stress than the substrate body, and the reinforcing material is not disposed in a region of the back surface of the substrate body where no trench is formed. Semiconductor substrate.

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