JP4892368B2 - Constant charge output circuit - Google Patents

Description

  The present invention relates to a constant charge output circuit that outputs a predetermined accurate amount of charge with respect to one clock signal input.

  FIG. 9 shows an example of a conventional D / A conversion circuit. The digital data input to the input terminals in10 to in13 is 4 bits. The D / A conversion circuit includes four inverters INV10 to INV13 and four resistors R10 to R13, and a load side capacitor (not shown) is connected to the output terminal out.

This D / A converter circuit functions as an adder circuit. When four input signals are “L”, the output terminal “out” is VDD, and when one input signal is “H”, it is 3/4 · VDD. If one input signal is “H”, it is 1/2 · VDD; if three input signals are “H”, it is 1/4 · VDD; if four input signals are “H”, it is GND. Each level is determined. Since the resistors R10 to R13 and the load capacitor (not shown) constitute a filter, the digital value of the input signal is converted into an analog value. Such a D / A circuit is described in Non-Patent Document 1.
Written by Masanori Kikuchi, “Easy-to-understand Semiconductor”, Nihon Jitsugyo Publishing Co., Ltd., May 20, 2001, page 139.

  However, in the conventional D / A conversion circuit described above, a glitch occurs due to a timing shift of continuous logical data, and an error occurs. Further, if the integration time differs for each timing due to the clock jitter, there is a problem that an output voltage value different from the logical value is generated and an error occurs.

  FIG. 10 is an explanatory diagram of error occurrence due to glitches. When the output voltages out10 to out13 of the inverters INV10 to INV13 are as illustrated, the synthesized output voltage Vo should ideally be 1/2 · VDD as shown in (a). In reality, a glitch occurs due to a timing shift of each data, and as shown in (b), a noise component is included and an error occurs.

  FIG. 11 is an explanatory diagram of error occurrence due to clock jitter. Ideally, the integrated voltage should change as shown in (a), but in reality, a difference occurs in the output voltage Vo by the time difference of the data width due to jitter, and an error occurs as shown in (b). Appears in the integral voltage.

  An object of the present invention is to provide a constant charge output circuit that outputs a predetermined accurate amount of charge for one clock signal input so that no error due to glitch or clock jitter occurs. is there.

The constant charge output circuit according to the first aspect of the present invention includes a reference-side transistor and an output-side transistor whose source or emitter is connected to a first power supply, and a current whose drain or collector is connected to an output terminal. A mirror circuit; a first switch and a capacitor connected in series between the drain or collector of the reference-side transistor of the current mirror circuit and a second power supply; and a second switch connected in parallel to the capacitor From the state where the first switch is turned off and the second switch is turned on, the first switch is turned on and the second switch is turned off, or the first switch is turned off and then the first switch is turned on. And a control circuit for turning on the switch.
According to a second aspect of the present invention, in the constant charge output circuit according to the first aspect, the control circuit is configured such that the first switch is turned on and the second switch is turned off at both ends of the capacitor. Is controlled to be longer than the time until the voltage is charged to a voltage obtained by subtracting the threshold voltage of the reference side transistor from the potential difference between the first power supply and the second power supply.
According to a third aspect of the present invention, there is provided a constant charge output circuit comprising: a reference side transistor having a source or emitter connected to a first power source and an output side transistor; and a drain or collector of the output side transistor connected to an output terminal. A first current mirror circuit, and a second current mirror circuit including a reference-side transistor and an output-side transistor whose source or emitter is connected to a second power source, and a drain or collector of the output-side transistor connected to the output terminal And first and third switches connected in series between the drain or collector of the reference side transistor of the first current mirror circuit and the drain or collector of the reference side transistor of the second current mirror circuit And the fourth switch is the first power supply side, and the fifth switch is the second power supply. The fourth and fifth switches connected in series between the first power supply and the second power supply, the common connection point of the first and third switches, and the fourth and second switches A capacitor connected between a common connection point of the five switches, a second switch connected in parallel to the capacitor, and turning off the first, third, fourth, and fifth switches. From the state in which the switch is turned on, the first and fifth switches are turned on and the second switch is turned off, or the first and fifth switches are turned on after the second switch is turned off, Or, from the state in which the first, third, fourth, and fifth switches are turned off and the second switch is turned on, the third and fourth switches are turned on and the second switch is turned off. Or the above A control circuit for turning ON the third and fourth switch of the switch after the OFF, the comprising the.
According to a fourth aspect of the present invention, in the constant charge output circuit according to the third aspect, the control circuit has a period during which the first and fifth switches are on and the second switch is off. More than the time until the voltage across the capacitor is charged to a voltage obtained by subtracting the threshold voltage of the reference-side transistor of the first current mirror circuit from the potential difference between the first power supply and the second power supply. In the period when the third and fourth switches are ON and the second switch is OFF, the voltage across the capacitor is between the first power source and the second power source. Control is performed so as to be longer than the time until the voltage is charged by subtracting the threshold voltage of the reference-side transistor of the second current mirror circuit from the potential difference.
According to a fifth aspect of the present invention, in the constant charge output circuit according to the third or fourth aspect, the first current mirror is connected in series with the fourth switch between the first power source and the capacitor. A first diode composed of a transistor having the same polarity as a transistor constituting the circuit is connected, and the second current mirror circuit is connected in series with the fifth switch between the second power source and the capacitor. A second diode composed of a transistor having the same polarity as that of the transistor to be configured is connected.
According to a sixth aspect of the present invention, in the constant charge output circuit according to the third, fourth, or fifth aspect, the output side transistors of the first and second current mirror circuits are plural, and the plural output sides The drain or collector of the transistor is connected to the output terminal via an individual switch that is ON / OFF controlled by the control circuit.
According to a seventh aspect of the present invention, in the constant charge output circuit according to the third, fourth, or fifth aspect, the second output side transistor different from the output side transistor is connected to the first current mirror circuit, and A second current mirror circuit is connected to the output transistor and a third output side transistor, and the first current mirror circuit and the first switch are connected between the first current mirror circuit and the first switch. A third current mirror circuit connected in cascade is provided, and a fourth current mirror circuit connected in cascade with the second current mirror circuit is provided between the second current mirror circuit and the third switch. Providing a first transmission gate between the drain or collector of the second output-side transistor of the first current mirror circuit and the output terminal; A second transmission gate is connected between the drain or collector of the third output-side transistor of the second current mirror circuit and the output terminal, and the gate or base of the third current mirror circuit and the first current mirror circuit are connected. The first and second CMOS inverters for controlling ON / OFF of the first transmission gate are connected to a power source of one, and the first and second CMOS inverters are controlled by the control circuit. A third and a fourth CMOS inverter for controlling ON / OFF of the second transmission gate are connected between the gate or base of the fourth current mirror circuit and the second power supply; The third and fourth CMOS inverters are controlled by the control circuit.

According to the first aspect of the present invention, by controlling the control circuit as in the second aspect of the invention, the amount of output charge per clock signal can be set to a constant value. Since an accurate amount of electric charge is output, it is difficult to be affected by clock jitter.
According to the third aspect of the invention, the polarity of the output charge can be switched, and at this time, a common capacitor is used. Therefore, by controlling the control circuit as in the fourth aspect of the invention, the discharge charge amount And the suction charge amount can be made the same.
According to the fifth aspect of the present invention, it is possible to prevent an error due to the polarity of the transistor from occurring regardless of the output charge of any polarity.
According to the sixth aspect of the present invention, when adding or subtracting a plurality of output charges, the first or second current mirror circuit after the predetermined number of the plurality of output side transistors is selected, Since a current flows through the reference-side transistor of the second current mirror circuit, charges are output simultaneously from the selected output-side transistor, so that it is possible to avoid the occurrence of glitches when controlling with multiple bits.
According to the seventh aspect of the invention, the first to fourth current mirror circuits can be operated with high accuracy.

<First embodiment>
FIG. 1 is a circuit diagram showing a configuration of a constant charge output circuit according to a first embodiment of the present invention. M1 and M2 are PMOS transistors constituting a current mirror circuit having a current mirror mirror ratio of A, and a switch SW1 and a capacitor C1 are connected in series between the drain of the reference side transistor M1 and GND, and the capacitor C1 includes A switch SW2 is connected in parallel. The switches SW1 and SW2 are ON / OFF controlled by the control circuit 10 in accordance with the input clock signal clock.

  In this embodiment, when the clock signal clock is “L”, first, the switch SW2 is turned on and the switch SW1 is turned off to make both ends of the capacitor C1 have the same potential, and the charge is extinguished. Next, when the clock signal clock becomes “H”, the switch SW2 is turned OFF, and thereafter (or simultaneously) the switch SW1 is turned ON, and the drain current flowing through the transistor M1 is charged in the capacitor C1. After this, when the voltage across the capacitor C1 reaches a voltage lower than VDD by the threshold voltage Vth of the transistor M1, the charging of the capacitor C1 is finished. During this time, the total charge output as the output signal out through the transistor M2 is equal to the current mirror ratio A of the amount of charge charged in the capacitor C1.

  Therefore, when the switch SW2 is OFF and the switch SW1 is ON is Ta, and the time when the voltage across the capacitor C1 reaches the voltage lower than GND by the threshold voltage Vth of the transistor M1 than VDD is Tb. As long as Ta ≧ Tb is secured, the amount of charge output from the transistor M2 becomes an accurate constant value.

  From the above, even if there is a variation in the “H” period of the clock signal clock, as long as the period is longer than the above-described period Tb, the “H” period is not affected. That is, under this condition, an accurate fixed amount of charge is output every time the clock signal clock becomes “H” without being affected by the clock jitter.

  Therefore, for example, according to the pulse width of the PWM signal (integer multiple of the period of the clock signal clock), if the input of the clock signal clock to the control circuit 10 is turned ON / OFF by the preceding circuit (not shown), The total amount of charges output from the transistor M2 becomes the amount of charges accurately corresponding to the pulse width of the PWM signal, and if the load is a capacitor, an integrated voltage corresponding to the pulse width of the PWM signal can be obtained.

  FIG. 2 is a circuit diagram showing a configuration of a constant charge output circuit according to a modification of the first embodiment. In this example, NMOS transistors MN3 and MN4 are used as a current mirror circuit having a current mirror ratio of A, and a capacitor C1 and a switch SW3 are connected in series between the drain of the transistor M3 and the power supply line of VDD.

  Here, ON / OFF of the switches SW2 and SW3 is controlled according to the clock signal clock. In this embodiment, when the clock signal clock is “L”, first, the switch SW2 is turned on and the switch SW3 is turned off, so that both ends of the capacitor C1 have the same potential and the charge is extinguished. Next, when the clock signal clock becomes “H”, the switch SW2 is turned OFF, and thereafter (or simultaneously) the switch SW3 is turned ON, and the drain current flowing through the transistor M3 is charged in the capacitor C1. This modified example is different in that the output signal becomes a suction current with respect to the discharge current of the circuit of FIG.

  1 and FIG. 2 may be reversed by “H” and “L” of the clock signal clock. That is, the capacitor C1 may be charged during the “L” period.

<Second embodiment>
FIG. 3 is a circuit diagram showing a configuration of a constant charge output circuit according to the second embodiment of the present invention. This is a combination of the constant charge output circuit of FIG. 1 and the constant charge output circuit of FIG. 2 so that an output signal with a bipolar polarity can be obtained. The capacitor C1 is common. The transistors M1 and M2 correspond to the first current mirror circuit of the claims, and the transistors M3 and M4 correspond to the second current mirror circuit of the claims.

  When the output current is taken out from the transistor M2, the ON / OFF of the switches SW1, SW2, and SW5 is controlled, and the switches SW3 and SW4 are kept OFF. When the output current is taken out from the transistor M4, the switches SW2, SW3, SW4 are controlled to be turned on / off, and the switches SW1, SW5 are kept off. Whether the discharge current is taken out from the transistor M2 or the suction current is taken out from the transistor M4 is controlled by the control circuit 12 according to the polarity signal push / pull.

  FIG. 4 shows a waveform diagram of the operation of the circuit of FIG. In the present embodiment, since the capacitor C1 is common, the charge amount is equal for both the ejection signal push_out and the suction signal pull_out. In this embodiment, if the polarity signal push / pull is a 1-bit input digital signal, the suction signal pull_out is output when the input signal push / pull is “L” in synchronization with the clock signal clock, and “H "", The discharge signal push_out is output.

  Therefore, if the suction signal pull_out and the discharge signal push_out are supplied to a common load and the signal input as the polarity signal push / pull is a PWM signal, the “L” period of the PWM signal has two clock signals clock. If it is minutes, the suction signal pull_out is output twice in succession, and the output voltage decreases by two stages. If the “H” period of the PWM signal is equivalent to three clock signals clock, the ejection signal push_out is output three times in succession, and the output voltage increases by three stages.

<Third embodiment>
FIG. 5 is a circuit diagram showing a configuration of a constant charge output circuit according to a third embodiment of the present invention. Here, a diode-connected PMOS transistor M5 is connected between the switch SW4 and the VDD power line in FIG. 3, a diode-connected NMOS transistor M6 is connected between the switch SW5 and the GND ground line, and a transistor M2 is connected. , M4 drains are commonly connected to a terminal for taking out the output signal out.

  In the circuit of FIG. 3 described above, when the threshold voltages of the PMOS transistor and the NMOS transistor are different, there is a difference between the discharge charge amount and the suction charge amount. On the other hand, in the circuit of FIG. 5, the voltage applied to both ends of the capacitor C1 is the same when discharging the charge and when sucking the charge, so that the discharge charge amount and the suction charge amount can be the same. it can. As described above, in this embodiment, although the complementary transistor is used, the influence of the difference in the characteristics of the transistors on the output charge is eliminated. The operation is exactly the same as in FIG.

<Fourth embodiment>
FIG. 6 is a circuit diagram showing a configuration of a constant charge output circuit according to a fourth embodiment of the present invention. Here, the output side transistor M7 that forms the current mirror circuit with the transistor M1 and the output side transistor M8 that forms the current mirror circuit with the transistor M1 are added to the circuit of FIG. 5, and switches SW6 to SW9 are added. It is a thing. Then, the control circuit 13 controls the switches SW6 to SW9 according to the value of the magnification signal amp so that the charge amount and polarity of the output signal out can be switched, thereby realizing multi-bit conversion. .

  In this embodiment, as shown in FIG. 7, the switches SW6 to SW9 are switched to a predetermined state in accordance with the magnification signal amp. For example, if the mirror ratios of the transistors M1, M2, M7, M4, M3, and M8 are all A, if the switch SW6 is turned on and the switch SW8 is turned off, the discharge current is the charge amount of the capacitor C1. If it is A times and the switches SW6 and SW8 are turned on, it becomes 2A times. If the switch SW7 is turned on and the switch SW9 is turned off, the suction current is A times the amount of charge charged to the capacitor C1, and if the switches SW7 and SW9 are turned on, the suction current is 2A.

  Therefore, if the magnification signal amp is 1-bit data and the polarity signal push / pull is another 1-bit data, the 2-bit data is + A and + 2A times the amount of charge charged in the capacitor C1. , -A times and -2A times can be selectively output, so that 2-bit input data can be D / A converted. At this time, since the start point of charge charging to the capacitor C1 is common and the end point is also common, the influence of the glitch caused by the time difference of the signal path of the data of each bit which has occurred in the conventional example is eliminated. Can do.

<Fifth embodiment>
FIG. 8 is a circuit diagram showing the configuration of the constant charge output circuit of the fifth embodiment. Here, the control circuit 14 includes inverters INV1 to INV8, NAND circuits NAND1 and NAND2, and a NOR circuit NOR1. M11 to M13, M19 to M21, M25, M26, M29, M31, M35, M37, M38, M39, M41, M43, M45, M49, M51 to M53, and M55 are PMOS transistors, and the other transistors are NMOS transistors. is there.

  In comparison with the circuit of FIG. 6, the transistors M11 and M12 correspond to the transistor M5, the transistor M13 corresponds to the switch SW4, the transistor M14 corresponds to the switch SW5, the transistors M15 and M16 correspond to the transistor M6, and the transmission Transistors M17 and M18 constituting the gate correspond to the switch SW2, the transistor M19 corresponds to the transistor M1, the transistor M21 corresponds to the switch SW1, the transistor M22 corresponds to the switch SW3, and the transistor M24 corresponds to the transistor M3. The transistor M25 corresponds to the transistor M2, the transistor M28 corresponds to the transistor M4, the transistor M35 corresponds to the transistor M7, and the transistor M36 corresponds to the transistor M8. That.

  Transistors M19, M25, M35, and M49 constitute a first current mirror circuit, transistors M24, M28, M36, and M50 constitute a second current mirror circuit, and transistors M20 and M26 constitute a third current mirror. A circuit is constituted, and the transistors M23 and M27 constitute a fourth current mirror circuit. The transistors M19, M25, M35, and M49 have the same W / L ratio, the transistors M20 and M26 have the same W / L ratio, and the transistors M24, M28, M36, and M50 have the same W / L ratio. The transistors M23 and M27 have the same W / L ratio. That is, the current mirror ratio A of each current mirror circuit is 1.

  Transistors M29 and M30, M39 and M40, M43 and M44, M53 and M54, M31 and M32, M41 and M42, M45 and M46, and M55 and M56 each constitute an inverter. Transistors M33 and M37, M47 and M51, M34 and M38, and M48 and M52 constitute transmission gates, respectively.

  In the present embodiment, the polarity signal push / pull1, the magnification signal amp1, and the magnification signal amp2 are each set as a 1-bit data signal, so that the 3-bit input data is synchronized with the clock signal clock. Can be converted.

  When the clock signal clock is “L”, the transistors M17 and M18 are turned on and the potentials at both ends of the capacitor C1 are equal. When the clock signal clock is “H”, the transistors M17 and M18 are turned off and the capacitor C1 can be charged. It becomes.

  When the polarity signal push / pull is “L”, the transistors M13 and M22 are ON and the transistors M14 and M21 are OFF. When the polarity signal is “H”, the transistors M13 and M22 are OFF and the transistors M14 and M21 are ON. .

  When the magnification signal amp1 is “L”, the transmission gate composed of the transistors M33 and 37 and the transmission gate composed of the transistors M34 and M38 are turned on, and when the magnification signal amp1 is “H”, the transmission gate is turned off. That is, when the magnification signal amp1 is “L”, the drain current of the transistor M35 or M36 is added to the drain current of the transistor 26 or M27, and is not added when it is “H”.

  When the transistor amp2 is “L”, the transmission gate composed of the transistors M47 and 51 and the transmission gate composed of the transistors M48 and M52 are turned on, and when the transistor amp2 is “H”, the transmission gate is turned off. That is, when the magnification signal amp2 is “L”, the drain current of the transistor M49 or M50 is added to the drain current of the transistor M26 or M27, and when the magnification signal amp2 is “H”, it is not added.

  Therefore, for example, when the polarity signal push / pull is “H”, the magnification signal amp1 is “L”, and the magnification signal amp2 is “H”, the charge twice as much as the charge charged in the capacitor C1 is used as the output signal out. Exhaled. The operation at this time will be described below.

  When the clock signal clock is “L”, the transistors M17 and M18 operating as transmission gates are turned on, the potentials at both ends of the capacitor C1 are equalized, the transistors M33 and M37, M34 and M38 operating as transmission gates are turned on, and the transistor M47 M51, M48 and M52 are turned OFF, the current mirror output of the transistors M49 and M50 is stopped, and the transistors M13 and M22 are fixed to OFF.

  Next, when the clock signal clock becomes “H”, the transistors M17 and M18 are first turned OFF, and then the transistors M14 and M21 are turned ON. The drain of the transistor M14 is connected to the total gates of the transistors M15 and M16 from GND. The capacitor C1 is charged by a potential higher than the source voltage, and the drain of the transistor M21 is lower than VDD by the total gate-source voltage of the transistors M19 and M20.

  At the same time, the current for charging the capacitor C1 flows through the transistors M25 and M35 that are current mirrored from the transistor M19, other than the transistor M49 that cannot flow current because the transistors M47 and M51 are OFF. At this time, since the W / L ratios of the transistors M19, M25, and M35 are equal, a current is output as the output signal out at twice the current of the transistor M19 that charges the capacitor C1, and as a result, is stored in the capacitor C1. A charge that is twice the charge is output.

  The above is a case where the amount of charge twice as much as the amount of charge charged in the capacitor C1 is discharged as the output signal out. However, when discharging the amount of charge equal to one time, “H” is applied to both the magnification signals amp1 and amp2. So that charges are discharged only from the transistor M26. Further, when discharging the charge amount of 3 times, “L” is given to both of the magnification signals amp1 and amp2 so as to be discharged from the transistors M26, M35, and M49.

  In addition, in order to absorb a charge amount that is one time larger than the charge amount charged in the capacitor C1 as the output signal out, “L” as a subtraction is given to the polarity signal push / pull. Then, “H” is given to both of the magnification input signals amp1 and amp2 so that charges are sucked only from the transistor M27. In order to absorb twice the charge amount, “L” is applied to the magnification signal amp1, “H” is applied to the amp2, or “H” is applied to the magnification signal amp1, and “L” is applied to the amp2. Suction is performed from M36 or from transistors M27 and M50. Further, when the charge amount of 3 times is sucked, "L" is given to both of the magnification input signals amp1 and amp2 so as to be sucked from the transistors M27, M36, and M50.

  In the present embodiment, the capacitor C1 serving as one reference is used in common, and the polarity and magnification of the current mirror circuit are switched and used, so that it is not easily affected by variations in elements.

  Further, when the magnification signals ampl and amp2 for switching the output magnification are set to “L” to increase the magnification, the gate voltage of the transistor M20 is applied to the gates of the transistors M33 and 37, and M47 and M51 that operate as switches, and the transistor M34 Since the gate voltage of the transistor M23 is applied to the gates of M38, M48, and M52, the drain voltages of the transistors M35 and M49 to which the current is mirrored become equal to the drain voltage of the reference transistor M19, and the current is The drain voltages of the mirrored transistors M36 and M50 are equal to the drain voltage of the reference transistor M24, and the operation accuracy of the current mirror is increased.

  Further, by using transmission gates (M33 and M37, M47 and M51, M34 and M38, M48 and M52) for switching the magnification, the switch signal leaking from between the gate and the drain is cancelled.

  In addition, since the transistors M11, M12, M15, and M16 are balanced in accordance with a plurality of stages of current mirror circuits (the number of transistors connected in series between VDD and GND is the same), the PMOS transistor Even if the characteristics of the transistor and the NMOS transistor are different, the voltage applied to the capacitor C1 is the same at the time of addition and subtraction, so the output charge amounts at the addition and subtraction are equal, and the influence of the channel length modulation effect is prevented. be able to. In the present invention, a bipolar transistor can be used in place of the MOS transistor, and in this case, the influence of the Early effect can be prevented.

1 is a constant charge output circuit according to a first embodiment of the present invention. It is a constant charge output circuit of the modification of a 1st Example. It is a constant charge output circuit of the 2nd example of the present invention. FIG. 4 is an operation waveform diagram of the constant charge output circuit of FIG. 3. It is a constant charge output circuit of the 3rd example of the present invention. It is a constant charge output circuit of the 4th example of the present invention. FIG. 7 is an operation waveform diagram of the constant charge output circuit of FIG. 6. It is a constant charge output circuit of the 5th example of the present invention. It is a circuit diagram which shows the structure of the conventional D / A conversion circuit. It is a wave form diagram which shows the influence of the glitch of the D / A converter circuit of FIG. FIG. 10 is a waveform diagram showing the influence of clock jitter in the D / A conversion circuit of FIG. 9.

Explanation of symbols

  10-14: Control circuit

Claims (7)

A current mirror circuit comprising a reference-side transistor and an output-side transistor whose source or emitter is connected to a first power supply, and a drain or collector of the output-side transistor connected to an output terminal;
A first switch and a capacitor connected in series between the drain or collector of the reference-side transistor of the current mirror circuit and a second power supply;
A second switch connected in parallel to the capacitor;
From the state in which the first switch is turned off and the second switch is turned on, the first switch is turned on and the second switch is turned off, or the second switch is turned off and then the first switch is turned on. A control circuit for turning on the switch;
A constant charge output circuit comprising: The constant charge output circuit according to claim 1, wherein the control circuit includes:
During the period in which the first switch is ON and the second switch is OFF, the threshold voltage of the reference-side transistor is determined based on the potential difference between the first power source and the second power source. A constant charge output circuit, characterized in that control is performed so as to be longer than a time required for charging to a voltage obtained by subtracting the voltage. A first current mirror circuit including a reference-side transistor and an output-side transistor whose source or emitter is connected to a first power supply, and a drain or collector of the output-side transistor connected to an output terminal;
A second current mirror circuit comprising a reference-side transistor and an output-side transistor whose source or emitter is connected to a second power supply, and a drain or collector of the output-side transistor connected to the output terminal;
First and third switches connected in series between the drain or collector of the reference side transistor of the first current mirror circuit and the drain or collector of the reference side transistor of the second current mirror circuit;
The fourth and second power supplies connected in series between the first power source and the second power source so that the fourth switch is on the first power source side and the fifth switch is on the second power source side. 5 switches,
A capacitor connected between a common connection point of the first and third switches and a common connection point of the fourth and fifth switches;
A second switch connected in parallel to the capacitor;
From the state in which the first, third, fourth, and fifth switches are turned off and the second switch is turned on, the first and fifth switches are turned on and the second switch is turned off, or From the state in which the first and fifth switches are turned on after turning off the second switch, or the first, third, fourth, and fifth switches are turned off and the second switch is turned on. A control circuit for turning on the third and fourth switches and turning off the second switch, or turning on the third and fourth switches after turning off the second switch;
A constant charge output circuit comprising: The constant charge output circuit according to claim 3, wherein the control circuit includes:
During the period in which the first and fifth switches are ON and the second switch is OFF, the voltage across the capacitor is changed from the potential difference between the first power source and the second power source. Control to be longer than the time until the current mirror circuit is charged to a voltage obtained by subtracting the threshold voltage of the reference side transistor of the current mirror circuit,
During the period in which the third and fourth switches are ON and the second switch is OFF, the voltage across the capacitor is changed according to the potential difference between the first power source and the second power source. The current mirror circuit is controlled so as to be longer than the time until charging to a voltage obtained by subtracting the threshold voltage of the reference side transistor of the current mirror circuit,
A constant charge output circuit. The constant charge output circuit according to claim 3 or 4,
A first diode composed of a transistor having the same polarity as that of the transistor constituting the first current mirror circuit is connected in series with the fourth switch between the first power source and the capacitor.
Between the second power supply and the capacitor, a second diode composed of a transistor having the same polarity as the transistor constituting the second current mirror circuit is connected in series with the fifth switch.
A constant charge output circuit. The constant charge output circuit according to claim 3, 4 or 5,
A plurality of the output side transistors of the first and second current mirror circuits are provided, and the drains or collectors of the plurality of output side transistors are connected via the individual switches that are ON / OFF controlled by the control circuit. Connected to the output terminal,
A constant charge output circuit. The constant charge output circuit according to claim 3, 4 or 5,
A second output side transistor different from the output side transistor is connected to the first current mirror circuit;
A third output side transistor different from the output side transistor is connected to the second current mirror circuit;
A third current mirror circuit connected in cascade with the first current mirror circuit is provided between the first current mirror circuit and the first switch;
A fourth current mirror circuit connected in cascade with the second current mirror circuit is provided between the second current mirror circuit and the third switch;
A first transmission gate is connected between a drain or collector of the second output-side transistor of the first current mirror circuit and the output terminal;
A second transmission gate is connected between a drain or collector of the third output-side transistor of the second current mirror circuit and the output terminal;
First and second CMOS inverters for controlling ON / OFF of the first transmission gate are connected between the gate or base of the third current mirror circuit and the first power supply, and the first Controlling the first and second CMOS inverters by the control circuit;
Third and fourth CMOS inverters for controlling ON / OFF of the second transmission gate are connected between the gate or base of the fourth current mirror circuit and the second power supply, and the second Controlling the third and fourth CMOS inverters by the control circuit;
A constant charge output circuit.

Images