JP4877722B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having an integrated circuit and a manufacturing method thereof. In particular, the present invention relates to an electronic device in which a semiconductor element having embedded wiring is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, when a multilayer wiring is formed on a semiconductor element, by stacking the wiring, a step is increased as the upper layer is formed, and it is difficult to process the wiring. Therefore, generally, a wiring material is embedded in a wiring opening such as a wiring groove or hole formed in an insulating film by a wiring forming technique called a damascene method.

  The damascene method is to form a metal wiring by first forming a groove in the insulating film, applying a metal material to the entire surface, and then polishing the entire surface by a CMP (Chemical Mechanical Polishing) method or the like. is there. At this time, a method including forming a hole for making contact with a lower metal wiring or a semiconductor region below the metal wiring is called a dual damascene method. The dual damascene method includes a step of forming a connection hole and a wiring groove with a lower layer wiring, depositing a wiring material, and removing a wiring material other than the wiring portion by a CMP method.

  For metal wiring using the dual damascene method, copper (Cu) by electrolytic plating is often used. In the electrolytic plating method, since copper (Cu) is completely embedded in the connection hole, it is necessary to adjust the plating solution and the applied electric field in a complicated manner. Further, it is difficult to process copper (Cu) by an etching process using an etchant or an etching gas, and a special CMP method for polishing is required for processing copper (Cu).

The electrolytic plating method and the CMP method have a problem in that the manufacturing cost for wiring formation is increased.

  In order to realize a high-performance semiconductor device capable of high-speed operation, a wiring material having a lower electrical resistivity than copper is used, and an insulating film having a low dielectric constant is used as a material for the insulating film in which the wiring opening is formed. The structure to be used is further required in the future.

  In view of this, the present inventors are studying the use of silver nanoparticles in order to use silver having a lower electrical resistivity than copper or an alloy containing silver as a main component. However, in the conventional silicon dioxide film and silicon nitride film used for the interlayer insulating film, the present inventors have a problem that since the film is dense, the contact area with the silver nanoparticles is small and the adhesion is poor. I found it.

  Further, a silicon dioxide film (ε = 4.1 to 3.7) used for a conventional interlayer insulating film is required to have an insulating film having a high relative dielectric constant and a low dielectric constant.

  Therefore, the present invention has been proposed in view of such circumstances, and a semiconductor having a low electrical resistivity wiring required for further speeding up of a semiconductor device and an interlayer insulating film having a low relative dielectric constant. It is an object to provide a device manufacturing method.

  According to the method for manufacturing a semiconductor device of the present invention, a silver wiring that conducts to a wiring formed under an interlayer insulating film through a connection hole of the interlayer insulating film is formed so as to be embedded in the interlayer insulating film. The formation process includes forming an interlayer insulating film on the lower layer wiring, forming a connection hole and a wiring groove connected to the lower layer wiring in the interlayer insulating film, and forming a wiring groove for forming the upper layer wiring in the interlayer insulating film. A patterning step to be formed on the substrate, a step of dropping a liquid conductive material (typically Ag) into the connection hole and the wiring groove by a droplet discharge method (typically an ink jet method), and a selection of the dropped conductive material A first conductive layer and a second conductive layer covering the upper surface of the first conductive layer in order to prevent diffusion of the conductive material of the first conductive layer, thereby forming the first conductive layer and the second conductive layer. And a step of forming an upper layer wiring composed of layers.

  That is, Structure 1 of the invention relating to a method for manufacturing a semiconductor device disclosed in this specification is a method for manufacturing a semiconductor device having a plurality of wiring layers, and includes a step of forming an insulating film, and selective etching to form the insulating film. A step of forming an opening (a connection hole and a wiring groove) in the film, a step of dropping a droplet containing a conductive material into the opening by a droplet discharge method, and a conductive treatment of the opening by selectively irradiating a laser beam. Heating a material to form a first conductive layer embedded in the opening of the insulating film, and forming a second conductive layer covering the top surface of the first conductive layer. This is a feature of a method for manufacturing a semiconductor device.

  In the configuration 1, the second conductive layer functioning as a barrier film for preventing diffusion of the conductive material of the first conductive layer is one selected from W, Mo, Ti, Cr, or Ta obtained by sputtering. It is characterized by being a metal layer containing a plurality of species.

In addition, it is desirable to form a barrier film for preventing diffusion of the conductive material (Ag) before dropping a droplet containing a conductive material into the opening (connection hole and wiring groove) by a droplet discharge method. Another structure 2 of the present invention relating to the manufacturing method of the present invention is a method of manufacturing a semiconductor device having an integrated circuit and a plurality of wiring layers. The step of forming an insulating film, the step of forming a mask on the insulating film, Selectively etching to form openings (connection holes and wiring grooves) in the insulating film; forming a first conductive layer in the mask and the openings;
A step of dropping a droplet containing a conductive material into the opening by a droplet discharge method; and a second method in which the conductive material in the opening is heated by selectively irradiating laser light to be embedded in the opening of the insulating film. A step of forming a conductive layer; a step of forming a third conductive layer on the mask and the second conductive layer; and a first conductive layer and a third conductive layer formed on the mask simultaneously with the removal of the mask And a step of leaving the third conductive layer formed in the opening by removing the semiconductor device.

  Moreover, in the said structure 2, in order to set it as an interlayer insulation film with a low dielectric constant, it is preferable that the said insulation film is a porous insulation film. In this specification, a porous insulating film refers to an insulating film having fine pores in the film, and preferably an inorganic insulating film or organic insulating film having a porosity of 20% or more and less than 90%. It is a film selected from a film or an organic-inorganic composite film. If the porosity is smaller than this range, the dielectric constant cannot be sufficiently reduced. On the other hand, if the porosity is larger than the range, the mechanical strength of the film is insufficient.

  Further, the present invention is not limited to the selective firing of the conductive layer with laser light, and another configuration 3 of the present invention relating to a method for manufacturing a semiconductor device is a semiconductor device having an integrated circuit and a plurality of wiring layers. A method for forming an insulating film; a step of selectively etching to form openings (connection holes and wiring grooves) in the insulating film; a step of forming a first conductive film; and a droplet A step of dropping a droplet including a conductive material around the opening and the periphery of the opening by a discharge method and baking to form a conductive film; a step of selectively etching the conductive film to form a second conductive layer; Forming a third conductive film on the second conductive layer, and etching the first conductive film and the third conductive film using the same mask to form the first conductive layer and the third conductive layer. A step of contacting a droplet to be dropped before dropping the droplet. A method for manufacturing a semiconductor device, which comprises carrying out the surface treatment to reduce the angular to the first conductive surface.

  The surface-treated region is a region having a small contact angle and a region with high wettability (hereinafter also referred to as a high wettability region). When the contact angle is large, the liquid composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted. However, when the contact angle is small, the composition has fluidity on the surface. Spreads out and wets the surface well. In the present invention, the contact angle of the region with high wettability is preferably 10 degrees or less. As this surface treatment, for example, a treatment for selectively increasing wettability with light may be performed. Specifically, a substance with low wettability is formed in the vicinity of the pattern formation region, and light with a degree of decomposition of the substance with low wettability is irradiated to decompose and remove the substance with low wettability in the processing region. As a result, the wettability of the processing region is improved and a high wettability region is formed.

  By performing the surface treatment as in the configuration 3, when the droplet containing the conductive material is dropped, the connection hole and the wiring groove can be filled so as to spread. By dropping droplets containing conductive material so that it spreads wet, the tact time of the coating process is reduced compared to the method of coating while tracing the connection holes and wiring grooves using the inkjet method without surface treatment. It can be shortened. In addition, it is possible to reduce the consumption of materials compared to a method of applying by spin-on coating.

  Further, a semiconductor device obtained by the manufacturing method of Configuration 2 is also one aspect of the present invention, and Configuration 4 is a semiconductor device having an integrated circuit and a plurality of wiring layers, and includes a porous insulating film and the porous device. A first conductive layer in contact with the bottom and inner walls of a wiring groove or contact hole (also referred to as a connection hole) formed in the insulating film, a second conductive layer in contact with the first conductive layer, and an upper surface of the second conductive layer And a wiring layer composed of a laminate with a third conductive layer in contact with the first conductive layer, the second conductive layer being surrounded by the first conductive layer and the third conductive layer, A semiconductor device comprising a step between a first surface including an upper surface of a porous insulating film and a second surface including an upper surface of the third conductive layer.

  In the configuration 4, the porous insulating film is a material containing silicon oxide.

  The present invention is not particularly limited to the porous insulating film, and the configuration 5 is a semiconductor device having an integrated circuit and a plurality of wiring layers, and the insulating film and a wiring groove or contact formed in the insulating film. A stack of a first conductive layer in contact with the bottom and inner walls of the hole, a second conductive layer in contact with the first conductive layer, and a third conductive layer in contact with the top surface of the second conductive layer and the first conductive layer. And the second conductive layer is surrounded by the first conductive layer and the third conductive layer, and includes a first surface including an upper surface of the insulating film, and the third conductive layer. And a second surface including a top surface of the semiconductor device.

  In any one of the structures 2 to 5, the integrated circuit includes at least one of a controller, a CPU, and a memory. Further, an antenna may be provided.

  In any one of the above configurations 2 to 5, the first conductive layer and the third conductive layer include one or more selected from W, Mo, Ti, Cr, or Ta obtained by sputtering. One of the features is that it is a metal layer. The first conductive layer and the third conductive layer may be made of the same material or different materials.

  One of the structures 2 to 5 is that the second conductive layer is a material containing silver. In a pattern forming method such as a conductive layer using a droplet discharge method, a pattern is formed by discharging a pattern forming material processed into particles, and fusing or fusion bonding by baking to solidify. Therefore, the pattern formed by sputtering or the like often shows a columnar structure, whereas it often shows a polycrystalline state having many grain boundaries.

  One of the structures 2 to 5 is that the second conductive layer is a material containing a resin. This resin is a material such as a binder contained in droplets containing a conductive material, and can be ejected by an ink jet method by mixing this resin, a solvent, and silver nanoparticles.

  According to the present invention, the number of steps can be reduced as compared with the conventional method by selectively forming wiring, and the conductive film is completely embedded in the interlayer insulating film having a high aspect ratio by using a liquid conductive material. It is possible.

  In addition, according to the present invention, by using a porous insulating film as the interlayer insulating film, it is possible to reduce the relative dielectric constant of the interlayer insulating film and improve the adhesion with the paste containing Ag.

  Embodiments of the present invention will be described below.

(Embodiment 1)
In this embodiment mode, FIGS. 1A to 1E and FIGS. 2A to 2C are used with respect to one embodiment of the present invention for forming a silver wiring embedded in an interlayer insulating film. I will explain. Here, for the sake of simplification, a semiconductor element and an integrated circuit are not shown, and only a connection portion between a buried silver wiring and a lower layer wiring is shown.

  First, a first layer wiring (lower layer wiring) 102 is formed on an insulating film 101 provided on a semiconductor substrate on which an element (not shown) such as a transistor is formed, and an interlayer insulation is formed so as to cover the wiring 102. A film 103 is formed (FIG. 1A).

  The semiconductor substrate is a single crystal silicon substrate or a compound semiconductor substrate, and is typically an N-type or P-type single crystal silicon substrate, GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, or ZnSe substrate. is there. Alternatively, an SOI (silicon on insulator) substrate in which an insulating layer and a single crystal semiconductor layer are stacked may be used. As an SOI substrate, for example, a SIMOX (separation by implied oxygen) substrate can be cited. A SIMOX substrate is a substrate in which a single crystal semiconductor layer is formed on an insulating layer and the insulating layer by embedding oxygen molecules in a portion slightly deep from the surface of the single crystal semiconductor layer and oxidizing it with high heat. A substrate in which one single crystal semiconductor layer, an insulating layer, and a second single crystal semiconductor layer are stacked.

  The interlayer insulating film 103 is selected to have a low relative dielectric constant in order to prevent signal delay due to capacitance. By using a porous insulating film as the interlayer insulating film 103, the above object can be achieved. In this embodiment mode, the use of a porous insulating film for the interlayer insulating film 103 reduces the dielectric constant and improves the adhesion with a wiring material to be formed later. The reason why the adhesion between the porous low dielectric constant interlayer insulating film and the wiring material is improved will be described later.

  After the interlayer insulating film 103 is formed, patterning is performed by photolithography to form a first mask 104a made of a photoresist. After that, the interlayer insulating film 103 is anisotropically etched to form a first opening (also referred to as a trench) 105 as shown in FIG.

  After the first mask 104a is removed, patterning is performed by photolithography in order to form a new mask. Thus, a second mask 104b made of a photoresist is formed as shown in FIG. Thereafter, the interlayer insulating film 103 is anisotropically etched again to form a second opening made of the connection hole 106a and the wiring groove 106b.

  After that, without removing the second mask 104b made of photoresist, a barrier film 107 is formed over the entire surface by sputtering as shown in FIG. As shown in FIG. 1D, the inner wall of the connection hole 106a and the inner wall of the wiring groove 106b are formed thin, but are formed so as to be hardly formed on the inner wall of the thick second mask 104b. Is desirable.

  Here, a TiN film is used as the barrier film 107. Note that the barrier film 107 can be referred to as a first conductive layer. The barrier film 107 is used as a diffusion preventive film for suppressing defects such as leaks that are caused by diffusion of a wiring material to be discharged later by the droplet discharge method into the interlayer insulating film 103. Note that the barrier film 107 is not limited to be formed by a sputtering method, but can also be formed by a CVD method.

  Next, as shown in FIG. 1E, a paste 108 containing Ag is dropped only on the opening by an inkjet method. In the inkjet method, when the ejected droplets land on the substrate, the positional accuracy of the landed droplets is low (for example, ± 10 μm). In this embodiment, the second mask 104b made of a photoresist is used as a partition wall. Compensates for landing accuracy. Thereby, the ink jet method can be used even with a process rule of 10 μm or less.

  The paste 108 containing Ag discharged by inkjet contains Ag nanoparticles, and the resistivity can be reduced as compared with Cu used as a conventional wiring material. In addition, since it is liquid, it can be covered with any shape of the base, and wiring can be formed without being bound by the shape of the base.

  Moreover, the size of the Ag nanoparticles of the paste 108 containing Ag is about 3 nm to 5 nm. Therefore, when a paste containing Ag is applied on the interlayer insulating film 103 of the porous insulating film or on the barrier film 107 formed on the interlayer insulating film 103, Ag particles are formed in the pores, recesses or interlayers of the interlayer insulating film 103. The barrier film 107 formed on the insulating film 103 enters the recess and the adhesion is enhanced by the so-called anchor effect.

  If the paste 108 containing Ag is not baked at about 300 ° C., sufficient conductivity cannot be obtained. Therefore, in this embodiment mode, only the paste 108 containing Ag is selectively heated and fired using a laser device. Here, the reason for using the laser device will be described later.

  Note that in this embodiment mode, a formed product after baking a paste containing Ag is also called a paste 108 containing Ag. Actually, it is a conductor solidified by fusion or fusion bonding by firing, and can also be called a second conductive layer.

  Next, as illustrated in FIG. 2A, a conductive film 109 is formed over the entire surface by a sputtering method so as to cover the paste 108 containing Ag. As shown in FIG. 2A, it is desirable that the second mask 104b having a large thickness is hardly formed on the inner wall. In FIG. 2A, although not formed on the inner wall of the connection hole 106a and the inner wall of the wiring groove 106b, a film may be formed. The conductive film 109 is used as a barrier for preventing a device failure such as a leak that occurs when the paste 108 containing Ag is baked and then the paste 108 containing Ag diffuses into the interlayer insulating film 103.

  Further, the paste 108 containing Ag is corroded by the etching gas, and there is a problem that the conductivity is lowered. Description will be made assuming that a structure as shown in FIG. In this structure, a connection hole 114 is formed in the interlayer insulating film 112, and the conductive Ag paste 111 and the upper electrode 113 are electrically connected. When the interlayer insulating film 112 is etched by dry etching to form the connection hole 114, the excited etching gas corrodes the conductive Ag paste 111, and the conductivity is significantly reduced.

  In order to prevent such corrosion, it is effective to use a conductive film 109 as a barrier as shown in FIG. Note that the conductive film 109 can also be referred to as a third conductive layer.

  For the above reasons, the conductive film 109 has a low resistance, has a barrier property to suppress the diffusion of the conductive Ag paste 108, and has a sufficiently large selection ratio with the silicon-based interlayer insulating film in dry etching. It is preferable that the material is provided at least. For example, the conductive film 109 may be formed using a material including one or more selected from W, Mo, Ti, Cr, and Ta.

  After the conductive film 109 is formed, the second mask 104b functioning as a photoresist is removed as shown in FIG. At this time, the barrier film 107 and the conductive film 109 deposited on the second mask 104b made of photoresist are removed together with the second mask 104b made of photoresist, and a wiring 110 embedded in the interlayer insulating film 103 is formed. can do. The embedded wiring 110 has a structure in which Ag is surrounded by the barrier film 107 and the conductive film 109.

  Here, the reason why a laser device is used for firing the conductive Ag paste 108 will be described. A method of removing the deposit on the photoresist together with the photoresist is called a lift-off method. In order to use this method, it is necessary that the photoresist can be peeled from the substrate, and that the deposit on the photoresist and the deposit on the substrate are cut off. In the manufacturing process of the present invention, if a heating instrument such as an oven is used, the entire substrate is heated and the resist is heated to several hundred degrees. Usually, when the photoresist is heated at a high temperature, the peelability is lowered, so that the lift-off method cannot be used. For this reason, in this embodiment, in order to make it possible to use the lift-off method after the wiring baking process, the wiring is selectively baked using a laser device.

  Moreover, although the example using the insulating film 101 provided on the semiconductor substrate on which an element such as a transistor is formed is shown, the insulating film provided on the glass substrate may be used without any particular limitation. For example, the glass substrate A lower layer wiring may be formed on the interlayer insulating film of the TFT provided thereon, and a buried wiring connected to the lower layer wiring may be formed.

(Embodiment 2)
In this embodiment, one embodiment of the present invention, in which steps are partly different from those of Embodiment 1 described above, will be described with reference to FIGS. Here again, for the sake of simplification, the semiconductor element and the integrated circuit are not shown, and only the connection portion between the embedded silver wiring and the lower layer wiring is shown.

  First, similarly to Embodiment Mode 1, steps from FIG. 1A to FIG. 1C are performed. Then, the mask is removed to obtain the state of FIG. In FIG. 3A, a lower wiring 202 formed on an insulating film 201 provided over a semiconductor substrate on which an element (not shown) such as a transistor is formed, an interlayer insulating film 203, and an interlayer insulating film The provided connection hole 204a and wiring groove 204b are shown.

  Next, as shown in FIG. 3B, a barrier film 205 is formed over the entire surface by sputtering or CVD. A barrier film is also formed on the inner wall of the opening. The barrier film 205 can be referred to as a first conductive layer.

  Next, surface treatment of the barrier film 205 is performed by ultraviolet irradiation in order to improve the wettability of the droplets dropped later. Here, the surface treatment for improving the wettability is a treatment such that the contact angle with the droplet is 10 ° or less, and in addition to ultraviolet irradiation, a gas such as oxygen, argon, hydrogen, helium, etc. There is plasma processing using corona or corona discharge processing.

  Next, as shown in FIG. 3C, the connection hole 204a and the wiring groove 204b are filled with a paste 206 containing Ag by an ink jet method. Here, the paste 206 containing Ag spreads and spreads by the surface modification treatment. The paste 206 containing Ag overflowing from the connection hole 204a and the wiring groove 204b can also be applied to openings (not shown) such as adjacent connection holes and wiring grooves formed around the connection hole 204a and the wiring groove 204b. Fill to spread.

  As described above, by dropping the paste 206 containing Ag so as to spread and spread, the dropping process is compared with the method of dropping the connection hole 204a and the wiring groove 204b using the inkjet method. It is possible to shorten the tact time. Further, the consumption of material can be reduced as compared with a method of applying by spin-on coating.

  Next, baking is performed at 300 ° C. for 1 hour using a heating apparatus such as an oven. Note that in this embodiment mode, a formed product obtained by baking a paste containing Ag and evaporating a solvent contained therein is also referred to as a paste 206 containing Ag. Actually, it is a conductor solidified by fusion or fusion bonding by firing, and can also be called a second conductive layer.

  Next, as shown in FIG. 3D, patterning is performed using photolithography, and wet etching is performed with a mixed acid aqueous solution of oxalic acid, phosphoric acid, and acetic acid to form an Ag wiring 207.

  Next, as shown in FIG. 3E, a conductive film 208 is formed by a sputtering method. Note that the conductive film 208 can also be referred to as a third conductive layer.

  Next, as shown in FIG. 3F, the barrier film 205 and the conductive film 208 are etched by anisotropic etching. In this way, a wiring embedded in the interlayer insulating film 203 can be obtained. The embedded wiring has a structure in which Ag is surrounded by the barrier film 205 and the conductive film 208.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  Hereinafter, a manufacturing procedure of an FET using the present invention will be briefly described with reference to FIG. Here, an example is shown in which a wiring connected to the impurity region of the FET is used as a lower layer wiring and a buried wiring is formed in a porous insulating film covering the lower layer wiring.

  First, a silicon substrate 301 made of single crystal silicon is prepared. Then, the n-type well 302 and the p-type well 303 are selectively formed in the first element formation region and the second element formation region of the main surface (element formation surface or circuit formation surface) of the silicon substrate, respectively.

  Next, a field oxide film 306 serving as an element isolation region for partitioning the first element formation region and the second element formation region is formed. The field oxide film 306 is a thick thermal oxide film and may be formed using a known LOCOS method. The element isolation method is not limited to the LOCOS method. For example, the element isolation region may have a trench structure using the trench isolation method, or may be a combination of the LOCOS structure and the trench structure.

  Next, a gate insulating film is formed by thermally oxidizing the surface of the silicon substrate, for example. The gate insulating film may be formed by a CVD method, and a silicon oxynitride film, a silicon oxide film, a silicon nitride film, or a stacked film thereof can be used. For example, a stacked film of a silicon oxide film having a thickness of 5 nm obtained by thermal oxidation and a silicon oxynitride film having a thickness of 10 nm to 15 nm obtained by a CVD method is formed.

Next, a laminated film of polysilicon layers 311a and 317a and silicide layers 311b and 317b is formed on the entire surface, and the laminated film is patterned based on a lithography technique and a dry etching technique, thereby forming a gate electrode having a polycide structure on the gate insulating film. 311 and 317 are formed. The polysilicon layers 311a and 317a may be doped in advance with phosphorus (P) at a concentration of about 10 ²¹ / cm ³ in order to reduce the resistance, or after the formation of the polysilicon film, a deep n-type impurity May be diffused. The silicide layers 311b and 317b can be made of molybdenum silicide (MoSix), tungsten silicide (WSix), tantalum silicide (TaSix), titanium silicide (TiSix), or the like. Just do it.

  Next, in order to form an extension region, ion implantation is performed on the silicon semiconductor substrate through the gate insulating film. In this embodiment, the impurity region formed between each source region and drain region and the channel formation region is called an extension region. The impurity concentration of the extension regions 307 and 313 may be lower than that of the source region and the drain region, may be equal, or may be higher. That is, the impurity concentration in the extension region may be determined based on characteristics required for the semiconductor device.

  Since this embodiment is a case of manufacturing a CMOS, a first element formation region in which a p-channel FET is to be formed is covered with a resist material, and an arsenic (n-type impurity) is formed using the gate electrode 317 as a mask. As) or phosphorus (P) is implanted into the silicon substrate. Further, the second element formation region in which the n-channel FET is to be formed is covered with a resist material, and boron (B), which is a p-type impurity, is implanted into the silicon substrate using the gate electrode as a mask.

  Next, a first activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation.

  Next, sidewalls 312 and 318 are formed on the sidewalls of the gate electrode. For example, an insulating material layer made of silicon oxide may be deposited on the entire surface by a CVD method, and the insulating material layer may be etched back to form the sidewall. By forming the sidewall, the coverage of the insulating film 331 can be improved and used as a mask when the impurity region is formed. Further, the gate insulating film may be selectively removed in a self-aligning manner during the etch back. Further, the gate insulating film may be etched after the etch back. Thus, gate insulating films 310 and 316 having a total width of the width of the gate electrode and the widths of the sidewalls provided on both sides of the side wall of the gate electrode are formed. By selectively removing the gate insulating film, a contact hole can be easily formed later, and the surface area with which the insulating film 331 is in contact is increased, so that adhesion can be improved.

  Next, ion implantation is performed on the exposed silicon substrate to form a source region and a drain region. Since the CMOS is manufactured, the first element formation region in which the p-channel FET is to be formed is covered with a resist material, and arsenic (As) that is an n-type impurity is formed using the gate electrode 317 and the sidewall 318 as a mask. ) Or phosphorus (P) is implanted into the silicon substrate to form the source region 314 and the drain region 315. Further, the second element formation region in which the n-channel FET is to be formed is covered with a resist material, and boron (B), which is a p-type impurity, is implanted into the silicon substrate using the gate electrode 311 and the sidewall 312 as a mask. Thus, a source region 308 and a drain region 309 are formed.

  Next, a second activation process is performed in order to activate the ion-implanted impurities and recover crystal defects in the silicon substrate generated by the ion implantation.

  Then, after activation, an interlayer insulating film, a plug electrode, a metal wiring, and the like are formed. The first interlayer insulating film 331 is formed to a thickness of 100 to 2000 nm using a silicon oxide film, a silicon oxynitride film, or the like by using a plasma CVD method or a low pressure CVD method. Further thereon, a second interlayer insulating film 332 of phosphorus glass (PSG), boron glass (BSG), or phosphorus boron glass (PBSG) is formed. The second interlayer insulating film 332 is formed by spin coating or atmospheric pressure CVD in order to improve flatness.

  The source electrodes 333 and 335 and the drain electrodes 334 and 336 are formed after forming contact holes reaching the source and drain regions of the respective FETs in the first interlayer insulating film 331 and the second interlayer insulating film 332. Therefore, it is preferable to use aluminum (Al) which is usually used as a low resistance material. Alternatively, a stacked structure of Al and titanium (Ti) may be used.

  Although not shown here, a contact hole reaching the gate electrode is provided in the first interlayer insulating film 331 and the second interlayer insulating film 332, and a wiring provided on the second interlayer insulating film and An electrically connected electrode is formed on the first interlayer insulating film.

  Next, a porous insulating film 342 serving as a third interlayer insulating film is formed. The porous insulating film 342 is an insulating film in which minute pores isolated in the film are uniformly distributed in the film, and can be obtained by a CVD method including a plasma reaction or a spin coating method.

  Next, in accordance with the embedded wiring formation method shown in Embodiment Mode 1, etching is performed using a mask to form connection holes and wiring grooves reaching the source electrodes 333 and 335.

  Next, a barrier film to be the first conductive layer 350 is formed, and a paste containing Ag is discharged by an inkjet method. Then, a second conductive layer 351 is formed by selectively irradiating laser light and baking a paste containing Ag. Then, a third conductive layer 352 is formed so as to cover the upper surface of the second conductive layer 351. Then, by removing the mask, the barrier film and the third conductive film provided on the mask are also removed to form a buried wiring. The embedded wiring formed in this manner has a step between a surface including the upper surface of the third conductive layer 352 and a surface including the upper surface of the porous insulating film 342. In addition, a first conductive layer 350 protruding from the third conductive layer 352 is provided in the stepped portion.

  Next, a fourth interlayer insulating film 343 is formed. The fourth interlayer insulating film 343 is formed of an organic resin material with a thickness of 1 μm to 2 μm. As the organic resin material, polyimide, polyamide, acrylic, benzocyclobutene (BCB), or the like can be used. Advantages of using the organic resin film include that the film formation method is simple, that the parasitic capacitance can be reduced because the relative dielectric constant is low, and that it is suitable for planarization. Of course, organic resin films other than those described above may be used.

  Next, a contact hole reaching the third conductive layer 352 is formed, a conductive film is formed by a sputtering method, and then patterning is performed to form an electrode 353.

  Finally, a passivation film 344 that covers the electrode 353 is formed to obtain the state shown in FIG. In FIG. 4, the left side is a p-channel FET 401 and the right side is an n-channel FET 402. If these FETs are combined in a complementary manner, a CMOS circuit can be formed.

  The CMOS circuit can constitute an inverter circuit, NAND circuit, AND circuit, NOR circuit, OR circuit, shift register circuit, sampling circuit, D / A converter circuit, A / D converter circuit, latch circuit, buffer circuit, and the like. . In addition, by combining these CMOS circuits, a memory element such as SRAM and DRAM, a CPU, a controller circuit, and other integrated circuits can be configured.

  The passivation film 344 is formed of a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film by a plasma CVD method.

  In this embodiment, an example of a top gate type is shown as the structure of the FET. However, the structure of the FET is not particularly limited, and, for example, a forward stagger type FET may be used.

  According to the present invention, it is possible to realize a structure in which silver having a lower electrical resistivity than copper is used as a wiring material and a porous insulating film having a low dielectric constant is used as a material for an insulating film in which a wiring opening is formed. . Therefore, according to the present invention, a high-performance semiconductor device capable of high-speed operation can be realized.

  Further, according to the present invention, the manufacturing cost for forming the wiring can be reduced by forming the embedded wiring without using the electrolytic plating method or the CMP method.

  In the present embodiment, an example is shown in which a part of the multi-layer wiring is used as a buried wiring to reduce the resistance. However, the buried wiring may be provided in more layers.

  In addition, this embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

  A large number of integrated circuits having FETs shown in the first embodiment are formed on a semiconductor substrate and are individually separated to form a chip. Dicing is performed to separate the chips individually. Next, chips are picked up one by one from the wafer and mounted on the lead frame. Then, the electrode terminals of the chip and the inner leads of the lead frame are connected so as to be electrically connected by a gold wire having a diameter of about 20 to 30 μm. Then, it is sealed with a mold resin layer so as to facilitate handling. The leads are then solder plated to prevent rust. Next, the lead frame is cut into individual packages, and the leads are molded. Thus, packaging is performed.

  FIG. 5 is a perspective view showing a cross-sectional structure of a device in which packaging is performed. In the structure shown in FIG. 5, a chip 702 is connected to a lead frame 701 by a wire bonding method. The chip 702 is sealed with a mold resin layer 703. The chip 702 is mounted on the lead frame 701 with a mounting adhesive 704.

  The lead frame 701 is a ball grid array type provided with solder balls 705. The solder ball 705 is provided on the side of the lead frame 701 opposite to the side on which the chip 702 is mounted. The wiring 706 provided in the lead frame 701 is electrically connected to the solder ball 705 through a contact hole provided in the lead frame.

  In this embodiment, the wiring 706 for electrical connection between the chip 702 and the solder ball 705 is provided on the surface of the lead frame 701 on which the chip is mounted. It is not limited. For example, the wiring may be provided in multiple layers inside the lead frame.

  In FIG. 4, the chip 702 and the wiring 706 are electrically connected by a gold wire 707. The chip 702 is provided with a semiconductor element, and a pad is provided on the side of the chip 702 opposite to the side on which the lead frame 701 is provided. The pad is electrically connected to the semiconductor element. The pad is connected to a wiring 706 provided on the lead frame 701 by a gold wire 707.

  Further, this embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, or Embodiment 1.

  Various electronic devices can be completed by mounting an IC chip in which an integrated circuit is built using the embedded wiring of the present invention. In addition, by providing a switching element with an FET and providing a reflective electrode connected to the switching element, a display portion of the electronic device can be configured as a reflective active matrix substrate, and various electronic devices can be completed.

  For example, a display unit of an electronic device is configured as an active matrix type liquid crystal display device by using a FET as a switching element and providing a liquid crystal element by providing a pixel electrode, a liquid crystal layer, and a counter electrode connected to the switching element. Various electronic devices can also be completed.

  For example, an electron can be formed as an active matrix light-emitting device by using a FET as a switching element and providing a light-emitting element by stacking a first electrode connected to the switching element, a layer containing an organic compound, and a second electrode. A display unit of the device can be configured to complete various electronic devices.

  Such electronic devices include personal computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, etc.), video cameras, digital cameras, reflective projectors, navigation systems, sound playback devices. (Car audio, audio component, etc.), image reproducing apparatus provided with a recording medium (specifically, an apparatus including a display and an IC chip capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image) ) And the like.

  A cellular phone which is one of the electronic devices of the present invention is taken as an example, and FIG. 6A shows a state where a package is actually mounted on the electronic device.

  The cellular phone module shown in FIG. 6A includes a printed wiring board 816, CPUs 811 and 802 stacked on a memory, a power supply circuit 803, a controller 801 stacked on an audio processing circuit 829, a transmission / reception circuit 804, and the like. Elements such as a resistor, a buffer, and a capacitor are mounted. Further, the panel 800 is mounted on the printed wiring board 816 by the FPC 808. The panel 800 is provided with a pixel portion 805, a scanning line driver circuit 806 that selects a pixel included in the pixel portion 805, and a signal line driver circuit 807 that supplies a video signal to the selected pixel.

  The power supply voltage to the printed wiring board 816 and various signals input from a keyboard or the like are supplied via a printed wiring board interface unit 809 on which a plurality of input terminals are arranged. Further, an antenna port 810 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 816.

  Note that in FIG. 6A, the printed wiring board 816 is mounted on the panel 800 using FPC; however, the structure is not necessarily limited thereto. The controller 801, the audio processing circuit 829, the memory 811, the CPU 802, or the power supply circuit 803 may be directly mounted on the panel 800 using a COG (Chip on Glass) method.

  Further, in the printed wiring board 816, noise may occur in the power supply voltage or the signal, or the rise of the signal may become dull due to the capacitance formed between the drawn wirings, the resistance of the wiring itself, or the like. Therefore, by providing various elements such as a capacitor and a buffer on the printed wiring board 816, it is possible to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 6B shows an example of a module provided with an integrated circuit mounted on an FPC.

  As shown in FIG. 6B, an integrated circuit (controller 901, CPU (Central Processing unit) 902, memory 903) is mounted on the FPC 908. The panel 900 is provided with a pixel portion 905 and a driving circuit (a signal line driving circuit 907 and a scanning line driving circuit 906), and these and an external power supply (not shown) provided outside are electrically connected. An FPC 908 for connection is attached to the panel 900 with an adhesive 909. By providing an integrated circuit (a controller 901, a CPU 902, and a memory 903) using a semiconductor substrate over the FPC 908, it is possible to prevent noise from being applied to a power supply voltage and a signal and a rise of a signal from being slowed down.

  In addition, this embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 1, or Example 2.

  An IC chip in which a circuit integrated using the embedded wiring of the present invention is used as a thin film integrated circuit or a non-contact type thin film integrated circuit device (also referred to as a wireless IC tag, RFID (Radio Frequency Identification)). You can also.

  FIG. 7 shows an example of an ID card in which the IC chip 1516 of the present invention is attached to a card-like substrate 1518 provided with a conductive layer 1517 functioning as an antenna. As described above, the IC chip 1516 of the present invention is small, thin, and lightweight, realizes a wide variety of uses, and does not impair the design of the article even when attached to the article.

  Note that the IC chip 1516 of the present invention is not limited to the form of being attached to the card-like substrate 1518, and can be attached to a curved surface or an article having various shapes. For example, IC chips are bills, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc.), packaging containers (wrapping paper, bottles, etc.), recording media (DVD software, video tape, etc.) ), Vehicles (such as bicycles), personal items (such as bags and glasses), foods, clothing, daily necessities, and the like.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Example 1, Example 2, or Example 3.

Various electronic devices can be completed by mounting an IC chip in which an integrated circuit is built using the embedded wiring of the present invention. A specific example will be described with reference to FIG.

  FIG. 8A illustrates a display device, which includes a housing 1901, a support base 1902, a display portion 1903, a speaker portion 1904, a video input terminal 1905, and the like. This display device is manufactured by using an FET formed by a manufacturing method shown in another embodiment for a driving IC. The display device includes a liquid crystal display device, a light emitting device, and the like, and specifically includes all information display devices such as a computer, a television receiver, and an advertisement display.

  FIG. 8B illustrates a computer, which includes a housing 1911, a display portion 1912, a keyboard 1913, an external connection port 1914, a pointing mouse 1915, and the like. By using the manufacturing methods described in the above embodiment modes, the present invention can be applied to a driver IC for a display portion, a CPU in a main body, a memory, and the like.

FIG. 8C illustrates a mobile phone, which is a typical example of a portable information terminal. This mobile phone includes a housing 1921, a display portion 1922, a sensor portion 1924, operation keys 1923, and the like. The sensor unit 1924 includes an optical sensor element, and controls the luminance of the display unit 1922 according to the illuminance obtained by the sensor unit 1924 or controls illumination of the operation key 1923 according to the illuminance obtained by the sensor unit 1924. By doing so, the current consumption of the mobile phone can be suppressed. In the case of a mobile phone having an imaging function such as a CCD, it is detected whether or not the photographer has looked into the optical viewfinder by changing the amount of light received by the sensor unit 1924 provided near the optical viewfinder. When the photographer is looking into the optical viewfinder, power consumption can be suppressed by turning off the display portion 1922.

Since electronic devices such as PDAs (Personal Digital Assistants, information portable terminals), digital cameras, and small game machines are portable information terminals, the display screen is small. Therefore, functional circuits such as a CPU, a memory, and a sensor can be formed using the FET shown in the above-described embodiment, so that the size and weight can be reduced.

In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified. FIG. 8D illustrates a state where the wireless IC tag 1942 is attached to the passport 1941. A wireless IC tag may be embedded in the passport 1941. Similarly, you can attach or embed a wireless IC tag to a driver's license, credit card, banknote, coin, securities, gift certificate, ticket, traveler's check (T / C), health insurance card, resident card, family register copy, etc. it can. In this case, only information indicating authenticity is input to the wireless IC tag, and an access right is set so that information cannot be read or written illegally. This can be realized by using the memory shown in the other embodiments. By using it as a tag in this way, it becomes possible to distinguish it from a forged one.

In addition, a wireless IC tag can be used as a memory. FIG. 8E illustrates an example in which the wireless IC tag 1951 is used as a label attached to a vegetable package. Further, a wireless IC tag may be attached or embedded in the package itself. The wireless IC tag 1951 includes a production stage process such as production place, producer, date of manufacture, processing method, product distribution process, price, quantity, usage, shape, weight, expiration date, various authentication information, etc. Can be recorded. Information from the wireless IC tag 1951 is received and read by the antenna unit 1953 of the reader 1952 and displayed on the display unit 1954 of the reader 1952, so that it is easy for the wholesaler, retailer, and consumer to grasp. In addition, by setting access rights for each of producers, traders, and consumers, a system is incapable of reading, writing, rewriting, and erasing without access rights.

The wireless IC tag can be used as follows. At the time of accounting, the fact that accounting has been completed is entered in the wireless IC tag, and a check means is provided at the exit to check whether accounting has been written on the wireless IC tag. If you try to leave the store without checking out, an alarm will sound. This method can prevent forgetting to pay and shoplifting.

Further, in consideration of customer privacy protection, the following method can be used. At the stage of accounting at the cash register, (1) lock the data input to the wireless IC tag with a password, (2) encrypt the data itself input to the wireless IC tag, (3) wireless Either the data input to the IC tag is deleted, or (4) the data input to the wireless IC tag is destroyed. These can be realized by using the memory described in the other embodiments. Then, by providing a check means at the exit, it is checked whether any of the processes (1) to (4) has been performed, or whether the wireless IC tag data has not been processed. Check for accounting. In this way, it is possible to check whether or not there is a transaction in the store, and it is possible to prevent information on the wireless IC tag from being read outside the store against the will of the owner.

By using the present invention, a structure in which silver having a lower electrical resistivity than copper is used as a wiring material and a porous insulating film having a low dielectric constant is used as a material for an insulating film in which a wiring opening is formed is realized. Thus, the IC chip provided in the wireless IC tag can be downsized. The smaller the size of the IC chip, the higher the impact resistance, so that the reliability is improved. In addition, the embedded wiring of the present invention can reduce the manufacturing cost of the wireless IC tag by forming the embedded wiring without using an electrolytic plating method or a CMP method.

  As described above, the applicable range of the semiconductor device manufactured according to the present invention is so wide that the semiconductor device manufactured according to the present invention can be used for electronic devices in various fields.

  This embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment 1, Embodiment 2, Embodiment 3, or Embodiment 4.

By applying the present invention to the formation of a multilayer wiring of a semiconductor device, it is possible to further miniaturize and multilayer the multilayer wiring of the semiconductor device, and to further increase the integration of the semiconductor device.

  In addition, according to the present invention, since embedded wiring can be realized without using an electroplating method, a CMP method, or the like, it is possible to reduce the manufacturing cost of a semiconductor device.

4A to 4D illustrate a manufacturing process of the present invention. (Embodiment 1) 4A to 4D illustrate a manufacturing process of the present invention. (Embodiment 1) 4A to 4D illustrate a manufacturing process of the present invention. (Embodiment 2) It is sectional drawing of the manufacturing process of FET of this invention. The perspective view showing the cross-section of the device in which the package was performed. The top view which shows the example mounted in the panel module. The top view which shows the example mounted in the card | curd. FIG. 14 illustrates an example of an electronic device.

Explanation of symbols

103 Interlayer insulating film 105 Opening (trench)
107 barrier film 108 conductive Ag paste 109 conductive film 110 wiring 111 conductive Ag paste 112 interlayer insulating film 113 upper electrode 114 connection hole 201 insulating film 202 lower layer wiring 203 interlayer insulating film 205 barrier film 206 conductive Ag paste 207 Ag wiring 208 Conductive film 301 Silicon substrate 302 n-type well 303 p-type well 306 Field oxide film 307 Extension region 308 Source region 309 Drain region 310 Gate insulating film 311 Gate electrode 312 Side wall 314 Source region 315 Drain region 324 Porous insulating film 331 Interlayer insulation Film 332 Interlayer insulation film 333 Source electrode 334 Drain electrode 341 Passivation film 342 Porous insulation film 343 Interlayer insulation film 344 Passivation film 350 Conductive layer 351 Conductivity 352 conductive layer 353 electrode 401 p-channel FET
402 n-channel FET
701 Lead frame 702 Chip 703 Mold resin layer 704 Adhesive 705 Solder ball 706 Wiring 707 Gold wire 800 Panel 801 Controller 802 CPU
803 Power supply circuit 804 Transmission / reception circuit 805 Pixel portion 806 Scan line driving circuit 807 Signal line driving circuit 808 FPC
809 Interface unit 810 Antenna port 811 Memory 816 Printed wiring board 829 Audio processing circuit 900 Panel 901 Integrated circuit (controller)
902 CPU (Central Processing unit)
903 Memory 905 Pixel portion 906 Scan line drive circuit 907 Drive circuit (signal line drive circuit)
908 FPC
909 Adhesive 104a Mask 104b Mask 106a Connection hole 106b Wiring groove 1516 IC chip 1517 Conductive layer 1518 Card-like board 1901 Case 1902 Support 1903 Display 1904 Speaker 1905 Video input terminal 1911 Case 1912 Display 1913 Keyboard 1914 External connection Port 1915 Pointing mouse 1921 Case 1922 Display unit 1923 Operation key 1924 Sensor unit 1941 Passport 1942 Wireless IC tag 1951 Wireless IC tag 1952 Reader 1953 Antenna unit 1954 Display unit 204a Connection hole 204b Wiring groove 311a Polysilicon layer 311b Silicide layer

Claims (15)

In a semiconductor device having an integrated circuit and a plurality of wiring layers,
A porous insulating film, and a first conductive layer in contact with an inner wall of a wiring groove and a connection hole formed in the porous insulating film;
A second conductive layer formed on and in contact with the first conductive layer;
A wiring layer comprising a laminate with a third conductive layer formed on the second conductive layer and in contact with the first conductive layer;
The second conductive layer is surrounded by the first conductive layer and the third conductive layer, and includes a first surface including an upper surface of the porous insulating film and a second surface including an upper surface of the third conductive layer. Has a step between the surface and
The first conductive layer has a hole with a hole of the porous insulation film has been transferred,
Said second conductive layer is viewed write enters the hole which is the transfer,
2. A semiconductor device according to claim 1, wherein the material of the second conductive layer is a paste containing metal particles .   2. The semiconductor device according to claim 1, wherein the porous insulating film is a material containing silicon oxide.   3. The semiconductor device according to claim 1, wherein the first conductive layer is a material including one or more selected from W, Mo, Ti, Cr, and Ta.   4. The semiconductor device according to claim 1, wherein the third conductive layer is a material including one or more selected from W, Mo, Ti, Cr, and Ta. .   5. The semiconductor device according to claim 1, wherein the second conductive layer is made of a material containing silver.   6. The semiconductor device according to claim 1, wherein the second conductive layer is a material containing a resin.   7. The semiconductor device according to claim 1, wherein the integrated circuit includes at least one of a controller, a CPU, and a memory. Forming a porous insulating film;
Forming a mask on the porous insulating film;
Selectively etching to form an opening in the porous insulating film;
Forming a first conductive film on the mask and in the opening;
Dropping a droplet containing a conductive material on the first conductive film in the opening by a droplet discharge method;
Forming a second conductive layer by selectively irradiating laser light to heat the conductive material;
Forming a third conductive film on the mask and the second conductive layer;
Removing the mask and simultaneously removing the first conductive film and the third conductive film formed on the mask to form a first conductive layer and a third conductive layer. There,
The first conductive film has holes to which the holes of the porous insulating film are transferred,
Said second conductive layer is viewed write enters the hole which is the transfer,
The method for manufacturing a semiconductor device, wherein the conductive material is a paste containing metal particles . Forming a porous insulating film;
Selectively etching to form an opening in the porous insulating film;
Forming a first conductive film on the porous insulating film and in the opening;
Dropping a droplet containing a conductive material onto the opening and the first conductive film around the opening by a droplet discharge method, and baking to form a second conductive film;
Selectively etching the second conductive film to form a second conductive layer;
Forming a third conductive film on the first conductive film and on the second conductive layer;
Etching the first conductive film and the third conductive film using the same mask to form a first conductive layer and a third conductive layer;
Performing a surface treatment to reduce the contact angle of the droplet before dropping the droplet on the opening and the first conductive film around the opening;
The first conductive film has holes to which the holes of the porous insulating film are transferred,
Said second conductive layer is viewed write enters the hole which is the transfer,
The method for manufacturing a semiconductor device, wherein the conductive material is a paste containing metal particles . Forming a porous insulating film;
Forming a mask on the porous insulating film;
Selectively etching to form an opening in the porous insulating film;
Forming a first conductive film on the mask and in the opening;
Dropping a droplet containing a conductive material on the first conductive film in the opening by a droplet discharge method;
Forming a second conductive layer by selectively irradiating laser light to heat the conductive material;
Forming a third conductive film on the mask and the second conductive layer;
Removing the mask and simultaneously removing the first conductive film and the third conductive film formed on the mask to form a first conductive layer and a third conductive layer. There,
Performing a surface treatment to reduce the contact angle of the droplet before dropping the droplet on the opening and the first conductive film around the opening;
The first conductive film has holes to which the holes of the porous insulating film are transferred,
Said second conductive layer is viewed write enters the hole which is the transfer,
The method for manufacturing a semiconductor device, wherein the conductive material is a paste containing metal particles .   11. The method for manufacturing a semiconductor device according to claim 9, wherein the surface treatment is ultraviolet irradiation, plasma treatment using a gas of oxygen, argon, hydrogen, or helium or corona discharge treatment.   12. The method for manufacturing a semiconductor device according to claim 8, wherein the insulating film is made of a material containing silicon oxide.   The first conductive layer and the third conductive layer according to any one of claims 8 to 12, wherein the first conductive layer and the third conductive layer are made of one or a plurality selected from W, Mo, Ti, Cr, or Ta obtained by a sputtering method. A method for manufacturing a semiconductor device, comprising: a layer including a semiconductor layer.   14. The method for manufacturing a semiconductor device according to claim 8, wherein the second conductive layer is a material containing silver.   The method for manufacturing a semiconductor device according to claim 8, wherein the second conductive layer is a material containing a resin.

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