JP4871933B2 - Receiver and receiving channel switching method in receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accomplish a receiver capable of suppressing low the influence of interference wave and attaining power saving, regarding a receiver of a keyless entry system or immobilizer system. <P>SOLUTION: A detection circuit 122 demodulates a signal of one reception channel set by a main CPU 13 and a self-polling function circuit 123 is intermittently activated in an interval T1, determines whether or not the signal of the reception channel from the detection circuit 122 is an activation signal and outputs an interrupt signal instructing clock switching to the main CPU 13 if the signal is the activation signal. Until the activation signal is received by the self-polling function circuit 123, the main CPU 13 is operated by a sub clock of low frequency but after the interrupt signal is given, the main CPU 13 is operated by a main clock of high frequency, determines a reception status of the reception channel at present and switches the reception channel to another reception channel if the reception status is adverse. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a receiver that receives a signal transmitted from a transmitter using a plurality of channels in a vehicle communication device by switching channels.

  A keyless entry system that locks / unlocks a vehicle door by remote control operation from a portable device, and an immobilizer system that can start an engine by electronic key verification are known. The keyless entry system or immobilizer system includes a transmitter (portable device) that transmits data and a receiver (vehicle-mounted device) that receives data transmitted from the transmitter and performs predetermined processing. Since the transmitter operates by user operation, it is not always necessary to save power when not in use, but the receiver needs to be able to receive data transmitted from the transmitter at any time. It is necessary to save power when not receiving.

  FIG. 6 is a block diagram showing a schematic configuration of a conventional receiver that saves power during standby. The receiver shown in FIG. 6 includes a receiving IC (Integrated Circuit) 100, a main CPU (Central Processing Unit) 105, a sub-clock unit 106 that supplies a low-speed sub clock (32 kHz), and a high-speed main clock (16 MHz). The main clock unit 107 that supplies the main component is configured as a main component. The reception IC 100 includes a detection circuit 101, a timer 102, a determination circuit 103, and a self polling function circuit 104.

  The timer 102 and the determination circuit 103 are connected to the detection circuit 101. As shown in the waveform diagram of FIG. 7, the detection circuit 101 is intermittently activated based on time information from the timer 102. The determination circuit 103 takes in the reception data detected by the detection circuit 101 when the detection circuit 101 is activated, and determines whether or not an activation signal composed of data of a specific data rate, such as a rectangular pulse of several pulses, is received. The power consumption is suppressed because it is determined, and A / D (Analog to Digital) conversion is not performed. If the activation signal is not received, the detection circuit 101 is set in the sleep state, and the operation is repeated thereafter until the activation signal is received. When the activation signal is received, the detection circuit 101 is maintained in the activated state and the main CPU 105 is activated. The main CPU 105 is activated by the self-polling function circuit 104. The main CPU 105 can input and determine a start signal in the sub-clock state, and can switch the clock. Therefore, when the activation signal is input, the operation clock is switched from the sub clock (32 kHz) to the main clock (16 MHz), the operation is started at a high speed, and the data signal following the activation signal is received. When the main CPU 105 shifts to the standby state, the main CPU 105 switches from the main clock to the sub clock. The detection circuit 101 is intermittently activated, and the main CPU 105 operates with the main clock when the determination circuit 103 determines that it has received the activation signal and is activated by the self-polling function circuit 104. As a result, power saving during standby can be achieved.

  Incidentally, since the receiver shown in FIG. 6 employs a method of receiving one type of signal (that is, a signal of one channel), there is a possibility that it cannot be received when there is an interference wave. It is necessary to prevent a period during which data cannot be received due to an interference wave. In order to avoid this problem, there is a proposal for switching and receiving a plurality of signals having different frequencies (see, for example, Patent Document 1).

  FIG. 8 is a schematic configuration diagram of a receiver configured to switch and receive a plurality of signals having different frequencies. The receiver shown in FIG. 8 includes a receiving IC 200 and a main CPU 204. The reception IC 200 includes a detection circuit 201, a timer 202, and a determination circuit 203. Note that a transmitter (not shown) switches the two channels (channel CH1 and channel CH2) having different frequencies and transmits the same signal as data. The detection circuit 201 has a PLL (Phase Locked Loop) 205, and a reception channel can be set. Since the PLL 205 determines the local oscillation signal, the main CPU 204 sets the channel CH1 and the channel CH2 for the PLL 205.

  When the receiver is always in an activated state and does not receive a signal, as shown in FIG. 9, it is periodically confirmed whether or not CH switching is necessary based on time information from the timer 202. In this confirmation, the channel CH1 and channel CH2 are switched and received and the channel with the smaller signal strength received is judged to have less noise and set as the reception channel, and the transmitter uses the channel with less noise. Request to send When the signal is received and the code is determined and cannot be determined, the CH is switched. That is, the main CPU 204 is always activated. This is because the reception channel is switched by checking the strength by A / D conversion, setting and switching the reception channel for the PLL 205, and determining whether the code is a predetermined code after setting the reception channel. is there. Patent Document 1 also discloses a configuration in which a transmitter transmits by switching the frequencies of two channels, CH1 and CH2, and switches between two channels, CH1 and CH2.

In this way, by selecting and transmitting a channel with less noise, or by receiving transmission data from a transmitter on two reception channels, even if reception of data fails on one reception channel, the other reception channel Can receive data, and the influence of jamming waves can be kept low.
JP 2008-101344 A

However, the receiver described in Patent Document 1 described above can suppress the influence of the interference wave by switching and receiving a plurality of signals having different frequencies, but it always activates the main CPU. There is a problem that power consumption is increased as compared with a receiver for one channel.
Note that when the receiver is operated intermittently to switch and receive the frequencies of the two channels CH1 and CH2 during one activation, the influence of the interference wave is suppressed and at the same time described in Patent Document 1. It is possible to reduce power consumption compared to the above technology. However, it is necessary to operate the main CPU with the main clock every time intermittent reception is performed, and by setting the channel of the receiving circuit and determining whether the code is a predetermined code or not, the power consumption can be sufficiently reduced. There is a problem that is difficult.

  The present invention has been made in view of such a point, and an object of the present invention is to provide a receiver that can suppress the influence of an interference wave and reduce power consumption.

  The receiver of the present invention includes a receiving circuit capable of setting a plurality of receiving channels, a detecting circuit for demodulating a signal output from the receiving circuit, and a signal having a predetermined pattern at the detecting circuit output while the receiving channel is fixed. A sub-control circuit that intermittently determines whether or not a signal is included and outputs an interrupt signal if a signal of a predetermined pattern is included, and until the interrupt signal is input from the sub-control circuit Is in a sleep state with a low operation clock frequency, and when a predetermined time longer than the intermittent period elapses, it enters a start state with a high operation clock frequency to determine the reception status in the current reception channel, and the reception according to the reception status And a main control circuit for setting another reception channel in the circuit.

  The reception channel switching method in the receiver of the present invention includes a step of receiving a transmission signal transmitted from a transmitter using a plurality of channels, a step of demodulating a signal received on a current reception channel, and a reception channel. Whether or not a signal of a predetermined pattern is included in a signal demodulated with the signal fixed and intermittently determined at a predetermined intermittent period, and if a signal of a predetermined pattern is included, outputting an interrupt signal; Until the interrupt signal is output, the main control circuit is in a sleep state, and when a time longer than the intermittent period elapses, the main control circuit is activated to determine the reception status of the current reception channel, and there is a reception signal. And a step of setting another reception channel if the predetermined pattern cannot be identified.

  According to this configuration, the main control circuit is set to the sleep state, intermittent reception operation is performed on one reception channel, and when the time longer than the intermittent period elapses, the main control circuit is started and the reception status on the current reception channel is determined. Therefore, if the reception status in the current reception channel is bad, it can be switched to another reception channel, the influence of the interference wave can be suppressed low, and power saving can be achieved.

  In the receiver, when the main control circuit determines the reception status in the current reception channel, the reception signal cannot be determined as a predetermined signal in the reception channel, and the reception quality and threshold value of the reception signal in the reception channel are determined. If the reception quality is equal to or lower than the threshold value, another reception channel may be set in the reception circuit.

  ADVANTAGE OF THE INVENTION According to this invention, while being able to suppress the influence of an interference wave low, the receiver which can aim at power saving can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing a schematic configuration of a receiver according to an embodiment of the present invention.
The receiver 1 of the present embodiment intermittently receives a transmission signal transmitted by switching two channels (channel CH1 and channel CH2) from the transmitter at a predetermined cycle. The receiver 1 includes an antenna 10, a filter 11, a receiving IC 12, a main CPU 13, a second timer 14, a 16 MHz main clock unit 15, and a 32 kHz sub clock unit 16. The reception IC 12 includes a reception circuit 121, a detection circuit 122, a self-polling function circuit 123 serving as a sub-control circuit, and a first timer 124. The reception circuit 121 includes a mixer 1211, a VCO (Voltage Controlled Oscillator). ) 1212, PLL 1213, and IF (Intermediate Frequency) filter 1214.

  The filter 11 is a band filter including the frequencies of the channels CH1 and CH2, and allows the signals of the channels CH1 and CH2 among the signals input from the antenna 10 to pass therethrough. The receiving IC 12 receives the signal of the receiving channel set in the receiving circuit 121, demodulates it by the detection circuit 122, and outputs it to the main CPU 13. In the receiving circuit 121, the oscillation frequency of the VCO 1212 is controlled in accordance with channel data given to the PLL 1213. Note that the channel data given to the PLL 1213 is stored in a memory (not shown) and operates with the CH data until the next channel data is given and rewritten. The mixer 1211 mixes the local oscillation signal input from the VCO 1212 and the reception signal that has passed through the filter 11 and converts it into an IF signal of the reception channel. The IF signal of the reception channel is extracted by the IF filter 1214 and input to the detection circuit 122. The frequency converted into the IF signal is determined by the frequency of the local oscillation signal input to the mixer 1211. When the channel data for receiving the signal of the reception channel CH1 is set in the PLL 1213, the reception circuit 121 operates to convert the IF signal of the reception channel CH1 and receives the signal of the reception channel CH2. When the channel data is set in the PLL 1213, it operates so as to convert it to the IF signal of the reception channel CH2. The detection circuit 122 demodulates the signal of one reception channel received by the reception circuit 121 and outputs the demodulated signal to the self-polling function circuit 123 and to the main CPU 13. The main CPU 13 can input and determine a start signal in the sub clock state, and can switch the clock.

  In a state where no signal is received, the self-polling function circuit 123, the first timer 124, and the second timer 14 are always in an operating state, and the CPU 13 is operated by the sub clock 16. The reception circuit 121 and the detection circuit 122 are intermittently activated based on time information from the first timer 124. That is, the activation state is entered in the section T1 shown in FIG. 2, and the sleep state is entered in the section T2. The first timer 124 is used to time the activation period T1 and the sleep period T2 (intermittent reception interval). The self-polling function circuit 123 determines whether a signal output from the detection circuit 122 is a start signal of a predetermined signal pattern when the reception circuit 121 and the detection circuit 122 are in a start state, and when the start signal is detected The receiver circuit 121 and the detector circuit 122 are maintained in the activated state for a predetermined period, and an interrupt signal for instructing the main CPU 13 to switch the clock is output, and the data signal transmitted following the activation signal is subjected to a predetermined process. As in the conventional example, the self-polling function circuit 123 determines whether or not an activation signal made up of data of a specific data rate, such as a rectangular pulse of several pulses, has been received. A / D (Analog to Digital ) Power consumption is reduced because no conversion is performed. The data signal is composed of a command signal for collecting lock / unlock / lock / unlock information and the ID of the portable device that has transmitted the transmission signal. The main CPU 13 is the main clock and determines what the command signal is. Also, authentication such as whether the ID is a predetermined ID is performed. The data signal is not limited to this.

  The main CPU 13 operates with a sub-clock having a low frequency until a start signal is given from the self-polling function circuit 123, and operates with a main clock having a high frequency when an interrupt signal is given from the self-polling function circuit 123. Further, as shown in FIG. 2, the main CPU 13 rises at a cycle T3 sufficiently longer than the intermittent reception cycle (T1 + T2) of the self-polling function circuit 123 based on the time information from the second timer 14, and operates with the main clock. Then, the reception status on the current reception channel is determined. Here, the period T3 at which the main CPU 13 rises autonomously is about several times the intermittent reception period (T1 + T2), and is synchronized with the activation timing of the reception circuit 121 and the detection circuit 122. The main CPU 13 switches to the main clock and starts operation when the time T3 has passed without receiving an interrupt signal from the self-polling function circuit 123. Then, it is determined whether the current reception channel is a predetermined code. If it is determined that the code is not the predetermined code, the reception quality is determined. If the reception quality is equal to or less than the threshold, the reception channel is switched to another reception channel. . If the noise is above a predetermined level, it is determined that the reception quality is below the threshold. Specifically, the predetermined code cannot be detected, the RSSI value is higher than the predetermined value, and the SN ratio is lower than the predetermined value. In addition, it is determined that the reception quality is equal to or lower than the threshold value. The reception channel switching is realized by the reception channel switching circuit 131 in the main CPU 13 generating channel data and setting it in the PLL 1213 of the reception circuit 121. As the period T3 is longer, the number of activations of the main CPU 13 can be reduced, so that power consumption can be reduced.

  FIG. 3 is a schematic configuration diagram of a transmitter provided in a portable device that performs data transmission to the receiver 1 through the channels CH1 and CH2. The transmitter 2 includes an antenna 20, a power amplifier 21, an oscillator 22, a PLL phase synchronization circuit 23, a CPU 24, a reference oscillator 25, and a division period 26. In response to a switch operation (not shown), the CPU 24 sequentially outputs, for example, 100 MHz PLL data or 102 MHz PLL data as 100 MHz and 102 MHz channel setting signals. The PLL phase synchronization circuit 23 compares the signal obtained by dividing the output of the oscillator 22 by the dividing period 26 with the signal of the reference oscillator 25 set to a predetermined frequency, and supplies the voltage or the voltage to the oscillator 22 so that the values match. Gives current output. In the division period 26, a signal is output from the PLL phase synchronization circuit 23 in accordance with the channel setting signal from the CPU 24, and the frequency division number changes. That is, the transmission channel is set from the CPU 24 to the PLL phase synchronization circuit 23. According to the signal output from the PLL phase synchronization circuit 23, 100 MHz and 102 MHz channel CH1 and channel CH2 signals are obtained from the oscillator 22, and these signals are amplified by the power amplifier 21 and continuously output from the antenna 20. The As described above, the transmission signal transmitted from the transmitter 2 is composed of the activation signal composed of the preamble signal and the data signal. However, the transmission signal is not limited to this, and the activation signal transmission section in one channel is the receiver 1. It is desirable to make it longer than the intermittent reception cycle. Note that the method of transmitting signals of two frequencies from the transmitter is not limited to the above circuit, and other known circuits may be used.

  The receiver 1 of the present embodiment receives one of the transmission signals of the channel CH1 and the channel CH2 that are continuously transmitted from the transmitter 2. That is, for example, when the reception channel CH1 is set, the signal of the channel CH1 from the transmitter 2 is intermittently received.

  Next, the operation of the receiver 1 of the present embodiment will be described with reference to the flowchart shown in FIG. First, the receiving channel CH1 is set (step S1). In the example shown in FIG. 4, channel CH1 is set as the reception channel. The channel switching unit 131 of the main CPU 13 transmits channel data to the PLL 1213 of the receiving IC 12 and sets an oscillation frequency at which the receiving channel CH1 can be received (step S2). As a result, the reception IC 12 can receive the signal of the reception channel CH1. After setting the reception channel CH1 in the PLL 1213 of the reception IC 12, the CPU 13 sets the reception circuit 121 and the detection circuit 122 of the reception IC 12 to the sleep state at the point A in FIG. 2, resets the first timer 124 to zero, and sets the first timer 124 to zero. The time measurement of (T2) is started by one timer 124 (step S3). Following the start of the first timer 124, the main CPU 13 is set to the sub clock mode, the second timer 14 is reset to zero, and the time measurement of T3 is started by the second timer 14 (step S4).

  After starting the second timer 14, it is determined whether or not the count value of the first timer 124 is equal to T2 (step S5), and if it is equal to T2, the reception circuit 121 and the detection circuit 122 of the reception IC 12 are set to sleep. The state is switched to the activated state (step S6). Then, a signal is received on the reception channel CH1 until T1 elapses from the start of activation (step S7), and it is determined whether an activation signal is received (step S8). That is, when activated by intermittent reception, it is determined whether or not the signal of the reception channel CH1 output from the detection circuit 122 is an activation signal of data (predetermined signal pattern) at a specific data rate. When data (start-up signal) at a specific data rate is received, an interrupt signal for instructing the main CPU 13 to switch the clock is output (step S9). When an interrupt signal is output to the main CPU 13, the main CPU 13 is activated to switch the clock from the low-frequency subclock to the high-frequency main clock, and the data signal transmitted following the activation signal is transmitted with the high-speed clock. A reception operation for determining whether or not the data signal is a predetermined data signal is started (step S10). As described above, when the activation signal can be normally received on the initially set reception channel CH1, the main CPU 16 can be activated by the activation signal without switching the reception channel. For this reason, at the time of intermittent reception, power saving can be achieved compared to the case where the main CPU 13 is activated to switch to two channels for reception.

  When the activation signal is not received during the intermittent reception operation period of T1, the process proceeds from step S7 to step S3, and enters the sleep state until the next intermittent reception timing.

  Here, there are two factors that prevent the activation signal from being received during the intermittent reception operation period. One is a case where the transmitter 2 is not transmitting a transmission signal, and the other is that there is noise or the like in the reception channel CH1 set first, and the activation signal is normal only by intermittent reception of one reception channel CH1. This is the case when it cannot be received.

In the present invention, the main CPU 13 is activated at a period T3 that is sufficiently longer than the intermittent reception period so as to appropriately switch the reception channel in the latter case without increasing the power consumption, and the reception state on the current reception channel is determined. Whether or not it is necessary to switch the reception channel is determined from the reception status. That is, if the activation signal is not received even if intermittent reception is repeated a plurality of times on one reception channel CH1, the intermittent reception is repeated until the time of the second timer 14 cleared to zero simultaneously with the first timer 124 reaches time T3 (step S15) When T3 is reached, the main CPU 13 is set to the main clock mode (step S16). That is, the main CPU 13 is started up once with a long cycle of T3 and is operated with the main clock 15. The main CPU 13 determines whether or not there is a reception signal on the current reception channel CH1, that is, whether or not the data signal transmitted following the activation signal is a signal of a predetermined code (step S10). When the transmitter 2 transmits a signal on the same channel as the current reception channel CH1, noise that cannot be distinguished from the activation signal at the same frequency as the CH1 and data of a specific data rate may overlap. In this case, it is impossible to determine whether the data is a predetermined code due to the influence of noise, and a received signal having a certain magnitude is detected. Therefore, when a received signal is detected, an RSSI value is further measured as reception quality, and the RSSI value is compared with a threshold value (step S12). When the RSSI value is larger than the threshold value, there is a high possibility that the data signal is not normally received due to the influence of noise, so the current reception channel CH1 is switched to another reception channel CH2 (step S13). The reception channel switching circuit 131 inputs the channel data of the channel CH2, which is the reception channel to be changed, to the PLL 1213 and switches from the reception channel CH1 to the reception channel CH2 (step S14). If the RSSI value is smaller than the threshold value in step S12, it is assumed that only noise having the same specific data rate as the activation signal has been received, and the process returns to step S3.
As described above, when there is noise during intermittent reception of the activation signal and it cannot be distinguished from the activation signal, the activation signal and the data signal are determined by channel switching. If there is no noise during intermittent reception of the activation signal, or data of a specific data rate that can be identified from the activation signal and cannot be identified by noise or the like in the determination of the data signal, the channel is immediately switched.
If it is a predetermined data code in step S10, that is, if it is a predetermined ID and includes a predetermined command signal, in step S11, for example, lock, unlock or lock unlock is performed according to the command signal. A signal for detecting the state is output, and processing according to the signal transmitted from the transmitter is performed.
When the timer reaches time T3 and the main CPU 13 is set to the main clock mode, it is determined whether the data code is a predetermined data code in step S10 regardless of how much noise is superimposed on the activation signal. .

  As described above, according to the present embodiment, when one channel is intermittently received at a short cycle (T1 + T2) and the activation signal is not received by intermittent reception, the main channel is cycled at a cycle T3 that is sufficiently longer than the intermittent reception cycle. Since the CPU 13 is activated to switch to another reception channel if the reception quality of the current reception channel is equal to or lower than the threshold value, the influence of the interference wave can be suppressed to a low level and power saving can be achieved.

  In the embodiment described above, the receiver 1 may have a transmission function to transmit the vehicle state (for example, door lock / unlock information) to the transmitter 2 side. Or you may make it give the function equivalent to the receiver 1 to the transmitter 2 mentioned above.

In the embodiment described above, a plurality of reception channels CH1 and CH2 can be set by controlling the frequency of the local oscillation signal mixed with the reception signal by the PLL 1213 of the reception IC 12. However, as shown in FIG. A dedicated receiving circuit may be provided corresponding to the channel CH2.
In step S16, the main CPU 13 is set to the main clock mode, and determines whether a predetermined code can be received on the current reception channel (step S10) and whether the reception quality is equal to or lower than a predetermined value (step S12). If the reception status is not determined and the reception quality is below the threshold value, the channel is changed, and another reception channel is set in the reception circuit according to the reception status. The determination of the situation may be only the determination of whether the code is a predetermined code. In addition, the switching of the reception channel of the reception circuit according to the reception status may be performed immediately when the predetermined code is not determined without considering the reception quality.

  The receiver 3 shown in FIG. 5 includes an antenna 30, a switch 31, filters 32 and 33, receiving ICs 34 and 35, a switch 36, a main CPU 37, a second timer 38, and a 16 MHz main clock unit. 39 and a sub-clock unit 40 of 32 kHz. The filter 32 on the channel CH1 side is configured by a band filter that allows the signal of the channel CH1 to pass therethrough, and the filter 33 on the channel CH2 side is configured by a bandpass filter that allows the signal of the channel CH2 to pass. The reception IC 34 receives the signal of the reception channel CH1, and the reception IC 35 receives the signal of the reception channel CH2. The switches 31 and 36 work together to switch to the filter 32 and the reception IC 34 when receiving the signal of the reception channel CH1, and to the filter 33 and the reception IC 35 when receiving the signal of the reception channel CH2. The reception IC 34 includes a reception circuit 341, a detection circuit 342, a first timer 343, and a self polling function circuit 344. The reception IC 35 includes a reception circuit 351, a detection circuit 352, a first timer 353, and a self polling function circuit 354.

  When the reception channel CH1 side is selected, the self-polling function circuit 344 of the reception IC 34 is intermittently activated based on the time information from the first timer 343. The self-polling function circuit 344 determines whether or not the reception channel signal output from the detection circuit 342 in the activated state is an activation signal having a predetermined signal pattern. To output an interrupt signal instructing clock switching. The main CPU 37 operates with the subclock 40 having a low frequency until the activation signal is received by the self polling function circuit 344, and operates with the main clock 39 having a high frequency when an interrupt signal is given from the self polling function circuit 343. Further, the main CPU 37 is activated at a period T3 longer than the intermittent reception period based on the time information from the second timer 38 and operates with the main clock. Also, the main CPU 37 determines the reception status of the current reception channel, and switches the current reception channel to another reception channel if the reception status is bad.

  When the reception channel CH2 side is selected, the self-polling function circuit 354 of the reception IC 35 is intermittently activated based on the time information from the first timer 353. The self-polling function circuit 354 determines whether or not the signal of the reception channel output from the detection circuit 352 in the activated state is an activation signal having a predetermined signal pattern. To output an interrupt signal instructing clock switching. The main CPU 37 operates with the subclock 40 having a low frequency until the activation signal is received by the self polling function circuit 354, and operates with the main clock having a high frequency when the interrupt signal is given from the self polling function circuit 353. Further, the main CPU 37 determines the reception status of the current reception channel, and switches the reception IC 35 to another reception IC 34 if the reception status is bad.

  In this way, by providing dedicated reception circuits corresponding to the channels CH1 and CH2, processing for setting a reception channel from the main CPU 37 to the reception circuit (PLL) becomes unnecessary.

  The present invention is applicable to a receiver in a keyless entry system, an immobilizer system, or the like.

The block diagram which shows schematic structure of the receiver which concerns on one embodiment of this invention Waveform diagram showing the activation state of the receiver of FIG. The block diagram which shows schematic structure of the transmitter which transmits data with respect to the receiver of FIG. Flow chart for explaining the operation of the receiver of FIG. The block diagram which shows schematic structure of the application example of the receiver of FIG. Block diagram showing schematic configuration of a conventional receiver Waveform diagram showing the startup state of the receiver of FIG. Block diagram showing schematic configuration of another conventional receiver Waveform diagram showing the activation state of the receiver of FIG.

Explanation of symbols

1 receiver
2 Transmitter 10 Antenna
11 Filter 12 Receiver IC
13 Main CPU
14 Timer
15 Main clock 16 Sub clock
20 antenna 21 power amplifier
22 Oscillator 23 PLL phase lock circuit
24 CPU
30 Antenna
31 switcher 32, 33 filter
34, 35 Receiver IC
36 selector
37 Main CPU
38, 343, 353 Timer
39 Main clock 40 Sub clock
121 receiving circuit 122 detecting circuit
123, 344, 354 Self-polling function circuit 124 Timer
131 Reception channel switching circuit 341, 351 Reception circuit
342, 352 detector circuit 1211 mixer
1212 VCO
1213 PLL
1214 IF filter

Claims (3)

A receiving circuit capable of setting a plurality of receiving channels;
A detection circuit that demodulates a signal output from the reception circuit;
A sub-routine that intermittently determines whether or not a predetermined pattern signal is included in the detection circuit output with the reception channel fixed, and outputs an interrupt signal if a predetermined pattern signal is included. A control circuit;
Until the interrupt signal is input from the sub-control circuit, the sleep state has a low operation clock frequency. When a predetermined time longer than the intermittent period elapses, the sleep state becomes a high operation clock frequency and reception on the current reception channel. A main control circuit for determining a situation and setting another reception channel in the reception circuit according to a reception situation;
A receiver comprising:   When the main control circuit determines the reception status in the current reception channel, the main control circuit cannot determine the reception signal in the reception channel as a predetermined signal, and compares the reception quality of the reception signal with the threshold in the reception channel. The receiver according to claim 1, wherein if the reception quality is equal to or less than a threshold value, another reception channel is set in the reception circuit. Receiving a transmission signal transmitted from a transmitter using multiple channels;
Demodulating the signal received on the current receiving channel;
A step of intermittently determining whether or not a signal of a predetermined pattern is included in a demodulated signal with the reception channel fixed, and outputting an interrupt signal if the signal of the predetermined pattern is included When,
Until the interrupt signal is output, the main control circuit is in a sleep state, and when a time longer than the intermittent period elapses, the main control circuit is activated to determine the reception status of the current reception channel, and there is a reception signal. And, if it cannot be distinguished from the predetermined pattern, setting another receiving channel;
A receiving channel switching method in a receiver.

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