JP4868380B2 - Variable capacitance circuit and integrated circuit including the same - Google Patents

Description

  The present invention relates to a variable capacitance circuit and an integrated circuit including the same.

  As a technique for switching the amplification gain of the voltage amplification circuit, for example, there is a technique for switching the amplification gain by switching the input capacitance of the voltage amplification circuit (Patent Document 1). A variable gain amplifier according to this technique is shown in FIG.

  The variable gain amplifier shown in FIG. 10 has a coupling capacitor 10 having one end connected to a signal input terminal Ti, and a pair of open / close switches (N-MOS) having a first contact (source or drain) connected to the other terminal of the capacitor 10. Transistors) 92, 94, capacitors 91, 93 inserted between the second contacts of the respective open / close switches 92, 94 and the ground conductor, inverters 321, 323 connected in series, and open / close switches 92, 94 The amplifier circuit 940 has an input terminal connected to a node 950 to which one contact is connected. The input terminal of the amplifier circuit 940 is the gate of the N-MOS transistor 943 for amplification, and the drain of the transistor 943 is connected to the output terminal To. A gain switching signal is input to the input terminal of the inverter 321, and the output terminals of the inverters 321 and 323 are connected to the control terminals (gates) of the switches 92 and 94, respectively.

  In this circuit, by switching the gain switching signal, only one of the ungrounded terminals of the capacitors 91 and 93 whose one end is grounded can be connected to the node 950. The capacitance between the node 950 and the ground conductor (in this case, the capacitance of the capacitors 91 and 93 that is coupled to the node 950) is denoted by C2, and the parasitic capacitance between the source and gate of the transistor 943 that performs amplification and If the drain-gate parasitic capacitances are Csg and Cdg, respectively, and the gain of the amplification transistor 943 is α, the voltage amplification gain β from the input terminal Ti to the output terminal To is approximately expressed by the following equation.

β = α · C1 · C1 · (C2 + Cgd + Csg) / (C2 + α · Cgd + Csg) (1)
Therefore, as the capacitance C2 between the node 950 and the ground conductor increases, the amplification gain β decreases. Therefore, the gain β of the amplifier circuit can be changed by changing the capacitance C2.

JP 2003-17959 A (pages 4-5, FIGS. 1, 5, 6)

  However, the method described above requires a capacitor for each selectable gain value (ie, the capacitance value of node 950 and the ground conductor). For this reason, if a large number of gain values are to be realized, the layout area on the IC chip increases according to the number of capacitors.

  The present invention has been made to solve the above problems, and an object thereof is to provide a variable capacitance circuit and an integrated circuit that can reduce a layout area.

  According to one aspect of the present invention, an input conductor that is electrically coupled to one end of a coupling capacitor and carries an input signal arriving through the coupling capacitor, and an electronic circuit that is connected to the input conductor and processes the input signal In addition, in an integrated circuit in which a reference voltage source that applies a predetermined DC voltage to the input conductor is integrated, a variable capacitance circuit that is connected in parallel with the reference voltage source and provides a switchable capacitance is obtained. The variable capacitance circuit includes a MOS capacitor whose capacitance changes according to an applied voltage, and a variable voltage source connected in series to the MOS capacitor and providing an output voltage corresponding to a given control signal.

  Further, according to another aspect of the present invention, an input conductor that is electrically coupled to one end of the coupling capacitor and transmits an input signal coming through the coupling capacitor, and an electronic circuit that is connected to the input conductor and processes the input signal And a reference voltage source that applies a predetermined DC voltage to the input conductor and a variable capacitance circuit that is connected in parallel to the reference voltage source and provides a switchable capacitance can be obtained. This variable capacitance circuit is the same as that described in the previous stage.

  Therefore, according to the present invention, different capacitances can be given to the input conductor of the electronic circuit mounted on the integrated circuit by one MOS capacitor.

  In general, a MOS capacitor exhibits a first constant capacitance (Ca) when the applied voltage is in a first region (low-capacity operating region) lower than the first negative threshold voltage (−Vca), and the applied voltage is When in the second region (high capacity operation region) higher than the second positive threshold voltage (Vcb), it exhibits a second constant capacity (Cb) higher than the first constant capacity (Ca). The control signal is a binary signal, and in response to the control signal, the variable voltage source outputs either the first voltage (VL) or the second voltage (VH) different from the first voltage. To do. At this time, the first voltage (VL) is set so that the applied voltage falls within the first region regardless of the change of the input signal, and the second voltage is the applied voltage regardless of the change of the input signal. It is preferable to set so as to be within the second region. With this configuration, two types of capacitors can be stably obtained regardless of the input signal.

  Specifically, the first voltage (VL) and the second voltage (VH) are set in the ranges of the following expressions (2) and (3).

  In a preferred embodiment, the variable voltage source includes a first voltage source that provides a first voltage, a second voltage source that provides a second voltage, and the first voltage source and the second voltage source in response to a control signal. A two-select switch circuit for connecting only one of the voltage sources to the MOS capacitor.

  The variable capacitance circuit may further include open / close switch means that is inserted between the series circuit of the MOS capacitor and the variable voltage source and the input conductor and opens / closes in response to the second binary control signal. As a result, the capacitance can be switched in three stages including 0 with one MOS capacitor.

  If the electronic circuit is an amplification circuit, the gain of the amplification circuit can be switched in accordance with the switching of the input capacitance, as given by equation (1).

  Furthermore, an amplifier circuit suitable for amplifying an image signal obtained from, for example, a CCD can be obtained by using a clamp circuit as a reference voltage source and inserting a clamp switch circuit between the input conductor and the clamp circuit.

  A plurality of variable capacitance circuits may be provided in parallel to realize a large number of capacitance values.

  In this case, since the number of control signals increases, a control unit that inputs a command from the outside, decodes the command, and generates a control signal for controlling the variable voltage source of the plurality of variable capacitance circuits according to the decoded command. It is preferable to provide it.

  According to the present invention, since two types of capacitance can be given to the electronic circuit with one MOS capacitor, the layout area can be reduced.

  Embodiments according to the present invention will be described below. In addition, when showing the same element in several drawing, the same referential mark is attached | subjected.

<Principle>
First, before describing specific embodiments, the principle will be schematically described.

  FIG. 1 is a diagram for explaining the principle of the integrated circuit 1 including the variable capacitance circuit 60 according to the present embodiment. As shown in FIG. 1A, an integrated circuit 1 includes a coupling capacitor 10 to which an input signal is applied to one end, a variable capacitance circuit 60 connected between the other end of the coupling capacitor 10 and a ground conductor, The electronic circuit 40 includes an input terminal connected to a node 50 (hereinafter referred to as an “input node”) between the coupling capacitor 10 and the variable capacitance circuit 60.

  The variable capacitance circuit 60 is obtained by connecting a capacitor 20 having terminals 22 and 24 and a two-stage variable voltage source 30 in series. Terminal 22 of capacitor 20 is connected to input node 50. The two-stage variable voltage source 30 has a common terminal connected to the terminal 24 of the capacitor 20, a two-select switch 32 having two select contacts, and an anode connected to the two select contacts of the two-select switch 32, And constant voltage sources 34 and 36 whose cathodes are grounded. The constant voltage sources 34 and 36 supply voltages VH and VL which are different from the ground conductor in the direction of the capacitor 20, respectively. Therefore, only one of the voltage sources 34 and 36 can be selected and connected to the terminal 24 of the capacitor 20 by controlling the switching signal to the 2-select switch 32.

  Since the capacitor 20 is mounted on the integrated circuit 1, it is a surface mount capacitor. In general, a surface mount capacitor is used as a surface mount capacitor having a structure shown in FIG. 2A and a relatively small capacitance per unit area. However, as shown in FIG. 1B or a capacitor having a structure as shown in FIG. 1B, and the capacitance per unit area is relatively large, and the capacitance changes greatly in the vicinity of the applied voltage of approximately 0 volts as shown in FIG. 1C. One of the MOS capacitors. According to the present invention, the latter MOS capacitor is used as the capacitor 20. In addition, the electronic circuit 40 includes the reference voltage source 41 between the ground conductor and the input node 50, thereby applying a constant voltage Vcl to the input node 50 in the direction of the wavy arrow.

  FIG. 1B is a longitudinal sectional view of a laminated thin film constituting the MOS capacitor 20 of the surface-mounted electronic circuit 1, and FIG. 1C is a voltage / capacitance characteristic of the MOS capacitor 20 and variable according to the present invention. FIG. 3 is a diagram illustrating an operation principle of a capacitive circuit 60.

  In FIG. 1B, the MOS capacitor 20 includes an N-type semiconductor substrate 24, a gate oxide film 23 formed on the substrate 24 as an insulator, and a polysilicon gate electrode 22 formed on the gate oxide film 23. Then, a capacitance C2 is provided between the semiconductor substrate 24 and the polysilicon gate electrode 22. In the MOS capacitor 20 configured in this way, when the voltage applied to both ends thereof is represented by Vc2 with reference to the direction of the arrow (the direction from the semiconductor substrate 24 to the polysilicon gate electrode 22), the voltage Vc2 is changed. It changes like the Vc2-C2 curve of 1 (C).

  In this specification, “voltage expressed with reference to the direction of the arrow” is simply referred to as “voltage in the direction of the arrow”. For example, in FIG. 1B, “voltage Vc2 in the direction of the arrow” means a voltage obtained by subtracting Vb from Va (= Va−Vb), where Va and Vb are the potentials at the tip and rear ends of the arrow, respectively. To do.

  Again in FIG. 1C, the capacitance C2 of the MOS capacitor 20 is stabilized at a low capacitance Ca when the voltage Vc2 in the direction of the arrow of the MOS capacitor 20 is lower than the voltage −Vca close to the ground potential, and the voltage Vc2 is −Vca. When the voltage Vc2 is greater than or equal to Vcb, the capacitance Cb is much larger than Ca and is stabilized. Here, a range of −Vca or less of the voltage Vc2 applied to the MOS capacitor 20 is referred to as a “low-capacity operation region”, and a range of Vcb or more is referred to as a “high-capacity operation region”. Based on the above, the operation of the integrated circuit 1 will be described.

  Here, in order to avoid confusion in interpretation, it is assumed that the voltage Vcl in the direction of the broken line of the reference voltage source is a positive voltage, and the MOS capacitor 20 has its polysilicon gate electrode 22 connected to the input node 50. It is assumed that the semiconductor substrate 24 is connected to the two-stage variable voltage source 30. Under this assumption, the voltage VH in the direction from the negative electrode to the positive electrode of the voltage source 34 (hereinafter simply expressed as the voltage of the voltage source 34) VH2 of the MOS capacitor 20 falls within the high capacity operation region. And the voltage VL of the voltage source 36 is set so that the capacitance voltage Vc2 falls within the low operating region, whereby the capacitance C2 of the MOS capacitor 20 is set to one of the low capacitance Ca and the high capacitance Cb with a binary switching signal. Can be set. The subscripts H and L of the voltage values VH and VL indicate whether the voltage is for a high capacity Cb or a voltage for a low capacity Ca regardless of the level of the voltage value.

  As described above, the input node 50 is fixed to the voltage Vcl in a DC manner by the reference voltage source 41, but the AC component of the input signal is also applied to the input node 50 through the coupling capacitor 10. Therefore, if the upper limit of the amplitude of the AC component applied to the input node 50 is Vs, the voltage at the input node 50 may vary in the range of Vcl ± Vs. In a general application, even if the voltage Vc2 of the MOS capacitor 20 changes due to the voltage of the input node 50 changing in this way, the voltage Vc2 falls within the low-capacity operation region or the high-capacity operation region. It is preferable that the capacitance C2 of Ca remains unchanged as Ca or Cb. When the voltage from the ground conductor of the two-stage variable voltage source 30 toward the MOS capacitor 20 is v, Vc2 = Vcl−v. However, v = VL during low capacity operation and v = VH during high capacity operation. In order for the voltage Vc2 of the MOS capacitor 20 to fall within the low-capacity operation region even when the input signal changes + Vs during the low-capacity operation, it is necessary that Vc2 (= Vcl−VL) ≦ −Vca−Vs. In order for the voltage Vc2 of the MOS capacitor 20 to fall within the high-capacity operation region even with respect to the change −Vs of the input signal during the capacity operation, it is necessary that Vc2 (= Vcl−VH) ≧ Vcb + Vs. Therefore, the voltages VH and VL of the voltage sources 34 and 36 used for the two-stage variable voltage source 30 may be set within the range of the following equation even when various conditions other than the above are taken into consideration.

VL ≧ Vcl + Vca + Vs (2)
VH ≦ Vcl−Vcb−Vs (3)
In the above description, in order to simplify the description, the potential of the terminal on the opposite side of the input node 50 of the variable capacitance circuit 60 is grounded. However, the present invention is not limited to this, and in other cases, Equations (2) and (3) can be applied with the voltage in the direction of the dashed line of the variable capacitance circuit 60 as Vcl.

Further, in the above description, it is assumed that the potential of the input node 50 is higher than the potential of the ground conductor, that is, Vcl is positive, but the reverse is also possible. FIG. 3 is a diagram for explaining the structure (A) and the operation (B) of the variable capacitance circuit 60a when Vcl is negative. As shown in FIG. 3A, when Vcl <0, the MOS capacitor 20 of the variable capacitance circuit 60a is mounted in the opposite direction to that when Vcl> 0. That is, the polysilicon gate electrode 22 of the MOS capacitor 20 is connected to the two-stage variable voltage source 30, and the semiconductor substrate 24 is connected to the input node 50. In this case, the voltage of the MOS capacitor 20 is expressed as Vc2 on the basis of the arrow pointing in the opposite direction to the case of Vcl> 0. Therefore, Vc2 = − (Vcl−v), and v, VH, VL, and Vcl are all negative, that is, voltages in directions opposite to the respective arrows are positive. From the Vc2 · C2 curve of FIG. 3B, the equations (2) and (3) are as follows.

VL ≦ Vcl−Vca−Vs (4)
VH ≧ Vcl + Vcb + Vs (5)
Of course, also in this case, the potential at the rear end of the arrow of the voltage Vcl need not be zero.

  As described above, according to the principle of the present invention, in the circuit (60 or 60a) in which the MOS capacitor (20) and the two-stage variable voltage source (30) are connected in series, the high capacity constituting the two-stage variable voltage source. The voltages VH and VL of the operating power supply (34) and the low-capacity operating power supply (36) are set so that the voltage (Vc2) of the MOS capacitor falls within the high-capacity operating range and the low-capacitance operating range, regardless of the input signal. And switching the output voltage (v) of the two-stage variable voltage source to either VH or VL, thereby changing the capacitance (C2) of the MOS capacitor to either high capacitance (Ca) or low capacitance (Cb). Can be switched.

  Since FIG. 1 shows the circuit 1 mounted on one IC chip, any number of other arbitrary circuits may be mounted on the same chip before, after, or before and after the circuit 1. If the circuit 1 is a first-stage circuit of an IC chip to be mounted, the coupling capacitor 10 is provided on the surface from the viewpoint of giving design freedom to the user or a designer as a user and reducing the layout area. It is preferable not to mount but externally.

  Hereinafter, preferred embodiments will be described. The above principle is effective for all of the following embodiments.

[First Embodiment]
FIG. 4 is a circuit diagram showing an integrated circuit 1a in which the variable gain amplifier 2 according to the first embodiment is integrated.

  Compared with the integrated circuit 1 in FIG. 1A, the integrated circuit 1a in FIG. 4 is replaced with a voltage amplifier 40a with an input clamp, a variable capacitance circuit is replaced with 60 to 60b, and an input line for a switching signal is used. This is the same except that a buffer inverter 321 is inserted and a buffer inverter 47 for supplying a clamp pulse to the voltage amplifier 40a with input clamp is added. However, assuming that it is the first stage of an IC in which the amplifier 2 is mounted, the variable gain amplifier 2 does not include the coupling capacitor 10.

  The voltage amplifier with input clamp 40a includes a clamp circuit 41a instead of the reference voltage source 41, and further includes an N-MOS transistor 42 whose gate and drain are connected to the power source V, and a gate connected to the input node 50, and a drain. Is composed of a common source N-MOS transistor 43 connected to the source of the transistor 42. A connection node between the source of the transistor 42 and the drain of the transistor 43 is the voltage amplifier 40a, that is, the output terminal To of the variable gain amplifier 2. The clamp circuit 41 a has a cathode electrode grounded, a DC voltage source 45 that provides a clamp voltage Vcl, a first contact (source or drain) connected to the input node 50, and a second contact connected to the anode of the DC voltage source 45. The clamp switch (N-MOS transistor) 46 is connected to the terminal and the control terminal (gate) is connected to the output terminal of the inverter 47. The open end of the coupling capacitor 10 is a signal input terminal Ti. The input terminal of the inverter 47 is connected to the clamp switch control terminal Tcl.

  N-MOS transistor 43 inverts and amplifies the voltage applied from input node 50. The transistor 42 serves as a constant current source that supplies current to the drain of the N-MOS transistor 43. The transistor 46 that is a clamp switch is turned on only when the voltage of the input node 50 is set, and is controlled to be turned off during a period in which the N-MOS transistor 43 operates as an inverting amplifier.

  The variable capacitance circuit 60b of FIG. 4 is the same as the variable capacitance circuit 60 of FIG. 1A except that the two-stage variable voltage source is changed from 30 to 30a. In the two-stage variable voltage source 30a, the voltage VH of the voltage source 34 is 0 volts, that is, the short-circuit line 34a, and the two-select switch 32 is replaced with two open / close switches (N-MOS transistors) 322 and 324 and one inverter 323. Except for this point, it is the same as the two-stage variable voltage source 30. Specifically, the first contacts (source or drain) of the open / close switches 322 and 324 are both connected to the input node 50. The second contact of the switch 322 is grounded by the short circuit line 34 a, and the second contact of the switch 324 is connected to the anode of the voltage source 36. The control terminal (gate) of the switch 322 is connected to the output of the buffer inverter 321 and the input of the inverter 323. The control terminal of the switch 324 is connected to the output of the inverter 323. The input of the buffer inverter 321 is connected to the gain switching terminal Tg.

  The operation of the variable gain amplifier 2 configured as described above will be described. FIG. 5 is an equivalent circuit diagram showing only a portion necessary for explaining the operation of the circuit 1a when the gain switching terminal Tg is low, that is, when the switch 322 is on and the switch 324 is off. In this case, since the output of the two-stage variable voltage source 30a is 0 volt (ground), the voltage Vc2 of the MOS capacitor 20 is Vcl. In the circuit 2, the clamp voltage Vcl is determined so that the AC component change range 2Vs of the input signal enters the linear operation region of the amplification transistor 43. Therefore, Vcl is larger than Vcb + Vs (see FIG. 1C). Set to Therefore, since a voltage exceeding Vcb + Vs is applied to the MOS capacitor 20, the capacitance C2 of the MOS capacitor 20 is Ca.

  FIG. 6 is an equivalent circuit diagram showing only a portion necessary for explaining the operation of the circuit 1a when the gain switching terminal Tg is high, that is, when the switch 322 is off and the switch 324 is on. In this case, since the output of the two-stage variable voltage source 30a is VL volts, the voltage Vc2 of the MOS capacitor 20 is Vcl-VL. Therefore, by setting the voltage value VL so that the voltage value VL of the voltage source 36 satisfies the expression (2), a voltage lower than − (Ca + Vs) is applied to the MOS capacitor 20. The capacitance C2 of the MOS capacitor 20 is a low capacitance Cb.

  From the above results, the amplification gain β from the input terminal Ti to the output terminal To is the MOS capacitor, as is apparent from a comparison between the case where Ca is substituted for C2 in the above formula (1) and the case where Cb is substituted. 20 increases for lower Ca and decreases for higher Cb.

  Thus, the variable gain amplifier 2 including the variable capacitance circuit 60b of the present invention can switch the amplification gain β of the entire circuit by switching the capacitance of a single capacitor of the variable capacitance circuit 60b by a gain switching signal. it can.

  The integrated circuit 1b of FIG. 11 shows a configuration that further embodies the two-stage variable voltage source 30a of the variable capacitance circuit 60b shown in FIG. The variable gain amplifier circuit 2a in FIG. 11 is the same as the variable gain amplifier circuit 2 in FIG. 4 except for the configuration of the two-stage variable voltage source 30a. The same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 11, the two-stage variable voltage source 30c includes switches 322 and 324, an inverter 323, a short circuit line 34a that short-circuits the switch 322 and the ground potential, and a voltage source 36a. The voltage source 36a includes transistors 325 and 326 connected in series between the power supply voltage V and the ground potential. Thus, the voltage VL is generated by dividing the voltage between the power supply voltage V and the ground potential.

  The gain variable amplifier circuit configured as described above can reduce the layout area for one capacitor as compared with the conventional example shown in FIG. Two transistors are used to realize the voltage source VL, but the layout area of the two transistors is smaller than the layout area required for one capacitor. Therefore, the layout area can be reduced as compared with the conventional example shown in FIG.

  An integrated circuit 1c in FIG. 12 shows a variable capacitance circuit 60e that further reduces the layout area. Similarly to FIG. 11, the variable gain amplifier circuit 2b of FIG. 12 is the same as the variable gain amplifier circuit 2 of FIG. 4 except for the configuration of the two-stage variable voltage source 30a. Further, the two-stage variable voltage source 30d in FIG. 12 is the same as the two-stage variable voltage source 30a in FIG. Therefore, the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 12, the voltage of the voltage source 36 is V volts, that is, a short-circuit line 36b to the power supply voltage. Therefore, the switch 324 is connected to the power supply voltage V by the short-circuit line 36b. The variable capacitance circuit configured as described above can reduce the layout area because the transistor for realizing the voltage source VL is not required as compared with the variable capacitance circuit shown in FIG. That is, according to FIG. 12, a variable capacitance circuit having two types of capacitance values can be realized with one capacitor, two switches, and a wiring for connecting the switch and the ground potential or power supply voltage. Therefore, the layout area can be further reduced as compared with the conventional example shown in FIG.

[Second Embodiment]
FIG. 7 shows a circuit 60c in which a switch (N-MOS transistor) 62 is added to the variable capacitance circuit 60b. The variable capacitance circuit 60c shown in the figure has a switch 62 inserted between the input node 50 and the variable capacitance circuit 60b. A control signal Gmax / is given to the control terminal (gate) of the switch 62. When the control signal Gmax / is low, the switch 62 is turned off and the amplification gain β is maximized. When the control signal Gmax / is high, the switch 62 is turned off, and the amplification gain β can be switched in two steps by the control signal Tg as described above. Thus, in the second embodiment, the amplification gain β can be switched in three stages with a single MOS capacitor.

[Third Embodiment]
In each of the above embodiments, the example in which the two-stage variable voltage source 30a is used to control the voltage Vc2 of the MOS capacitor 20 has been described. However, in the third embodiment, the voltage is changed to the two-stage variable voltage source 30a. A variable voltage source 30b (FIG. 9) that can be changed to any value within a predetermined range is provided. That is, in the case of the third embodiment, the variable voltage source 30b is connected to one terminal 24 of the capacitor C2.

  According to the third embodiment, the voltage applied from the variable voltage source 30b to the one terminal 24 of the capacitor C2 is set to an arbitrary value in the vicinity of 0 V (that is, set to an arbitrary value of −Vca to Vcb). Thus, the capacitance value given from the capacitor C2 to the voltage amplifier 40a can be finely adjusted to an arbitrary value. That is, the gain of the voltage amplifier 40a can be finely adjusted by one capacitor C2.

[Fourth Embodiment]
FIG. 8 is a circuit diagram showing an integrated circuit according to the fourth embodiment. In FIG. 8, a gain N-stage variable amplifier 2a includes M (= N−1) variable capacitance circuits 60 inserted in parallel between an input node and a ground conductor, and a voltage amplifier having an input terminal connected to the input node. 40a (see FIG. 4). When the switching signals Tg1, Tg2,..., TgM are all set high, the gain N-stage variable amplifier 2a has a minimum capacitance between the input node and the ground conductor of M · Ca, and the signal Tgj (j = 1). When (M) is set to low one by one, (Cb-Ca) is added, and the maximum is M · Cb. Therefore, the capacitance (that is, the amplification gain β) can be switched to the (M + 1) stage.

  Of course, any of the variable capacitance circuits 60 a to 60 c may be used as the variable capacitance circuit 60. When M variable capacitance circuits 60c are used, the capacitance, that is, the gain, can be switched in (2M + 1) stages including the capacitance 0.

  In the case of this embodiment, since the number of control lines increases, it is inefficient to connect the control lines to the IC pins as they are. Therefore, a controller (not shown) is incorporated so that the switching level can be serially input as a command using a mode signal and a serial data line from the outside, and the controller decodes the command to control signals Tg1, Tg2,. .., preferably producing TgM and Tcl.

  As described above, the gain N-stage variable amplifier 2a according to this embodiment can realize a large number of amplification levels, and is therefore suitable for incorporation into a high-performance CCD digitizer or the like.

  Note that the gain N-stage variable amplifier 2a shown in FIG. 8 does not include the coupling capacitor 10 because it is assumed to be externally attached.

  The above is merely an embodiment for explaining the present invention. Accordingly, it is easy for those skilled in the art to make various changes, modifications, or additions to the above-described embodiments in accordance with the technical idea or principle of the present invention.

  For example, although the semiconductor substrate 24 of the MOS capacitor 20 is an N-type semiconductor substrate, a P-type semiconductor substrate may be used.

  In the variable capacitance circuits 60, 60a, and 60b of FIGS. 1A, 3A, and 4, the order of the MOS capacitor 20 and the two-stage variable voltage source 30 (or 30a) may be reversed.

  4 and 7, all the transistors are N-MOS transistors, but it is also possible to use P-MOS transistors. For example, if one of the N-MOS transistors 322 and 324 is a P-MOS transistor in the two-stage variable voltage source 30a of FIG. 4, the inverter 323 is unnecessary.

  For convenience of explanation, the term “input node” has been used so far. This refers to the entire conductor or conductor through which the input signal is transmitted via the coupling capacitor. In the claims, the term “connection conductor” is used. .

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the principle of the integrated circuit which concerns on embodiment of this invention, (A) is a circuit diagram which shows an integrated circuit notionally, (B) is a longitudinal cross-section of the laminated thin film which comprises a MOS capacitor FIG. 4C is a graph showing the voltage / capacitance characteristics of the MOS capacitor and the operation principle of the variable capacitance circuit. It is a graph which shows sectional drawing (A) and voltage capacity characteristic (B) which show the structure of the capacitor by a polysilicon gate. It is a graph explaining the structure (A) and operation | movement (B) of a variable capacitance circuit in case Vcl is negative. 1 is a circuit diagram showing an integrated circuit according to a first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram showing only a portion necessary for explaining the operation of the integrated circuit when the gain switching terminal Tg is low. FIG. 6 is an equivalent circuit diagram showing only a portion necessary for explaining the operation of the integrated circuit when the gain switching terminal Tg is high. FIG. 6 is a circuit diagram of only a part of an integrated circuit according to a second embodiment of the present invention. FIG. 10 is a circuit diagram of only a part of an integrated circuit according to a fourth embodiment of the present invention. FIG. 6 is a circuit diagram of only a part of an integrated circuit according to a third embodiment of the present invention. It is a circuit diagram which shows the variable gain amplifier by a prior art. It is a modification of the integrated circuit which concerns on the 1st Embodiment of this invention. It is a 2nd modification of the integrated circuit which concerns on the 1st Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit 2, 2a Variable gain amplifier 10 Coupling capacitor 20 MOS capacitor 30, 30a, 30b, 30c, 30d Two-stage variable voltage source 32 2 selection switch 34 Voltage source (VH)
36 Voltage source (VL)
40 Electronic circuit 41 Reference voltage source 50 Input conductor (input node)
60, 60a, 60b, 60c variable capacitance circuit

Claims (16)

In the variable capacitance circuit that can switch the electrostatic capacitance given to the voltage amplification circuit,
A MOS capacitor that provides capacitance to the voltage amplification circuit;
An applied voltage switching means for switching the capacitance applied from the MOS capacitor to the voltage amplification circuit by changing the voltage applied to the MOS capacitor and switching the capacitance of the MOS capacitor;
The variable capacitance circuit is an amplification gain switching circuit that switches an amplification gain of the voltage amplification circuit by switching an electrostatic capacitance to be given to the voltage amplification circuit ,
The MOS capacitor exhibits a first constant capacitance when the applied voltage is in a first region lower than a first negative threshold voltage, and a second region in which the applied voltage is higher than a second positive threshold voltage Presents a second constant volume higher than the first constant volume,
The control signal is a binary signal;
The variable voltage source outputs one of a first voltage and a second voltage different from the first voltage according to the control signal, and the first voltage is a value of the input signal. The applied voltage is set so as to be within the first region regardless of a change, and the second voltage is set so that the applied voltage is within the second region regardless of the change of the input signal. A variable capacitance circuit. In a variable capacitance circuit that can switch the capacitance to be given to other electronic circuits,
A MOS capacitor that provides capacitance to the electronic circuit;
Application voltage switching means for switching the capacitance applied from the MOS capacitor to the electronic circuit by changing the voltage applied to the MOS capacitor and switching the capacitance of the MOS capacitor;
The electronic circuit is connected to one end of the variable capacitance circuit, receives an input signal through a coupling capacitor having one end connected to a connection conductor that performs the connection, and is connected in parallel to the variable capacitance circuit and the connection A reference voltage source for applying a predetermined DC voltage to the conductor;
The applied voltage switching circuit is a variable voltage source that is connected in series to the MOS capacitor and that provides an output voltage according to a given control signal ;
The variable voltage source is:
A first voltage source for providing the first voltage;
A second voltage source for providing the second voltage;
A variable capacitance circuit comprising a two-select switch circuit that connects only one of the first voltage source and the second voltage source to the MOS capacitor in response to the control signal. The variable capacitance circuit according to claim 2, wherein the variable voltage source can output an arbitrary voltage within a predetermined range in accordance with the control signal. The MOS capacitor exhibits a first constant capacitance when the applied voltage is in a first region lower than a first negative threshold voltage, and a second region in which the applied voltage is higher than a second positive threshold voltage Presents a second constant volume higher than the first constant volume,
The control signal is a binary signal;
The variable voltage source outputs one of a first voltage and a second voltage different from the first voltage according to the control signal, and the first voltage is a value of the input signal. The applied voltage is set so as to be within the first region regardless of a change, and the second voltage is set so that the applied voltage is within the second region regardless of the change of the input signal. The variable capacitance circuit according to claim 2 , wherein the variable capacitance circuit is provided. The first voltage ≧ the predetermined DC voltage−the first threshold voltage + the allowable voltage for the change, and the second voltage ≦ the predetermined DC voltage−the second threshold voltage−the allowable voltage for the change. The variable capacitance circuit according to claim 2 , wherein the first voltage and the second voltage are set so that In an integrated circuit comprising: an electronic circuit that processes a signal input from a signal input terminal; and a variable capacitance circuit that can switch a capacitance applied to the electronic circuit.
The variable capacitance circuit is:
A MOS capacitor that provides capacitance to the electronic circuit;
Application voltage switching means for switching the capacitance applied from the MOS capacitor to the electronic circuit by changing the voltage applied to the MOS capacitor and switching the capacitance of the MOS capacitor;
The electronic circuit is connected to one end of the variable capacitance circuit, and receives an input signal through a coupling capacitor having one end connected to a connection conductor that performs the connection,
The integrated circuit is further integrated with a reference voltage source that is connected in parallel with the variable capacitance circuit and applies a predetermined DC voltage to the connection conductor,
The applied voltage switching means is a variable voltage source connected in series to the MOS capacitor and giving an output voltage according to a given control signal,
The MOS capacitor exhibits a first constant capacitance when the applied voltage is in a first region lower than a first negative threshold voltage, and a second region in which the applied voltage is higher than a second positive threshold voltage Presents a second constant volume higher than the first constant volume,
The control signal is a binary signal;
The variable voltage source outputs one of a first voltage and a second voltage different from the first voltage according to the control signal, and the first voltage is a value of the input signal. The applied voltage is set so as to be within the first region regardless of a change, and the second voltage is set so that the applied voltage is within the second region regardless of the change of the input signal. An integrated circuit characterized by that. The electronic circuit is a voltage amplification circuit;
The integrated circuit according to claim 6, wherein the variable capacitance circuit is an amplification gain switching circuit that switches an amplification gain of the voltage amplification circuit by switching an electrostatic capacitance applied to the voltage amplification circuit. The integrated circuit according to claim 6, wherein the variable voltage source can output an arbitrary voltage within a predetermined range in accordance with the control signal. The first voltage ≧ the predetermined DC voltage−the first threshold voltage + the allowable voltage for the change, and the second voltage ≦ the predetermined DC voltage−the second threshold voltage−the allowable voltage for the change. The integrated circuit according to any one of claims 6 to 8, wherein the first voltage and the second voltage are set such that The variable voltage source is:
A first voltage source for providing the first voltage;
A second voltage source for providing the second voltage;
10. A two-select switch circuit for connecting only one of the first voltage source and the second voltage source to the MOS capacitor according to the control signal. 2. The integrated circuit according to item 1. The integrated circuit according to claim 10, wherein an output voltage of the first voltage source is zero. The two-option switch circuit is
Two MOS transistors in which one of the source electrode and the drain electrode is connected to each other to form a common terminal, and the other forms two alternative contact terminals;
An inverting circuit connected between the gate electrodes of the two MOS transistors;
The integrated circuit according to claim 10 or 11, characterized by comprising: The variable capacitance circuit further includes open / close switch means that is inserted between a series circuit of the MOS capacitor and the variable voltage source and the connection conductor and opens and closes in response to a second binary control signal. An integrated circuit according to any one of claims 8 to 12. The reference voltage source is a clamp circuit;
The integrated circuit according to claim 7, further comprising a clamp switch circuit inserted between the connection conductor and the clamp circuit. 14. The integrated circuit according to claim 6, wherein a plurality of the variable capacitance circuits are provided in parallel. The apparatus further comprises control means for inputting a command from the outside, decoding the command, and generating the control signal for controlling the variable voltage source of the plurality of variable capacitance circuits according to the command. Item 16. The integrated circuit according to Item 15.

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